x86/msr: Clean up the MSR_EFER constants

There are no remaining users of the bit position constants.  Move the used
constants into the cleaned-up area of msr-index.h and apply appropriate style.

Rename EFER_NX to EFER_NXE to match both the Intel and AMD specs.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 150f7f90a26506e7899e2a95341c42b18c020983..dd1bea0d10b3e813595204dc701ffec5a22b75d5 100644 (file)
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -639,7 +639,7 @@ trampoline_setup:
         /* Check for NX. Adjust EFER setting if available. */
         bt      $cpufeat_bit(X86_FEATURE_NX), %edx
         jnc     1f
-        orb     $EFER_NX >> 8, 1 + sym_esi(trampoline_efer)
+        orb     $EFER_NXE >> 8, 1 + sym_esi(trampoline_efer)
 1:
 
         /* Check for availability of long mode. */

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index abf8e206d76be9637d6781dd525723abfb2da20c..9b011c344636bc2ac4a4bbbfa5f7638fd094cd9c 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -270,14 +270,14 @@ static void early_init_intel(struct cpuinfo_x86 *c)
        if (disable) {
                wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
                bootsym(trampoline_misc_enable_off) |= disable;
-               bootsym(trampoline_efer) |= EFER_NX;
+               bootsym(trampoline_efer) |= EFER_NXE;
        }
 
        if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
                printk(KERN_INFO "revised cpuid level: %d\n",
                       cpuid_eax(0));
        if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
-               write_efer(read_efer() | EFER_NX);
+               write_efer(read_efer() | EFER_NXE);
                printk(KERN_INFO
                       "re-enabled NX (Execute Disable) protection\n");
        }

diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index fb217031ff0e342efa6eecfbb3c2a06e19c1a2fa..9b0cc29aae8080b8d3e4c7406fb8d1606e8de325 100644 (file)
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -692,7 +692,7 @@ static void __init efi_arch_cpu(void)
         caps[cpufeat_word(X86_FEATURE_SYSCALL)] = cpuid_edx(0x80000001);
 
         if ( cpu_has_nx )
-            trampoline_efer |= EFER_NX;
+            trampoline_efer |= EFER_NXE;
     }
 }
 

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 5086773e5c8b89eaa0dafe389e2e2acf527b3c15..7b48a1b925bbb18bce9503ee5d95a0f43806174e 100644 (file)
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -952,8 +952,8 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
     if ( (value & EFER_LMA) && (!(value & EFER_LME) || !cr0_pg) )
         return "LMA/LME/CR0.PG inconsistency";
 
-    if ( (value & EFER_NX) && !p->extd.nx )
-        return "NX without feature";
+    if ( (value & EFER_NXE) && !p->extd.nx )
+        return "NXE without feature";
 
     if ( (value & EFER_SVME) && (!p->extd.svm || !nestedhvm_enabled(d)) )
         return "SVME without nested virt";

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 8dc92c8b9f96278b8513a5a5ef61935cbcb2ff1e..309912a23499faafea80ebfda277b5833e14ab41 100644 (file)
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -563,8 +563,8 @@ static void svm_update_guest_efer(struct vcpu *v)
     if ( paging_mode_shadow(v->domain) )
     {
         /* EFER.NX is a Xen-owned bit and is not under guest control. */
-        guest_efer &= ~EFER_NX;
-        guest_efer |= xen_efer & EFER_NX;
+        guest_efer &= ~EFER_NXE;
+        guest_efer |= xen_efer & EFER_NXE;
 
         /*
          * CR0.PG is a Xen-owned bit, and remains set even when the guest has

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index e09b7e3af9007a29e3146166f110533b926cb0a4..b0a42d05f86ac3da259f95d3250e14e97bbc6bc5 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1623,8 +1623,8 @@ static void vmx_update_guest_efer(struct vcpu *v)
          * When using shadow pagetables, EFER.NX is a Xen-owned bit and is not
          * under guest control.
          */
-        guest_efer &= ~EFER_NX;
-        guest_efer |= xen_efer & EFER_NX;
+        guest_efer &= ~EFER_NXE;
+        guest_efer |= xen_efer & EFER_NXE;
     }
 
     if ( !vmx_unrestricted_guest(v) )

diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
index 4a8fb571de4285cb88423d300d246df11a649e43..7e842f2dc2ba6c41f3b858d55cfa170c9aa81f05 100644 (file)
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -376,7 +376,7 @@ int hvm_get_param(struct domain *d, uint32_t index, uint64_t *value);
 #define hvm_smap_enabled(v) \
     (hvm_paging_enabled(v) && ((v)->arch.hvm.guest_cr[4] & X86_CR4_SMAP))
 #define hvm_nx_enabled(v) \
-    ((v)->arch.hvm.guest_efer & EFER_NX)
+    ((v)->arch.hvm.guest_efer & EFER_NXE)
 #define hvm_pku_enabled(v) \
     (hvm_paging_enabled(v) && ((v)->arch.hvm.guest_cr[4] & X86_CR4_PKE))
 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 903923e5a58b3ed08f82d09c8350450ee205369d..3fe14b820c3898131d725c0f0b7332ced02baee2 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -119,6 +119,17 @@
 #define  PASID_PASID_MASK                   0x000fffff
 #define  PASID_VALID                        (_AC(1, ULL) << 31)
 
+#define MSR_EFER                            0xc0000080 /* Extended Feature Enable Register */
+#define  EFER_SCE                           (_AC(1, ULL) <<  0) /* SYSCALL Enable */
+#define  EFER_LME                           (_AC(1, ULL) <<  8) /* Long Mode Enable */
+#define  EFER_LMA                           (_AC(1, ULL) << 10) /* Long Mode Active */
+#define  EFER_NXE                           (_AC(1, ULL) << 11) /* No Execute Enable */
+#define  EFER_SVME                          (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */
+#define  EFER_FFXSE                         (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */
+
+#define EFER_KNOWN_MASK \
+    (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE)
+
 #define MSR_K8_SYSCFG                       0xc0010010
 #define  SYSCFG_MTRR_FIX_DRAM_EN            (_AC(1, ULL) << 18)
 #define  SYSCFG_MTRR_FIX_DRAM_MOD_EN        (_AC(1, ULL) << 19)
@@ -145,7 +156,6 @@
  */
 
 /* x86-64 specific MSRs */
-#define MSR_EFER               0xc0000080 /* extended feature register */
 #define MSR_STAR               0xc0000081 /* legacy mode SYSCALL target */
 #define MSR_LSTAR              0xc0000082 /* long mode SYSCALL target */
 #define MSR_CSTAR              0xc0000083 /* compat mode SYSCALL target */
@@ -155,24 +165,6 @@
 #define MSR_SHADOW_GS_BASE     0xc0000102 /* SwapGS GS shadow */
 #define MSR_TSC_AUX            0xc0000103 /* Auxiliary TSC */
 
-/* EFER bits: */
-#define _EFER_SCE              0  /* SYSCALL/SYSRET */
-#define _EFER_LME              8  /* Long mode enable */
-#define _EFER_LMA              10 /* Long mode active (read-only) */
-#define _EFER_NX               11 /* No execute enable */
-#define _EFER_SVME             12 /* AMD: SVM enable */
-#define _EFER_FFXSE            14 /* AMD: Fast FXSAVE/FXRSTOR enable */
-
-#define EFER_SCE               (1<<_EFER_SCE)
-#define EFER_LME               (1<<_EFER_LME)
-#define EFER_LMA               (1<<_EFER_LMA)
-#define EFER_NX                        (1<<_EFER_NX)
-#define EFER_SVME              (1<<_EFER_SVME)
-#define EFER_FFXSE             (1<<_EFER_FFXSE)
-
-#define EFER_KNOWN_MASK                (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \
-                                EFER_SVME | EFER_FFXSE)
-
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0              0x000000c1
 #define MSR_IA32_A_PERFCTR0            0x000004c1