arm: Handle booting on SMP platforms

Make all non-boot CPUs wait forever instead of trying to boot in parallel.

Signed-off-by: Tim Deegan <tim@xen.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Committed-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S
index 48f8f3fd8a5a2b416e331de9a7459ad7f8084351..5b5034b7bf342e649868b2e1fdfcc12798200db7 100644 (file)
--- a/xen/arch/arm/head.S
+++ b/xen/arch/arm/head.S
@@ -61,6 +61,19 @@ start:
        add   r8, r10                /* r8 := paddr(DTB) */
 #endif
 
        add   r8, r10                /* r8 := paddr(DTB) */
 #endif
 

+       /* Are we the boot CPU? */
+       mrc   CP32(r0, MPIDR)
+       tst   r0, #(1<<31)           /* Multiprocessor extension supported? */
+       beq   boot_cpu
+       tst   r0, #(1<<30)           /* Uniprocessor system? */
+       bne   boot_cpu
+       bics  r0, r0, #(0xff << 24)  /* Ignore flags */
+       beq   boot_cpu               /* If all other fields are 0, we win */
+
+1:     wfi
+       b     1b
+       
+boot_cpu:

 #ifdef EARLY_UART_ADDRESS
        /* Say hello */
        ldr   r11, =EARLY_UART_ADDRESS  /* r11 := UART base address */
 #ifdef EARLY_UART_ADDRESS
        /* Say hello */
        ldr   r11, =EARLY_UART_ADDRESS  /* r11 := UART base address */

diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index d61ea88c5c6d0e7e46c9fead7d664e4bd0f79545..f6e71eb8f972b0edee98ad5731c9373a072b2c44 100644 (file)
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -91,6 +91,7 @@
 /* Coprocessor 15 */
 
 /* CP15 CR0: CPUID and Cache Type Registers */
 /* Coprocessor 15 */
 
 /* CP15 CR0: CPUID and Cache Type Registers */

+#define MPIDR           p15,0,c0,c0,5   /* Multiprocessor Affinity Register */

 #define ID_PFR0         p15,0,c0,c1,0   /* Processor Feature Register 0 */
 #define ID_PFR1         p15,0,c0,c1,1   /* Processor Feature Register 1 */
 #define ID_DFR0         p15,0,c0,c1,2   /* Debug Feature Register 0 */
 #define ID_PFR0         p15,0,c0,c1,0   /* Processor Feature Register 0 */
 #define ID_PFR1         p15,0,c0,c1,1   /* Processor Feature Register 1 */
 #define ID_DFR0         p15,0,c0,c1,2   /* Debug Feature Register 0 */