x86/AMD: expose HWCR.TscFreqSel to guests

Linux has been warning ("firmware bug") about this bit being clear for a
long time. While writable in older hardware it has been readonly on more
than just most recent hardware. For simplicitly report it always set (if
anything we may want to log the issue ourselves if it turns out to be
clear on older hardware) on CPU families 10h and up (in family 0fh the
bit is part of a larger field of different purpose).

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Ian Jackson <iwj@xenproject.org>

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 8ed0b4e9825a2c4f9cf7b717b2e9592a6936c4f7..0ebcb04259e5e6d34f0113af87b6e9c90edf6429 100644 (file)
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -315,6 +315,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
         *val = msrs->tsc_aux;
         break;
 
         *val = msrs->tsc_aux;
         break;
 

+    case MSR_K8_HWCR:
+        if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
+            goto gp_fault;
+        *val = get_cpu_family(cp->basic.raw_fms, NULL, NULL) >= 0x10
+               ? K8_HWCR_TSC_FREQ_SEL : 0;
+        break;
+

     case MSR_AMD64_DE_CFG:
         if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             goto gp_fault;
     case MSR_AMD64_DE_CFG:
         if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             goto gp_fault;

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 1f5a5d0e385a0494a14ffb4c47fd513af8f4dbfa..f2e34dd22bd8e496aa3681cd16f6eb1e9ffc9760 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -287,6 +287,8 @@
 
 #define MSR_K7_HWCR                    0xc0010015
 #define MSR_K8_HWCR                    0xc0010015
 
 #define MSR_K7_HWCR                    0xc0010015
 #define MSR_K8_HWCR                    0xc0010015

+#define K8_HWCR_TSC_FREQ_SEL           (1ULL << 24)
+

 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K8_PSTATE_LIMIT            0xc0010061
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K8_PSTATE_LIMIT            0xc0010061