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target/mips: Amend CP0 WatchHi register implementation
authorYongbok Kim <yongbok.kim@mips.com>
Fri, 20 Dec 2019 09:34:09 +0000 (10:34 +0100)
committerAleksandar Markovic <amarkovic@wavecomp.com>
Wed, 29 Jan 2020 18:28:52 +0000 (19:28 +0100)
commitfeafe82cc2289a31b3e3f11dc76f3539ea22d670
treeb22339b97d2f69b7e083df84b6899e42b2a2ba8ctree
parent6cdda0ff4bad7edbb4c94a52234138bf2ac9a6b6commit | diff
target/mips: Amend CP0 WatchHi register implementation

WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.

Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1579883929-1517-4-git-send-email-aleksandar.markovic@rt-rk.com>
target/mips/cpu.h diff | blob | blame | history
target/mips/helper.h diff | blob | blame | history
target/mips/machine.c diff | blob | blame | history
target/mips/op_helper.c diff | blob | blame | history
target/mips/translate.c diff | blob | blame | history
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