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(parent: 41e0c70) | patch
target-mips: fix FPU in 64-bit mode
authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 28 Mar 2009 22:22:50 +0000 (22:22 +0000)
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 28 Mar 2009 22:22:50 +0000 (22:22 +0000)
commitf364515c836fcc7caa1606a8c27edae25f27a6ce
tree544c9948fa5c44b81f5642b3290c4cf7753ab6b5tree
parent41e0c701599de298beec6853f9bb055365e51174commit | diff
target-mips: fix FPU in 64-bit mode

TCG does not allow the same memory location to be aliased in two
different global registers, fpu_fpr32 and fpu_fpr64.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6915 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips/translate.c diff | blob | history
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