]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Introduce extension implied rules definition
authorFrank Chang <frank.chang@sifive.com>
Tue, 25 Jun 2024 11:46:24 +0000 (19:46 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 13:06:00 +0000 (23:06 +1000)
commitf04f7709203c539bec29258288ba846b993db8e3
treec7eb6d01ba0b43f430655564a23e1d39086ce00f
parentc165408779ae3a5aceddc8603471b1c20e58fcae
target/riscv: Introduce extension implied rules definition

RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offset of the extension defined in RISCVCPUConfig. 'ext' will also
serve as the key of the hash tables to look up the rule in the following
commit.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240625114629.27793-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h