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(parent: 068e538) | patch
target/xtensa: implement PREFCTL SR
authorMax Filippov <jcmvbkbc@gmail.com>
Mon, 18 Feb 2019 11:11:40 +0000 (03:11 -0800)
committerMax Filippov <jcmvbkbc@gmail.com>
Thu, 28 Feb 2019 12:43:22 +0000 (04:43 -0800)
commiteb3f4298c96d79a5a67b904c28f293864cc5ccc3
tree5cb370d2454e556508d48b6cedbdf84a13558ff2tree
parent068e538a54552289a58689f21c99ed3696e59961commit | diff
target/xtensa: implement PREFCTL SR

Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target/xtensa/cpu.h diff | blob | blame | history
target/xtensa/translate.c diff | blob | blame | history
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