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(parent: 617448a) | patch
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
authorAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Dec 2020 18:22:29 +0000 (10:22 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 18 Dec 2020 05:56:44 +0000 (21:56 -0800)
commitc0a635f3973d974befb954463287786fd988bb64
treeb06eb031a496452bcd61e464ccb707dad2d82289tree
parent617448a46b60c353fae0c645a024b628c1f9f700commit | diff
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
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