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(parent: fabbe7e) | patch
arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature
authorBertrand Marquis <bertrand.marquis@arm.com>
Mon, 13 Jun 2022 12:53:13 +0000 (13:53 +0100)
committerStefano Stabellini <stefano.stabellini@xilinx.com>
Thu, 16 Jun 2022 00:33:47 +0000 (17:33 -0700)
commit9ebd9550f6bbec7f3ae474ebaad5a6f119402b6c
treeb0f11618c028777db4a76c2a86374c2a07f1c9actree
parentfabbe7e0feae3bb2a93eba272e19bbb2baa12813commit | diff
arm: add ISAR2, MMFR0 and MMFR1 fields in cpufeature

Complete AA64ISAR2 and AA64MMFR[0-1] with more fields.
While there add a comment for MMFR bitfields as for other registers in
the cpuinfo structure definition.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
xen/arch/arm/include/asm/cpufeature.h diff | blob | blame | history
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