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(parent: ab20c5c) | patch
x86/amd: Try to set lfence as being Dispatch Serialising
authorAndrew Cooper <andrew.cooper3@citrix.com>
Wed, 14 Feb 2018 11:42:31 +0000 (12:42 +0100)
committerJan Beulich <jbeulich@suse.com>
Wed, 14 Feb 2018 11:42:31 +0000 (12:42 +0100)
commit8335c8aedacd9a50b4796afb533dc8205f2129e4
treed5d7540a7b9da97a9e6cfd082abffdcbdd171f11tree
parentab20c5c804ae814de9bed5f85d55fecc894dc78fcommit | diff
x86/amd: Try to set lfence as being Dispatch Serialising

This property is required for the AMD's recommended mitigation for Branch
Target Injection, but Xen needs to cope with being unable to detect or modify
the MSR.

This is part of XSA-254.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
master commit: fe3ee5530a8d0d0b6a478167125d00c40f294a86
master date: 2018-01-16 17:45:50 +0000
xen/arch/x86/cpu/amd.c diff | blob | blame | history
xen/include/asm-x86/cpufeature.h diff | blob | blame | history
xen/include/asm-x86/msr-index.h diff | blob | blame | history
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