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ARM: fix CPS masks (Vincent Palatin).
authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 19 Jul 2008 10:34:35 +0000 (10:34 +0000)
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 19 Jul 2008 10:34:35 +0000 (10:34 +0000)
commit7997d92f2c75cf56e8142be8e4c1fb5b8dbcc2a4
tree9b07fba4334e3de4d464ce5760febadd9e0697b2tree
parent22478e79f2793aa1bc7a5019ae2e48303573e0d5commit | diff
ARM: fix CPS masks (Vincent Palatin).

According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
target-arm/translate.c diff | blob | history
Obsolete Qemu-dm 3.3 stable branch