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(parent: c96fc9b) | patch
cadence_gem: Correct Marvell PHY SPCFC reset value
authorAlistair Francis <alistair.francis@xilinx.com>
Tue, 8 Sep 2015 16:38:45 +0000 (17:38 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 8 Sep 2015 16:38:45 +0000 (17:38 +0100)
commit7777b7a0ba27696ddf34a19818be17cc415551cc
tree91a900a534dd0d296da8dc1c376ede30ebb42024tree
parentc96fc9b52d0a318d8026a0bcaba204d319ad91e0commit | diff
cadence_gem: Correct Marvell PHY SPCFC reset value

Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: c795069e49040ff770fe2ece19dfe1791b729e22.1441316450.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/net/cadence_gem.c diff | blob | blame | history
osstest gate outputs for qemu