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target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 15 Feb 2023 02:05:34 +0000 (10:05 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 1 Mar 2023 23:17:52 +0000 (15:17 -0800)
commit732b902dd5803e3cb228424050300beffe097acf
treeb0bab96c6a0119400bbeae56a4b8718557706c3etree
parent3f4a5a5314b1d2d1fe910b87a3784743993003dacommit | diff
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

Check for Zve32f/Zve64d can overlap check for F/D.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
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