]> xenbits.xensource.com Git - qemu-xen.git/commit
RISC-V: Adding XTheadFmv ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Tue, 31 Jan 2023 20:20:12 +0000 (21:20 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 6 Feb 2023 22:19:23 +0000 (08:19 +1000)
commit578086ba2ffe4afb24b94975d75dfc02f8be1ee4
tree4b77ac4cb8f110ceb3ce65ebf01f5dd78aeceb85
parent95bd8daaafdff905ee4fa0620c097ad4eb2e8a13
RISC-V: Adding XTheadFmv ISA extension

This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn_trans/trans_xthead.c.inc
target/riscv/translate.c
target/riscv/xthead.decode