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target/riscv: Add the MPV and MTL mstatus bits
authorAlistair Francis <Alistair.Francis@wdc.com>
Sat, 20 Apr 2019 02:27:10 +0000 (02:27 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 24 May 2019 19:09:24 +0000 (12:09 -0700)
commit49aaa3e534f5422a56313bb93c1880e70fc1da7e
tree2c8d0addff82857db3ffb3534264520ad029994dtree
parent16fdb8ff64374ed51b246437e13043039a8eb9f9commit | diff
target/riscv: Add the MPV and MTL mstatus bits

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu_bits.h diff | blob | blame | history
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