]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Save counter values during countinhibit update
authorAtish Patra <atishp@rivosinc.com>
Thu, 11 Jul 2024 22:31:11 +0000 (15:31 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 18 Jul 2024 02:08:44 +0000 (12:08 +1000)
commit46023470e014234f3e15ec4497e003550bd7da0d
treee06daf6b6e3d2f0ed781bd9820e78d12c7bb1996
parentb2d7a7c7e4e30fb5341d38deac968de675f9419c
target/riscv: Save counter values during countinhibit update

Currently, if a counter monitoring cycle/instret is stopped via
mcountinhibit we just update the state while the value is saved
during the next read. This is not accurate as the read may happen
many cycles after the counter is stopped. Ideally, the read should
return the value saved when the counter is stopped.

Thus, save the value of the counter during the inhibit update
operation and return that value during the read if corresponding bit
in mcountihibit is set.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-8-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/csr.c
target/riscv/machine.c