]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Update default priority table for local interrupts
authorAnup Patel <apatel@ventanamicro.com>
Thu, 16 Jun 2022 03:15:43 +0000 (08:45 +0530)
committerAlistair Francis <alistair@alistair23.me>
Sun, 3 Jul 2022 00:03:20 +0000 (10:03 +1000)
commit435774992e82d2d16f025afbb20b4f7be9b242b0
treee4a70542226b11f3a1a5604c3809e6aafc0100ff
parentdf01af337f0cd48137ec67e207e3de5956acc379
target/riscv: Update default priority table for local interrupts

The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
   and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
   (not mandatory) priority assignments.

We update the default priority table and hviprio mapping as-per above.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c