]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Add additional xlen for address when MPRV=1
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 14 Jun 2023 03:25:46 +0000 (11:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 10 Jul 2023 12:29:14 +0000 (22:29 +1000)
commit3a610f5430f61bd67f0ac78ef40c8d3bd2b4f8ee
tree22a8ae8c1cd13d36c4e782b1f8bab5947dee7049
parent029f5feed6e5b7173788b7414af3e8aa32746344
target/riscv: Add additional xlen for address when MPRV=1

As specified in privilege spec:"When MPRV=1, load and store memory
addresses are treated as though the current XLEN were set to MPP’s
XLEN". So the xlen for address may be different from current xlen.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230614032547.35895-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/translate.c