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(parent: d3d93c6) | patch
target-mips: apply CP0.PageMask before writing into TLB entry
authorLeon Alrae <leon.alrae@imgtec.com>
Wed, 10 Dec 2014 12:36:39 +0000 (12:36 +0000)
committerYongbok Kim <yongbok.kim@imgtec.com>
Wed, 2 Aug 2017 21:18:11 +0000 (22:18 +0100)
commit2d1847ec1ca47fe82f1d8122409cedffdd3925d5
tree6e4a7fff26ff5c1e614ef891923c6c5509c5ecc7tree
parentd3d93c6c1eb0d94d2f203ac272629e6ebfc468a7commit | diff
target-mips: apply CP0.PageMask before writing into TLB entry

PFN0 and PFN1 have to be masked out with PageMask_Mask.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[Yongbok Kim:
  Added commit message]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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