]> xenbits.xensource.com Git - qemu-xen.git/commit
target-mips: Also apply the CP0.Status mask to MTTC0
authorMaciej W. Rozycki <macro@codesourcery.com>
Thu, 20 Nov 2014 11:15:34 +0000 (11:15 +0000)
committerLeon Alrae <leon.alrae@imgtec.com>
Tue, 16 Dec 2014 12:45:20 +0000 (12:45 +0000)
commit1d725ae952a14b30c84b7bc81b218b8ba77dd311
tree2b41de5acdbf012a5b877817e6a0bf0c5573fd27
parentcbb26c9a122c3f71fb53989817d406a2f6d08662
target-mips: Also apply the CP0.Status mask to MTTC0

Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places.  Also preserve the
current values of masked out bits.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/op_helper.c