]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
authorAnup Patel <apatel@ventanamicro.com>
Fri, 20 Jan 2023 12:59:48 +0000 (18:29 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 6 Feb 2023 22:19:22 +0000 (08:19 +1000)
commit14cb78bfaf4f99283252d9683ea4c0d97274ddea
tree1a12aa4f23feeec202270960e121e8f5a03119c5
parent2cfb3b6c9b78fd9d47a2934ba53293c73c680406
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP

Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c
target/riscv/time_helper.c