]> xenbits.xensource.com Git - qemu-xen.git/commit
target/riscv: Fix mstatus dirty mask
authorAlistair Francis <alistair.francis@wdc.com>
Fri, 23 Aug 2019 15:21:22 +0000 (08:21 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 17 Sep 2019 15:42:50 +0000 (08:42 -0700)
commit14115b91ddb106b3e05c74c26a056b253ca666ea
treeac7036c5ff2914eff1b4fcbc6f9b0b473540d1de
parenta9f37afab111ddbe394574bed5f69683439d46e6
target/riscv: Fix mstatus dirty mask

This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.

Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/csr.c