xenbits.xensource.com Git - qemu-xen.git/commit

]> xenbits.xensource.com Git - qemu-xen.git/commit

author	Richard Henderson <richard.henderson@linaro.org>
	Wed, 9 Dec 2020 19:58:39 +0000 (13:58 -0600)
committer	Richard Henderson <richard.henderson@linaro.org>
	Thu, 7 Jan 2021 15:09:06 +0000 (05:09 -1000)
commit	07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1
tree	a22f2b213b2cb96c8e0e30c69bca9edb00b678bc	tree
parent	d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5	commit \| diff

tcg: Introduce INDEX_op_qemu_st8_i32

Enable this on i386 to restrict the set of input registers
for an 8-bit store, as required by the architecture. This
removes the last use of scratch registers for user-only mode.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

15 files changed:

include/tcg/tcg-opc.h		diff \| blob \| blame \| history
tcg/README		diff \| blob \| blame \| history
tcg/aarch64/tcg-target.h		diff \| blob \| blame \| history
tcg/arm/tcg-target.h		diff \| blob \| blame \| history
tcg/i386/tcg-target.c.inc		diff \| blob \| blame \| history
tcg/i386/tcg-target.h		diff \| blob \| blame \| history
tcg/mips/tcg-target.h		diff \| blob \| blame \| history
tcg/optimize.c		diff \| blob \| blame \| history
tcg/ppc/tcg-target.h		diff \| blob \| blame \| history
tcg/riscv/tcg-target.h		diff \| blob \| blame \| history
tcg/s390/tcg-target.h		diff \| blob \| blame \| history
tcg/sparc/tcg-target.h		diff \| blob \| blame \| history
tcg/tcg-op.c		diff \| blob \| blame \| history
tcg/tcg.c		diff \| blob \| blame \| history
tcg/tci/tcg-target.h		diff \| blob \| blame \| history

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