1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Tue Apr 25 20:53:38 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Tue Apr 25 22:10:05 2006 -0600
     1.3 @@ -283,8 +283,13 @@ vmx_alt_itlb_miss_1:
     1.4  	and r18=0x10,r18	// bit 4=address-bit(61)
     1.5  	or r19=r17,r19		// insert PTE control bits into r19
     1.6  	;;
     1.7 +	movl r20=IA64_GRANULE_SHIFT<<2
     1.8  	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
     1.9  	;;
    1.10 +	mov cr.itir=r20
    1.11 +	;;
    1.12 +	srlz.i
    1.13 +	;;
    1.14  	itc.i r19		// insert the TLB entry
    1.15  	mov pr=r31,-1
    1.16  	rfi
    1.17 @@ -332,6 +337,11 @@ vmx_alt_dtlb_miss_1:
    1.18  	;;
    1.19  	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
    1.20  (p6) mov cr.ipsr=r24
    1.21 +	movl r20=IA64_GRANULE_SHIFT<<2
    1.22 +	;;
    1.23 +	mov cr.itir=r20
    1.24 +	;;
    1.25 +	srlz.i
    1.26  	;;
    1.27  (p7) itc.d r19		// insert the TLB entry
    1.28  	mov pr=r31,-1