ia64/xen-unstable

changeset 15891:fdd298b75fb5

[IA64] Performance enhancement for big-endian, 4k-pages, protection keys

Signed-off-by: Juergen Gross <juergen.gross@fujitsu-siemens.com>
author Alex Williamson <alex.williamson@hp.com>
date Mon Sep 17 13:26:19 2007 -0600 (2007-09-17)
parents 082faaa306e0
children b2a02f7ed849
files xen/arch/ia64/xen/faults.c xen/arch/ia64/xen/hyperprivop.S xen/arch/ia64/xen/ivt.S xen/arch/ia64/xen/mm.c xen/arch/ia64/xen/vcpu.c xen/arch/ia64/xen/vhpt.c
line diff
     1.1 --- a/xen/arch/ia64/xen/faults.c	Mon Sep 17 11:30:51 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/faults.c	Mon Sep 17 13:26:19 2007 -0600
     1.3 @@ -602,6 +602,9 @@ ia64_handle_reflection(unsigned long ifa
     1.4  		check_lazy_cover = 1;
     1.5  		vector = IA64_PAGE_NOT_PRESENT_VECTOR;
     1.6  		break;
     1.7 +	case 21:
     1.8 +		vector = IA64_KEY_PERMISSION_VECTOR;
     1.9 +		break;
    1.10  	case 22:
    1.11  		vector = IA64_INST_ACCESS_RIGHTS_VECTOR;
    1.12  		break;
     2.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Mon Sep 17 11:30:51 2007 -0600
     2.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Mon Sep 17 13:26:19 2007 -0600
     2.3 @@ -223,9 +223,6 @@ ENTRY(hyper_ssm_i)
     2.4  	// give up for now if: ipsr.be==1, ipsr.pp==1
     2.5  	mov r30=cr.ipsr
     2.6  	mov r29=cr.iip;;
     2.7 -	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
     2.8 -	cmp.ne p7,p0=r21,r0
     2.9 -(p7)	br.sptk.many dispatch_break_fault ;;
    2.10  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
    2.11  	cmp.ne p7,p0=r21,r0
    2.12  (p7)	br.sptk.many dispatch_break_fault ;;
    2.13 @@ -268,7 +265,7 @@ ENTRY(hyper_ssm_i)
    2.14  	// FOR SSM_I ONLY, also turn on psr.i and psr.ic
    2.15  	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC)
    2.16  //	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
    2.17 -	movl r27=~(IA64_PSR_BE|IA64_PSR_BN);;
    2.18 +	movl r27=~IA64_PSR_BN;;
    2.19  	or r30=r30,r28;;
    2.20  	and r30=r30,r27;;
    2.21  	mov r20=1
    2.22 @@ -361,10 +358,7 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.23  	cmp.ltu p6,p0=r26,r27
    2.24  (p6)	br.cond.spnt.few rp;;
    2.25  	mov r17=cr.ipsr;;
    2.26 -	// slow path if: ipsr.be==1, ipsr.pp==1
    2.27 -	extr.u r21=r17,IA64_PSR_BE_BIT,1 ;;
    2.28 -	cmp.ne p6,p0=r21,r0
    2.29 -(p6)	br.cond.spnt.few rp;;
    2.30 +	// slow path if: ipsr.pp==1
    2.31  	extr.u r21=r17,IA64_PSR_PP_BIT,1 ;;
    2.32  	cmp.ne p6,p0=r21,r0
    2.33  (p6)	br.cond.spnt.few rp;;
    2.34 @@ -453,7 +447,7 @@ GLOBAL_ENTRY(fast_tick_reflect)
    2.35  	cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
    2.36  (p7)	dep r17=0,r17,IA64_PSR_CPL0_BIT,2
    2.37  	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
    2.38 -	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
    2.39 +	movl r27=~(IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
    2.40  	or r17=r17,r28;;
    2.41  	and r17=r17,r27
    2.42  	ld4 r16=[r18];;
    2.43 @@ -556,9 +550,6 @@ GLOBAL_ENTRY(fast_break_reflect)
    2.44  #endif
    2.45  	mov r30=cr.ipsr
    2.46  	mov r29=cr.iip;;
    2.47 -	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
    2.48 -	cmp.ne p7,p0=r21,r0
    2.49 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.50  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
    2.51  	cmp.ne p7,p0=r21,r0
    2.52  (p7)	br.spnt.few dispatch_break_fault ;;
    2.53 @@ -633,7 +624,7 @@ ENTRY(fast_reflect)
    2.54  	cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
    2.55  (p7)	dep r30=0,r30,IA64_PSR_CPL0_BIT,2
    2.56  	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
    2.57 -	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
    2.58 +	movl r27=~(IA64_PSR_PP|IA64_PSR_BN);;
    2.59  	or r30=r30,r28;;
    2.60  	and r30=r30,r27
    2.61  	// also set shared_mem ipsr.i and ipsr.ic appropriately
    2.62 @@ -744,9 +735,6 @@ GLOBAL_ENTRY(fast_access_reflect)
    2.63  #endif
    2.64  	mov r30=cr.ipsr
    2.65  	mov r29=cr.iip;;
    2.66 -	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
    2.67 -	cmp.ne p7,p0=r21,r0
    2.68 -(p7)	br.spnt.few dispatch_reflection ;;
    2.69  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
    2.70  	cmp.ne p7,p0=r21,r0
    2.71  (p7)	br.spnt.few dispatch_reflection ;;
    2.72 @@ -794,9 +782,6 @@ GLOBAL_ENTRY(fast_tlb_miss_reflect)
    2.73  	cmp.eq p7,p0=r21,r0
    2.74  (p7)	br.spnt.few page_fault ;;
    2.75  	// slow path if strange ipsr or isr bits set
    2.76 -	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
    2.77 -	cmp.ne p7,p0=r21,r0
    2.78 -(p7)	br.spnt.few page_fault ;;
    2.79  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
    2.80  	cmp.ne p7,p0=r21,r0
    2.81  (p7)	br.spnt.few page_fault ;;
    2.82 @@ -1068,10 +1053,6 @@ ENTRY(hyper_rfi)
    2.83  1:
    2.84  	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.85  	ld8 r21=[r20];;		// r21 = vcr.ipsr
    2.86 -	extr.u r22=r21,IA64_PSR_BE_BIT,1 ;;
    2.87 -	// if turning on psr.be, give up for now and do it the slow way
    2.88 -	cmp.ne p7,p0=r22,r0
    2.89 -(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.90  	// if (!(vpsr.dt && vpsr.rt && vpsr.it)), do it the slow way
    2.91  	movl r20=(IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IT);;
    2.92  	and r22=r20,r21
     3.1 --- a/xen/arch/ia64/xen/ivt.S	Mon Sep 17 11:30:51 2007 -0600
     3.2 +++ b/xen/arch/ia64/xen/ivt.S	Mon Sep 17 13:26:19 2007 -0600
     3.3 @@ -313,7 +313,6 @@ GLOBAL_ENTRY(dispatch_reflection)
     3.4  	adds out1=16,sp
     3.5  	mov out2=cr.isr
     3.6  	mov out3=cr.iim
     3.7 -//	mov out3=cr.itir		// TODO: why commented out?
     3.8  
     3.9  	ssm psr.ic | PSR_DEFAULT_BITS
    3.10  	;;
     4.1 --- a/xen/arch/ia64/xen/mm.c	Mon Sep 17 11:30:51 2007 -0600
     4.2 +++ b/xen/arch/ia64/xen/mm.c	Mon Sep 17 13:26:19 2007 -0600
     4.3 @@ -509,25 +509,22 @@ u64 translate_domain_pte(u64 pteval, u64
     4.4  	u64 arflags;
     4.5  	u64 arflags2;
     4.6  	u64 maflags2;
     4.7 -	u64 ps;
     4.8  
     4.9  	pteval &= ((1UL << 53) - 1);// ignore [63:53] bits
    4.10  
    4.11  	// FIXME address had better be pre-validated on insert
    4.12  	mask = ~itir_mask(_itir.itir);
    4.13  	mpaddr = ((pteval & _PAGE_PPN_MASK) & ~mask) | (address & mask);
    4.14 -	ps = current->arch.vhpt_pg_shift ? current->arch.vhpt_pg_shift :
    4.15 -					   PAGE_SHIFT;
    4.16 -
    4.17 -	if (_itir.ps > ps)
    4.18 -		_itir.ps = ps;
    4.19 +
    4.20 +	if (_itir.ps > PAGE_SHIFT)
    4.21 +		_itir.ps = PAGE_SHIFT;
    4.22  
    4.23  	((ia64_itir_t*)itir)->itir = _itir.itir;/* Copy the whole register. */
    4.24  	((ia64_itir_t*)itir)->ps = _itir.ps;	/* Overwrite ps part! */
    4.25  
    4.26  	pteval2 = lookup_domain_mpa(d, mpaddr, entry);
    4.27 -	if (ps < PAGE_SHIFT)
    4.28 -		pteval2 |= mpaddr & (PAGE_SIZE - 1) & ~((1L << ps) - 1);
    4.29 +	if (_itir.ps < PAGE_SHIFT)
    4.30 +		pteval2 |= mpaddr & (PAGE_SIZE - 1) & ~((1L << _itir.ps) - 1);
    4.31  
    4.32  	/* Check access rights.  */
    4.33  	arflags  = pteval  & _PAGE_AR_MASK;
     5.1 --- a/xen/arch/ia64/xen/vcpu.c	Mon Sep 17 11:30:51 2007 -0600
     5.2 +++ b/xen/arch/ia64/xen/vcpu.c	Mon Sep 17 13:26:19 2007 -0600
     5.3 @@ -2319,8 +2319,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
     5.4  {
     5.5  	ia64_itir_t _itir = {.itir = itir};
     5.6  	unsigned long psr;
     5.7 -	unsigned long ps = (vcpu->domain == dom0) ? _itir.ps :
     5.8 -						    vcpu->arch.vhpt_pg_shift;
     5.9  
    5.10  	check_xen_space_overlap("itc", vaddr, 1UL << _itir.ps);
    5.11  
    5.12 @@ -2329,12 +2327,12 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
    5.13  		panic_domain(NULL, "vcpu_itc_no_srlz: domain trying to use "
    5.14  		             "smaller page size!\n");
    5.15  
    5.16 -	BUG_ON(_itir.ps > vcpu->arch.vhpt_pg_shift);
    5.17 +	BUG_ON(_itir.ps > PAGE_SHIFT);
    5.18  	vcpu_tlb_track_insert_or_dirty(vcpu, vaddr, entry);
    5.19  	psr = ia64_clear_ic();
    5.20  	pte &= ~(_PAGE_RV2 | _PAGE_RV1);	// Mask out the reserved bits.
    5.21  					// FIXME: look for bigger mappings
    5.22 -	ia64_itc(IorD, vaddr, pte, IA64_ITIR_PS_KEY(ps, _itir.key));
    5.23 +	ia64_itc(IorD, vaddr, pte, _itir.itir);
    5.24  	ia64_set_psr(psr);
    5.25  	// ia64_srlz_i(); // no srls req'd, will rfi later
    5.26  	if (vcpu->domain == dom0 && ((vaddr >> 61) == 7)) {
    5.27 @@ -2350,7 +2348,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
    5.28  	// even if domain pagesize is larger than PAGE_SIZE, just put
    5.29  	// PAGE_SIZE mapping in the vhpt for now, else purging is complicated
    5.30  	else {
    5.31 -		_itir.ps = vcpu->arch.vhpt_pg_shift;
    5.32  		vhpt_insert(vaddr, pte, _itir.itir);
    5.33  	}
    5.34  }
     6.1 --- a/xen/arch/ia64/xen/vhpt.c	Mon Sep 17 11:30:51 2007 -0600
     6.2 +++ b/xen/arch/ia64/xen/vhpt.c	Mon Sep 17 13:26:19 2007 -0600
     6.3 @@ -293,15 +293,18 @@ static void
     6.4  {
     6.5  	void *vhpt_base = __va(vhpt_maddr);
     6.6  	u64 pgsz = 1L << current->arch.vhpt_pg_shift;
     6.7 +	u64 purge_addr = vadr & ~(PAGE_SIZE - 1);
     6.8  
     6.9 +	addr_range += vadr - purge_addr;
    6.10 +	addr_range = (addr_range + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
    6.11  	while ((long)addr_range > 0) {
    6.12  		/* Get the VHPT entry.  */
    6.13 -		unsigned int off = ia64_thash(vadr) -
    6.14 +		unsigned int off = ia64_thash(purge_addr) -
    6.15  			__va_ul(vcpu_vhpt_maddr(current));
    6.16  		struct vhpt_lf_entry *v = vhpt_base + off;
    6.17  		v->ti_tag = INVALID_TI_TAG;
    6.18  		addr_range -= pgsz;
    6.19 -		vadr += pgsz;
    6.20 +		purge_addr += pgsz;
    6.21  	}
    6.22  }
    6.23