ia64/xen-unstable

changeset 18583:faf07ca43a28

Add pci configuration code, which is needed by VTD

Signed-off-by; Anthony Xu <anthony.xu@intel.com>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Fri Oct 10 11:47:07 2008 +0900 (2008-10-10)
parents 903a901ab372
children 1a77bb358d7b
files xen/arch/ia64/xen/Makefile xen/arch/ia64/xen/pci.c
line diff
     1.1 --- a/xen/arch/ia64/xen/Makefile	Fri Oct 10 11:17:24 2008 +0900
     1.2 +++ b/xen/arch/ia64/xen/Makefile	Fri Oct 10 11:47:07 2008 +0900
     1.3 @@ -37,6 +37,7 @@ obj-y += xentime.o
     1.4  obj-y += flushd.o
     1.5  obj-y += privop_stat.o
     1.6  obj-y += xenpatch.o
     1.7 +obj-y += pci.o
     1.8  
     1.9  obj-$(crash_debug) += gdbstub.o
    1.10  obj-$(xen_ia64_tlb_track) += tlb_track.o
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/arch/ia64/xen/pci.c	Fri Oct 10 11:47:07 2008 +0900
     2.3 @@ -0,0 +1,134 @@
     2.4 +/*
     2.5 + * pci.c - Low-Level PCI Access in IA-64
     2.6 + *
     2.7 + * Derived from bios32.c of i386 tree.
     2.8 + *
     2.9 + * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
    2.10 + *  David Mosberger-Tang <davidm@hpl.hp.com>
    2.11 + * Bjorn Helgaas <bjorn.helgaas@hp.com>
    2.12 + * Copyright (C) 2004 Silicon Graphics, Inc.
    2.13 + *
    2.14 + * Note: Above list of copyright holders is incomplete...
    2.15 + */
    2.16 +
    2.17 +#include <xen/pci.h>
    2.18 +#include <xen/pci_regs.h>
    2.19 +#include <xen/spinlock.h>
    2.20 +
    2.21 +#include <asm/io.h>
    2.22 +#include <asm/sal.h>
    2.23 +#include <asm/hw_irq.h>
    2.24 +
    2.25 +/*
    2.26 + * Low-level SAL-based PCI configuration access functions. Note that SAL
    2.27 + * calls are already serialized (via sal_lock), so we don't need another
    2.28 + * synchronization mechanism here.
    2.29 + */
    2.30 +
    2.31 +#define PCI_SAL_ADDRESS(seg, bus, devfn, reg)       \
    2.32 +    (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
    2.33 +
    2.34 +/* SAL 3.2 adds support for extended config space. */
    2.35 +
    2.36 +#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)   \
    2.37 +    (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
    2.38 +
    2.39 +static int
    2.40 +pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
    2.41 +        int reg, int len, u32 *value)
    2.42 +{
    2.43 +    u64 addr, data = 0;
    2.44 +    int mode, result;
    2.45 +
    2.46 +    if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
    2.47 +        return -EINVAL;
    2.48 +
    2.49 +    if ((seg | reg) <= 255) {
    2.50 +        addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
    2.51 +        mode = 0;
    2.52 +    } else {
    2.53 +        addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
    2.54 +        mode = 1;
    2.55 +    }
    2.56 +    result = ia64_sal_pci_config_read(addr, mode, len, &data);
    2.57 +    if (result != 0)
    2.58 +        return -EINVAL;
    2.59 +
    2.60 +    *value = (u32) data;
    2.61 +    return 0;
    2.62 +}
    2.63 +
    2.64 +static int
    2.65 +pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
    2.66 +        int reg, int len, u32 value)
    2.67 +{
    2.68 +    u64 addr;
    2.69 +    int mode, result;
    2.70 +
    2.71 +    if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
    2.72 +        return -EINVAL;
    2.73 +
    2.74 +    if ((seg | reg) <= 255) {
    2.75 +        addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
    2.76 +        mode = 0;
    2.77 +    } else {
    2.78 +        addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
    2.79 +        mode = 1;
    2.80 +    }
    2.81 +    result = ia64_sal_pci_config_write(addr, mode, len, value);
    2.82 +    if (result != 0)
    2.83 +        return -EINVAL;
    2.84 +    return 0;
    2.85 +}
    2.86 +
    2.87 +
    2.88 +uint8_t pci_conf_read8(
    2.89 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg)
    2.90 +{
    2.91 +    uint32_t value;
    2.92 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
    2.93 +    pci_sal_read(0, bus, (dev<<3)|func, reg, 1, &value);
    2.94 +    return (uint8_t)value;
    2.95 +}
    2.96 +
    2.97 +uint16_t pci_conf_read16(
    2.98 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg)
    2.99 +{
   2.100 +    uint32_t value;
   2.101 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
   2.102 +    pci_sal_read(0, bus, (dev<<3)|func, reg, 2, &value);
   2.103 +    return (uint16_t)value;
   2.104 +}
   2.105 +
   2.106 +uint32_t pci_conf_read32(
   2.107 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg)
   2.108 +{
   2.109 +    uint32_t value;
   2.110 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
   2.111 +    pci_sal_read(0, bus, (dev<<3)|func, reg, 4, &value);
   2.112 +    return (uint32_t)value;
   2.113 +}
   2.114 +
   2.115 +void pci_conf_write8(
   2.116 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
   2.117 +    uint8_t data)
   2.118 +{
   2.119 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
   2.120 +    pci_sal_write(0, bus, (dev<<3)|func, reg, 1, data);
   2.121 +}
   2.122 +
   2.123 +void pci_conf_write16(
   2.124 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
   2.125 +    uint16_t data)
   2.126 +{
   2.127 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
   2.128 +    pci_sal_write(0, bus, (dev<<3)|func, reg, 2, data);
   2.129 +}
   2.130 +
   2.131 +void pci_conf_write32(
   2.132 +    unsigned int bus, unsigned int dev, unsigned int func, unsigned int reg,
   2.133 +    uint32_t data)
   2.134 +{
   2.135 +    BUG_ON((bus > 255) || (dev > 31) || (func > 7) || (reg > 255));
   2.136 +    pci_sal_write(0, bus, (dev<<3)|func, reg, 4, data);
   2.137 +}