ia64/xen-unstable

changeset 15474:f71dcdd9cddb

[IA64] Clear the key part of cr.itir

Clear the key part of cr.itir before itc.X in alt_dtlb_miss(), alt_itlb_miss()
and frametable_miss(). Preparation for using protection keys.

Signed-off-by: Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jul 05 13:15:44 2007 -0600 (2007-07-05)
parents 34f285b57b87
children a8aeffcc06aa
files xen/arch/ia64/xen/ivt.S xen/include/asm-ia64/xenkregs.h
line diff
     1.1 --- a/xen/arch/ia64/xen/ivt.S	Thu Jul 05 13:04:00 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/ivt.S	Thu Jul 05 13:15:44 2007 -0600
     1.3 @@ -154,14 +154,17 @@ late_alt_itlb_miss:
     1.4  	movl r17=PAGE_KERNEL
     1.5  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
     1.6  	;;
     1.7 +	mov r20=cr.itir
     1.8  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
     1.9  	and r19=r19,r16		// clear ed, reserved bits, and PTE ctrl bits
    1.10  	extr.u r18=r16,XEN_VIRT_UC_BIT,1	// extract UC bit
    1.11  	;;
    1.12  	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
    1.13  	or r19=r17,r19		// insert PTE control bits into r19
    1.14 +	dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN	// clear the key 
    1.15  	;;
    1.16  	dep r19=r18,r19,4,1	// set bit 4 (uncached) if access to UC area.
    1.17 +	mov cr.itir=r20		// set itir with cleared key
    1.18  (p8)	br.cond.spnt page_fault
    1.19  	;;
    1.20  	itc.i r19		// insert the TLB entry
    1.21 @@ -195,6 +198,7 @@ late_alt_dtlb_miss:
    1.22  (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
    1.23  (p8)	br.cond.spnt page_fault
    1.24  	;;
    1.25 +	mov r20=cr.itir
    1.26  #ifdef CONFIG_VIRTUAL_FRAME_TABLE
    1.27  	shr r22=r16,56	 	// Test for the address of virtual frame_table
    1.28  	;;
    1.29 @@ -204,11 +208,13 @@ late_alt_dtlb_miss:
    1.30  	// If it is not a Xen address, handle it via page_fault.
    1.31  	extr.u r22=r16,59,5
    1.32  	;;
    1.33 +	dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN	// clear the key
    1.34  	cmp.ne p8,p0=0x1e,r22
    1.35  (p8)	br.cond.sptk page_fault
    1.36  	;;
    1.37  	dep r21=-1,r21,IA64_PSR_ED_BIT,1
    1.38  	or r19=r19,r17		// insert PTE control bits into r19
    1.39 +	mov cr.itir=r20		// set itir with cleared key
    1.40  	;;
    1.41  	dep r19=r18,r19,4,1	// set bit 4 (uncached) if access to UC area
    1.42  (p6)	mov cr.ipsr=r21
    1.43 @@ -242,7 +248,7 @@ GLOBAL_ENTRY(frametable_miss)
    1.44  	shladd r24=r19,3,r24	// r24=&pte[pte_offset(addr)]
    1.45  	;;
    1.46  (p7)	ld8 r24=[r24]		// r24=pte[pte_offset(addr)]
    1.47 -	mov r25=0x700|(PAGE_SHIFT<<2) // key=7
    1.48 +	mov r25=(PAGE_SHIFT<<IA64_ITIR_PS)
    1.49  (p6)	br.spnt.few frametable_fault
    1.50  	;;
    1.51  	mov cr.itir=r25
     2.1 --- a/xen/include/asm-ia64/xenkregs.h	Thu Jul 05 13:04:00 2007 -0600
     2.2 +++ b/xen/include/asm-ia64/xenkregs.h	Thu Jul 05 13:15:44 2007 -0600
     2.3 @@ -35,4 +35,16 @@
     2.4  #define IA64_PTA_VF     (__IA64_UL(1) << IA64_PTA_VF_BIT)
     2.5  #define IA64_PTA_BASE   (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
     2.6  
     2.7 +/* Some cr.itir declarations. */
     2.8 +#define	IA64_ITIR_PS		2
     2.9 +#define	IA64_ITIR_PS_LEN	6
    2.10 +#define IA64_ITIR_PS_MASK	(((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
    2.11 +							<< IA64_ITIR_PS)
    2.12 +#define	IA64_ITIR_KEY		8
    2.13 +#define	IA64_ITIR_KEY_LEN	24
    2.14 +#define	IA64_ITIR_KEY_MASK	(((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
    2.15 +							<< IA64_ITIR_KEY)
    2.16 +#define IA64_ITIR_PS_KEY(_ps, _key)	(((_ps) << IA64_ITIR_PS) | \
    2.17 +					(((_key) << IA64_ITIR_KEY)))
    2.18 +
    2.19  #endif /* _ASM_IA64_XENKREGS_H */