1.1 --- a/tools/ioemu/hw/pci.c	Thu Nov 30 17:27:00 2006 +0000
     1.2 +++ b/tools/ioemu/hw/pci.c	Thu Nov 30 17:32:16 2006 +0000
     1.3 @@ -221,23 +221,16 @@ uint32_t pci_default_read_config(PCIDevi
     1.4                                   uint32_t address, int len)
     1.5  {
     1.6      uint32_t val;
     1.7 -
     1.8      switch(len) {
     1.9 +    case 1:
    1.10 +        val = d->config[address];
    1.11 +        break;
    1.12 +    case 2:
    1.13 +        val = le16_to_cpu(*(uint16_t *)(d->config + address));
    1.14 +        break;
    1.15      default:
    1.16      case 4:
    1.17 -	if (address <= 0xfc) {
    1.18 -	    val = le32_to_cpu(*(uint32_t *)(d->config + address));
    1.19 -	    break;
    1.20 -	}
    1.21 -	/* fall through */
    1.22 -    case 2:
    1.23 -        if (address <= 0xfe) {
    1.24 -	    val = le16_to_cpu(*(uint16_t *)(d->config + address));
    1.25 -	    break;
    1.26 -	}
    1.27 -	/* fall through */
    1.28 -    case 1:
    1.29 -        val = d->config[address];
    1.30 +        val = le32_to_cpu(*(uint32_t *)(d->config + address));
    1.31          break;
    1.32      }
    1.33      return val;
    1.34 @@ -340,8 +333,7 @@ void pci_default_write_config(PCIDevice 
    1.35  
    1.36              d->config[addr] = val;
    1.37          }
    1.38 -        if (++addr > 0xff)
    1.39 -        	break;
    1.40 +        addr++;
    1.41          val >>= 8;
    1.42      }
    1.43  

     2.1 --- a/tools/ioemu/vl.h	Thu Nov 30 17:27:00 2006 +0000
     2.2 +++ b/tools/ioemu/vl.h	Thu Nov 30 17:32:16 2006 +0000
     2.3 @@ -650,8 +650,11 @@ typedef struct PCIIORegion {
     2.4  #define PCI_MAX_LAT		0x3f	/* 8 bits */
     2.5  
     2.6  struct PCIDevice {
     2.7 -    /* PCI config space */
     2.8 -    uint8_t config[256];
     2.9 +    /*
    2.10 +     * PCI config space. The 4 extra bytes are a safety buffer for guest
    2.11 +     * word/dword writes that can extend past byte 0xff.
    2.12 +     */
    2.13 +    uint8_t config[256+4];
    2.14  
    2.15      /* the following fields are read only */
    2.16      PCIBus *bus;