ia64/xen-unstable

changeset 18857:f571834d3f5d

AMD IOMMU: Propagate HyperTransport settings from IVHD table to control register

Attached patch propagate HyperTransport settings suggested by IVHD
table to iommu control register(MMIO offset 0018h).

Signed-off-by: Wei Wang <wei.wang2@amd.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Dec 03 15:56:05 2008 +0000 (2008-12-03)
parents 5c121966ad9a
children bb7683510600
files xen/drivers/passthrough/amd/iommu_init.c
line diff
     1.1 --- a/xen/drivers/passthrough/amd/iommu_init.c	Wed Dec 03 15:55:32 2008 +0000
     1.2 +++ b/xen/drivers/passthrough/amd/iommu_init.c	Wed Dec 03 15:56:05 2008 +0000
     1.3 @@ -152,13 +152,33 @@ static void __init set_iommu_translation
     1.4  {
     1.5      u32 entry;
     1.6  
     1.7 -    entry = readl(iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET);
     1.8 -    set_field_in_reg_u32(iommu->ht_tunnel_support ? IOMMU_CONTROL_ENABLED :
     1.9 -                         IOMMU_CONTROL_ENABLED, entry,
    1.10 +    entry = readl(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
    1.11 +
    1.12 +    if ( enable )
    1.13 +    {
    1.14 +        set_field_in_reg_u32(iommu->ht_tunnel_support ? IOMMU_CONTROL_ENABLED :
    1.15 +                         IOMMU_CONTROL_DISABLED, entry,
    1.16                           IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_MASK,
    1.17                           IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT, &entry);
    1.18 +        set_field_in_reg_u32(iommu->isochronous ? IOMMU_CONTROL_ENABLED :
    1.19 +                         IOMMU_CONTROL_DISABLED, entry,
    1.20 +                         IOMMU_CONTROL_ISOCHRONOUS_MASK,
    1.21 +                         IOMMU_CONTROL_ISOCHRONOUS_SHIFT, &entry);
    1.22 +        set_field_in_reg_u32(iommu->coherent ? IOMMU_CONTROL_ENABLED :
    1.23 +                         IOMMU_CONTROL_DISABLED, entry,
    1.24 +                         IOMMU_CONTROL_COHERENT_MASK,
    1.25 +                         IOMMU_CONTROL_COHERENT_SHIFT, &entry);
    1.26 +        set_field_in_reg_u32(iommu->res_pass_pw ? IOMMU_CONTROL_ENABLED :
    1.27 +                         IOMMU_CONTROL_DISABLED, entry,
    1.28 +                         IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_MASK,
    1.29 +                         IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT, &entry);
    1.30 +        /* do not set PassPW bit */
    1.31 +        set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, entry,
    1.32 +                         IOMMU_CONTROL_PASS_POSTED_WRITE_MASK,
    1.33 +                         IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT, &entry);
    1.34 +    }
    1.35      set_field_in_reg_u32(enable ? IOMMU_CONTROL_ENABLED :
    1.36 -                         IOMMU_CONTROL_ENABLED, entry,
    1.37 +                         IOMMU_CONTROL_DISABLED, entry,
    1.38                           IOMMU_CONTROL_TRANSLATION_ENABLE_MASK,
    1.39                           IOMMU_CONTROL_TRANSLATION_ENABLE_SHIFT, &entry);
    1.40      writel(entry, iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET);
    1.41 @@ -171,7 +191,7 @@ static void __init set_iommu_command_buf
    1.42  
    1.43      entry = readl(iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET);
    1.44      set_field_in_reg_u32(enable ? IOMMU_CONTROL_ENABLED :
    1.45 -                         IOMMU_CONTROL_ENABLED, entry,
    1.46 +                         IOMMU_CONTROL_DISABLED, entry,
    1.47                           IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_MASK,
    1.48                           IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT, &entry);
    1.49      writel(entry, iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET);