ia64/xen-unstable

changeset 9260:f4cef1aa2521

Fix ASSERT failure caused by NX support code on x86_64
When turning on debug for x86_64, ASSERT(gpfn =3D=3D (gpfn & =
PGT_mfn_mask))
in __shadow_status will fail, this patch makes the NX support code
comply with this ASSERT.
NB: NX on PAE xen is not supported yet.

Signed-off-by: Xin Li <xin.b.li@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Tue Mar 14 16:09:34 2006 +0100 (2006-03-14)
parents de5d2b9a9cfb
children e3d7c2183866
files xen/arch/x86/shadow.c xen/include/asm-x86/mm.h
line diff
     1.1 --- a/xen/arch/x86/shadow.c	Tue Mar 14 16:00:16 2006 +0100
     1.2 +++ b/xen/arch/x86/shadow.c	Tue Mar 14 16:09:34 2006 +0100
     1.3 @@ -3413,7 +3413,9 @@ static inline int l2e_rw_fault(
     1.4      l1_pgentry_t sl1e;
     1.5      l1_pgentry_t old_sl1e;
     1.6      l2_pgentry_t sl2e;
     1.7 +#ifdef __x86_64__
     1.8      u64 nx = 0;
     1.9 +#endif
    1.10      int put_ref_check = 0;
    1.11      /* Check if gpfn is 2M aligned */
    1.12  
    1.13 @@ -3428,7 +3430,9 @@ static inline int l2e_rw_fault(
    1.14      l2e_remove_flags(tmp_l2e, _PAGE_PSE);
    1.15      if (l2e_get_flags(gl2e) & _PAGE_NX) {
    1.16          l2e_remove_flags(tmp_l2e, _PAGE_NX);
    1.17 -        nx = 1ULL << 63;
    1.18 +#ifdef __x86_64__
    1.19 +        nx = PGT_high_mfn_nx;
    1.20 +#endif
    1.21      }
    1.22  
    1.23  
    1.24 @@ -3436,7 +3440,11 @@ static inline int l2e_rw_fault(
    1.25      if ( !__shadow_get_l2e(v, va, &sl2e) )
    1.26          sl2e = l2e_empty();
    1.27  
    1.28 +#ifdef __x86_64__
    1.29      l1_mfn = __shadow_status(d, start_gpfn | nx, PGT_fl1_shadow);
    1.30 +#else
    1.31 +    l1_mfn = __shadow_status(d, start_gpfn, PGT_fl1_shadow);
    1.32 +#endif
    1.33  
    1.34      /* Check the corresponding l2e */
    1.35      if (l1_mfn) {
    1.36 @@ -3454,7 +3462,11 @@ static inline int l2e_rw_fault(
    1.37      } else {
    1.38          /* Allocate a new page as shadow page table if need */
    1.39          gmfn = gmfn_to_mfn(d, start_gpfn);
    1.40 +#ifdef __x86_64__
    1.41          l1_mfn = alloc_shadow_page(d, start_gpfn | nx, gmfn, PGT_fl1_shadow);
    1.42 +#else
    1.43 +        l1_mfn = alloc_shadow_page(d, start_gpfn, gmfn, PGT_fl1_shadow);
    1.44 +#endif
    1.45          if (unlikely(!l1_mfn)) {
    1.46              BUG();
    1.47          }
     2.1 --- a/xen/include/asm-x86/mm.h	Tue Mar 14 16:00:16 2006 +0100
     2.2 +++ b/xen/include/asm-x86/mm.h	Tue Mar 14 16:09:34 2006 +0100
     2.3 @@ -98,8 +98,17 @@ struct page_info
     2.4   /* 16-bit count of uses of this frame as its current type. */
     2.5  #define PGT_count_mask      ((1U<<16)-1)
     2.6  
     2.7 +#ifdef __x86_64__
     2.8 +#define PGT_high_mfn_shift  52
     2.9 +#define PGT_high_mfn_mask   (0x7ffUL << PGT_high_mfn_shift)
    2.10 +#define PGT_mfn_mask        (((1U<<23)-1) | PGT_high_mfn_mask)
    2.11 +#define PGT_high_mfn_nx     (0x800UL << PGT_high_mfn_shift)
    2.12 +#else
    2.13   /* 23-bit mfn mask for shadow types: good for up to 32GB RAM. */
    2.14  #define PGT_mfn_mask        ((1U<<23)-1)
    2.15 + /* NX for PAE xen is not supported yet */
    2.16 +#define PGT_high_mfn_nx     (1ULL << 63)
    2.17 +#endif
    2.18  
    2.19  #define PGT_score_shift     23
    2.20  #define PGT_score_mask      (((1U<<4)-1)<<PGT_score_shift)