ia64/xen-unstable

changeset 15160:f3f59dafaa18

[IA64] clean-up in ivt.S: remove useless code.

The tests just before the #if VHPT_ENABLED makes the block of code useless.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Mon Jun 04 14:14:35 2007 -0600 (2007-06-04)
parents ab677b67b4a5
children 3e170567505a
files xen/arch/ia64/xen/ivt.S
line diff
     1.1 --- a/xen/arch/ia64/xen/ivt.S	Mon Jun 04 14:12:19 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/ivt.S	Mon Jun 04 14:14:35 2007 -0600
     1.3 @@ -119,9 +119,8 @@ ENTRY(itlb_miss)
     1.4  	;;
     1.5  	/* If address belongs to VMM, go to alt tlb handler */
     1.6  	cmp.eq p6,p0=0x1e,r17
     1.7 -(p6)	br.cond.spnt	late_alt_itlb_miss
     1.8  	;;
     1.9 -	cmp.eq p6,p0=0x1d,r17
    1.10 +	cmp.eq.or p6,p0=0x1d,r17
    1.11  (p6)	br.cond.spnt	late_alt_itlb_miss
    1.12  	;;
    1.13  	mov pr = r31, 0x1ffff
    1.14 @@ -140,68 +139,11 @@ ENTRY(dtlb_miss)
    1.15  	;;
    1.16  	extr.u r17=r16,59,5
    1.17  	;;
    1.18 -	cmp.eq p6,p0=0x1e,r17		// if the address belongs to VMM, go
    1.19 -					//   to the alternate tlb handler
    1.20 -(p6)	br.cond.spnt	late_alt_dtlb_miss
    1.21 -	;;
    1.22 -	cmp.eq p6,p0=0x1d,r17
    1.23 -(p6)	br.cond.spnt	late_alt_dtlb_miss
    1.24 -	;;
    1.25 -#if VHPT_ENABLED
    1.26 -	mov r30=cr.ipsr			// XXX TODO optimization
    1.27 -	mov r28=cr.iip			
    1.28 -	mov r17=cr.isr
    1.29 +	/* If address belongs to VMM, go to alt tlb handler */
    1.30 +	cmp.eq p6,p0=0x1e,r17
    1.31  	;;
    1.32 -
    1.33 -	extr.u r18 = r30, IA64_PSR_CPL0_BIT, 2	// extract psr.cpl
    1.34 -	;; 
    1.35 -	cmp.ne p6, p0 = r0, r18			// cpl == 0?
    1.36 -(p6)	br.cond.sptk 2f
    1.37 -
    1.38 -	tbit.nz p7,p0=r17,IA64_ISR_SP_BIT	// is speculation bit on?
    1.39 -	;; 
    1.40 -(p7)	br.cond.spnt 2f
    1.41 -
    1.42 -	// Is the faulted iip in the vmm area?
    1.43 -	//    -- check [59:58] bit
    1.44 -	//    -- if 00, 11: guest
    1.45 -	//    -- if 01, 10: vmm
    1.46 -	extr.u r19 = r28, 58, 2
    1.47 -	;; 
    1.48 -	cmp.eq p10, p0 = 0x0, r19
    1.49 -(p10)	br.cond.sptk 2f
    1.50 -	cmp.eq p11, p0 = 0x3, r19
    1.51 -(p11)	br.cond.sptk 2f
    1.52 -
    1.53 -	// Is the faulted address is in the identity mapping area?
    1.54 -	// must be either 0xf000... or 0xe8000...
    1.55 -	extr.u r20 = r16, 59, 5
    1.56 -	;; 
    1.57 -	cmp.eq p12, p0 = 0x1e, r20 	// (0xf0 >> 3) = 0x1e
    1.58 -(p12)	br.cond.spnt 1f
    1.59 -	cmp.eq p0, p13 = 0x1d, r20 	// (0xe8 >> 3) = 0x1d
    1.60 -(p13)	br.cond.sptk 2f
    1.61 -
    1.62 -1:
    1.63 -	movl r24=PAGE_KERNEL 		// xen identity mapping area.
    1.64 -	movl r25=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.65 -	;;
    1.66 -	shr.u r26=r16,55	// move address bit 59 to bit 4
    1.67 -	and r25=r25,r16		// clear ed, reserved bits, and PTE control bits
    1.68 -	;;
    1.69 -	and r26=0x10,r26	// bit 4=address-bit(59)
    1.70 -	;; 
    1.71 -	or r25=r25,r24		// insert PTE control bits into r25
    1.72 -	;;
    1.73 -	or r25=r25,r26		// set bit 4 (uncached) if the access was to
    1.74 -				//   region 6
    1.75 -	;;
    1.76 -	itc.d r25		// insert the TLB entry
    1.77 -	mov pr=r31,-1
    1.78 -	rfi
    1.79 -
    1.80 -2:
    1.81 -#endif	
    1.82 +	cmp.eq.or p6,p0=0x1d,r17
    1.83 +(p6)	br.cond.spnt	late_alt_dtlb_miss
    1.84  	br.cond.sptk fast_tlb_miss_reflect
    1.85  	;;
    1.86  END(dtlb_miss)