ia64/xen-unstable

changeset 15725:f317c27973f5

[IA64] Shrink vtlb size

Instrumenting thash_purge_all() shows a very low usage of vtlb
entries (21 at most).

This patch shrinks the default vtlb size from 512KB to 16KB
to optimize memory. This also speeds up ptc_e emulation.
To improve the hash function, frequency of collision never changed
and there is no performance degradation.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Thu Aug 16 09:37:54 2007 -0600 (2007-08-16)
parents cd51fa91956b
children b5dbf184df6c
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vtlb.c xen/include/asm-ia64/vmmu.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Sun Aug 12 14:50:02 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Thu Aug 16 09:37:54 2007 -0600
     1.3 @@ -32,9 +32,9 @@ static void __init parse_vtlb_size(char 
     1.4  
     1.5      if (sz > 0) {
     1.6          default_vtlb_sz = fls(sz - 1);
     1.7 -        /* minimum 256KB (since calculated tag might be broken) */
     1.8 -        if (default_vtlb_sz < 18)
     1.9 -            default_vtlb_sz = 18;
    1.10 +        /* minimum 16KB (for tag uniqueness) */
    1.11 +        if (default_vtlb_sz < 14)
    1.12 +            default_vtlb_sz = 14;
    1.13      }
    1.14  }
    1.15  
    1.16 @@ -240,40 +240,8 @@ void machine_tlb_insert(struct vcpu *v, 
    1.17   */
    1.18  void machine_tlb_purge(u64 va, u64 ps)
    1.19  {
    1.20 -//    u64       psr;
    1.21 -//    psr = ia64_clear_ic();
    1.22      ia64_ptcl(va, ps << 2);
    1.23 -//    ia64_set_psr(psr);
    1.24 -//    ia64_srlz_i();
    1.25 -//    return;
    1.26 -}
    1.27 -/*
    1.28 -u64 machine_thash(u64 va)
    1.29 -{
    1.30 -    return ia64_thash(va);
    1.31 -}
    1.32 -
    1.33 -u64 machine_ttag(u64 va)
    1.34 -{
    1.35 -    return ia64_ttag(va);
    1.36  }
    1.37 -*/
    1.38 -thash_data_t * vsa_thash(PTA vpta, u64 va, u64 vrr, u64 *tag)
    1.39 -{
    1.40 -    u64 index,pfn,rid,pfn_bits;
    1.41 -    pfn_bits = vpta.size-5-8;
    1.42 -    pfn = REGION_OFFSET(va)>>_REGION_PAGE_SIZE(vrr);
    1.43 -    rid = _REGION_ID(vrr);
    1.44 -    index = ((rid&0xff)<<pfn_bits)|(pfn&((1UL<<pfn_bits)-1));
    1.45 -    *tag = ((rid>>8)&0xffff) | ((pfn >>pfn_bits)<<16);
    1.46 -    return (thash_data_t *)((vpta.base<<PTA_BASE_SHIFT)+(index<<5));
    1.47 -//    return ia64_call_vsa(PAL_VPS_THASH,va,vrr,vpta,0,0,0,0);
    1.48 -}
    1.49 -
    1.50 -//u64 vsa_ttag(u64 va, u64 vrr)
    1.51 -//{
    1.52 -//    return ia64_call_vsa(PAL_VPS_TTAG,va,vrr,0,0,0,0,0);
    1.53 -//}
    1.54  
    1.55  int vhpt_enabled(VCPU *vcpu, uint64_t vadr, vhpt_ref_t ref)
    1.56  {
     2.1 --- a/xen/arch/ia64/vmx/vtlb.c	Sun Aug 12 14:50:02 2007 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Thu Aug 16 09:37:54 2007 -0600
     2.3 @@ -286,6 +286,17 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
     2.4      return ret;
     2.5  }
     2.6  
     2.7 +static thash_data_t * vtlb_thash(PTA vpta, u64 va, u64 vrr, u64 *tag)
     2.8 +{
     2.9 +    u64 index, pfn, rid;
    2.10 +
    2.11 +    pfn = REGION_OFFSET(va) >> _REGION_PAGE_SIZE(vrr);
    2.12 +    rid = _REGION_ID(vrr);
    2.13 +    index = (pfn ^ rid) & ((1UL << (vpta.size - 5)) - 1);
    2.14 +    *tag = pfn ^ (rid << 39);
    2.15 +    return (thash_data_t *)((vpta.base << PTA_BASE_SHIFT) + (index << 5));
    2.16 +}
    2.17 +
    2.18  /*
    2.19   *  purge software guest tlb
    2.20   */
    2.21 @@ -308,7 +319,7 @@ static void vtlb_purge(VCPU *v, u64 va, 
    2.22          size = PSIZE(rr_ps);
    2.23          vrr.ps = rr_ps;
    2.24          while (num) {
    2.25 -            cur = vsa_thash(hcb->pta, curadr, vrr.rrval, &tag);
    2.26 +            cur = vtlb_thash(hcb->pta, curadr, vrr.rrval, &tag);
    2.27              while (cur) {
    2.28                  if (cur->etag == tag && cur->ps == rr_ps)
    2.29                      cur->etag = 1UL << 63;
    2.30 @@ -401,7 +412,7 @@ void vtlb_insert(VCPU *v, u64 pte, u64 i
    2.31      vcpu_get_rr(v, va, &vrr.rrval);
    2.32      vrr.ps = itir_ps(itir);
    2.33      VMX(v, psbits[va >> 61]) |= (1UL << vrr.ps);
    2.34 -    hash_table = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
    2.35 +    hash_table = vtlb_thash(hcb->pta, va, vrr.rrval, &tag);
    2.36      cch = hash_table;
    2.37      while (cch) {
    2.38          if (INVALID_TLB(cch)) {
    2.39 @@ -639,7 +650,7 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
    2.40          ps = __ffs(psbits);
    2.41          psbits &= ~(1UL << ps);
    2.42          vrr.ps = ps;
    2.43 -        cch = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
    2.44 +        cch = vtlb_thash(hcb->pta, va, vrr.rrval, &tag);
    2.45          do {
    2.46              if (cch->etag == tag && cch->ps == ps)
    2.47                  return cch;
     3.1 --- a/xen/include/asm-ia64/vmmu.h	Sun Aug 12 14:50:02 2007 -0600
     3.2 +++ b/xen/include/asm-ia64/vmmu.h	Thu Aug 16 09:37:54 2007 -0600
     3.3 @@ -24,7 +24,7 @@
     3.4  #define XEN_TLBthash_H
     3.5  
     3.6  #define     MAX_CCN_DEPTH       (15)       // collision chain depth
     3.7 -#define     DEFAULT_VTLB_SZ     (19) // 512K hash + 512K c-chain for VTLB
     3.8 +#define     DEFAULT_VTLB_SZ     (14) // 16K hash + 16K c-chain for VTLB
     3.9  #define     DEFAULT_VHPT_SZ     (23) // 8M hash + 8M c-chain for VHPT
    3.10  #define     VTLB(v,_x)          (v->arch.vtlb._x)
    3.11  #define     VHPT(v,_x)          (v->arch.vhpt._x)