ia64/xen-unstable
changeset 4499:f301b12bedde
bitkeeper revision 1.1283 (4254ed0bK7tEfc4Z935RO2wbK5HcPw)
Properly ensure that every write to GS is followed by a serialising
instruction before the next SWAPGS (AMD erratum #88). We only resort
to adding an otherwise unnecessary mfence in two cases.
Signed-off-by: Keir Fraser <keir@xensource.com>
Properly ensure that every write to GS is followed by a serialising
instruction before the next SWAPGS (AMD erratum #88). We only resort
to adding an otherwise unnecessary mfence in two cases.
Signed-off-by: Keir Fraser <keir@xensource.com>
author | kaf24@firebug.cl.cam.ac.uk |
---|---|
date | Thu Apr 07 08:19:23 2005 +0000 (2005-04-07) |
parents | 3f2415a328b7 |
children | 608f95d3df77 |
files | xen/arch/x86/domain.c |
line diff
1.1 --- a/xen/arch/x86/domain.c Thu Apr 07 08:01:29 2005 +0000 1.2 +++ b/xen/arch/x86/domain.c Thu Apr 07 08:19:23 2005 +0000 1.3 @@ -585,22 +585,21 @@ static void load_segments(struct exec_do 1.4 n->arch.user_ctxt.fs_base, 1.5 n->arch.user_ctxt.fs_base>>32); 1.6 1.7 + /* Most kernels have non-zero GS base, so don't bother testing. */ 1.8 + /* (This is also a serialising instruction, avoiding AMD erratum #88.) */ 1.9 + wrmsr(MSR_SHADOW_GS_BASE, 1.10 + n->arch.user_ctxt.gs_base_kernel, 1.11 + n->arch.user_ctxt.gs_base_kernel>>32); 1.12 + 1.13 /* This can only be non-zero if selector is NULL. */ 1.14 if ( n->arch.user_ctxt.gs_base_user ) 1.15 wrmsr(MSR_GS_BASE, 1.16 n->arch.user_ctxt.gs_base_user, 1.17 n->arch.user_ctxt.gs_base_user>>32); 1.18 1.19 - /* This can only be non-zero if selector is NULL. */ 1.20 - if ( p->arch.user_ctxt.gs_base_kernel | 1.21 - n->arch.user_ctxt.gs_base_kernel ) 1.22 - wrmsr(MSR_SHADOW_GS_BASE, 1.23 - n->arch.user_ctxt.gs_base_kernel, 1.24 - n->arch.user_ctxt.gs_base_kernel>>32); 1.25 - 1.26 /* If in kernel mode then switch the GS bases around. */ 1.27 if ( n->arch.flags & TF_kernel_mode ) 1.28 - __asm__ __volatile__ ( safe_swapgs ); 1.29 + __asm__ __volatile__ ( "swapgs" ); 1.30 1.31 if ( unlikely(!all_segs_okay) ) 1.32 {