ia64/xen-unstable

changeset 4438:f042ec659698

bitkeeper revision 1.1236.1.194 (424db315wN-6WLb5nifJ_SZs9-2r6A)

Merge bk://xen.bkbits.net/xeno-unstable.bk
into bkbits.net:/repos/x/xen-ia64/xeno-unstable-ia64.bk
author xen-ia64.adm@bkbits.net
date Fri Apr 01 20:46:13 2005 +0000 (2005-04-01)
parents 185169ecc5e0 5ac1e6647195
children 528e86541344
files xen/arch/ia64/Rules.mk xen/arch/ia64/patch/linux-2.6.7/ivt.S xen/arch/ia64/regionreg.c xen/arch/ia64/vcpu.c xen/arch/ia64/vhpt.c xen/arch/ia64/xenasm.S xen/arch/ia64/xensetup.c xen/include/asm-ia64/config.h xen/include/asm-ia64/vhpt.h
line diff
     1.1 --- a/xen/arch/ia64/Rules.mk	Fri Apr 01 17:44:42 2005 +0000
     1.2 +++ b/xen/arch/ia64/Rules.mk	Fri Apr 01 20:46:13 2005 +0000
     1.3 @@ -5,8 +5,8 @@ ifeq ($(COMPILE_ARCH),$(TARGET_ARCH))
     1.4  OBJCOPY = objcopy
     1.5  endif
     1.6  ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
     1.7 -CC = /usr/local/sp_env/v2.2/i686/bin/ia64-unknown-linux-gcc
     1.8 -LD = /usr/local/sp_env/v2.2/i686/bin/ia64-unknown-linux-ld
     1.9 +CC = /usr/local/sp_env/v2.2.3/i686/bin/ia64-unknown-linux-gcc
    1.10 +LD = /usr/local/sp_env/v2.2.3/i686/bin/ia64-unknown-linux-ld
    1.11  OBJCOPY = /usr/local/sp_env/v2.2/i686/bin/ia64-unknown-linux-objcopy
    1.12  endif
    1.13  HOSTCC := gcc
     2.1 --- a/xen/arch/ia64/patch/linux-2.6.7/ivt.S	Fri Apr 01 17:44:42 2005 +0000
     2.2 +++ b/xen/arch/ia64/patch/linux-2.6.7/ivt.S	Fri Apr 01 20:46:13 2005 +0000
     2.3 @@ -1,5 +1,5 @@
     2.4 ---- /home/djm/src/xen/xeno-ia64.bk/xen/linux-2.6.7/arch/ia64/kernel/ivt.S	2004-06-15 23:18:59.000000000 -0600
     2.5 -+++ /home/djm/src/xen/xeno-ia64.bk/xen/arch/ia64/ivt.S	2004-12-17 13:47:03.000000000 -0700
     2.6 +--- ../../linux-2.6.7/arch/ia64/kernel/ivt.S	2004-06-15 23:18:59.000000000 -0600
     2.7 ++++ arch/ia64/ivt.S	2005-03-28 20:16:02.000000000 -0700
     2.8  @@ -1,3 +1,21 @@
     2.9  +
    2.10  +#ifdef XEN
    2.11 @@ -36,49 +36,63 @@
    2.12   	.section .text.ivt,"ax"
    2.13   
    2.14   	.align 32768	// align on 32KB boundary
    2.15 -@@ -213,6 +238,9 @@
    2.16 +@@ -213,6 +238,13 @@
    2.17   // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
    2.18   ENTRY(itlb_miss)
    2.19   	DBG_FAULT(1)
    2.20  +#ifdef XEN
    2.21  +	VHPT_CCHAIN_LOOKUP(itlb_miss,i)
    2.22 ++#ifdef VHPT_GLOBAL
    2.23 ++	br.cond.sptk page_fault
    2.24 ++	;;
    2.25 ++#endif
    2.26  +#endif
    2.27   	/*
    2.28   	 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
    2.29   	 * page table.  If a nested TLB miss occurs, we switch into physical
    2.30 -@@ -257,6 +285,9 @@
    2.31 +@@ -257,6 +289,13 @@
    2.32   // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
    2.33   ENTRY(dtlb_miss)
    2.34   	DBG_FAULT(2)
    2.35  +#ifdef XEN
    2.36  +	VHPT_CCHAIN_LOOKUP(dtlb_miss,d)
    2.37 ++#ifdef VHPT_GLOBAL
    2.38 ++	br.cond.sptk page_fault
    2.39 ++	;;
    2.40 ++#endif
    2.41  +#endif
    2.42   	/*
    2.43   	 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
    2.44   	 * page table.  If a nested TLB miss occurs, we switch into physical
    2.45 -@@ -301,6 +332,10 @@
    2.46 +@@ -301,6 +340,13 @@
    2.47   // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
    2.48   ENTRY(alt_itlb_miss)
    2.49   	DBG_FAULT(3)
    2.50  +#ifdef XEN
    2.51 -+// I think this is superfluous, once all regions have VHPT enabled
    2.52 ++//#ifdef VHPT_GLOBAL
    2.53  +//	VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i)
    2.54 ++//	br.cond.sptk page_fault
    2.55 ++//	;;
    2.56 ++//#endif
    2.57  +#endif
    2.58   	mov r16=cr.ifa		// get address that caused the TLB miss
    2.59   	movl r17=PAGE_KERNEL
    2.60   	mov r21=cr.ipsr
    2.61 -@@ -339,6 +374,10 @@
    2.62 +@@ -339,6 +385,13 @@
    2.63   // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
    2.64   ENTRY(alt_dtlb_miss)
    2.65   	DBG_FAULT(4)
    2.66  +#ifdef XEN
    2.67 -+// I think this is superfluous, once all regions have VHPT enabled
    2.68 ++//#ifdef VHPT_GLOBAL
    2.69  +//	VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d)
    2.70 ++//	br.cond.sptk page_fault
    2.71 ++//	;;
    2.72 ++//#endif
    2.73  +#endif
    2.74   	mov r16=cr.ifa		// get address that caused the TLB miss
    2.75   	movl r17=PAGE_KERNEL
    2.76   	mov r20=cr.isr
    2.77 -@@ -368,6 +407,17 @@
    2.78 +@@ -368,6 +421,17 @@
    2.79   	cmp.ne p8,p0=r0,r23
    2.80   (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
    2.81   (p8)	br.cond.spnt page_fault
    2.82 @@ -96,7 +110,7 @@
    2.83   
    2.84   	dep r21=-1,r21,IA64_PSR_ED_BIT,1
    2.85   	or r19=r19,r17		// insert PTE control bits into r19
    2.86 -@@ -448,6 +498,9 @@
    2.87 +@@ -448,6 +512,9 @@
    2.88   /////////////////////////////////////////////////////////////////////////////////////////
    2.89   // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
    2.90   ENTRY(ikey_miss)
    2.91 @@ -106,7 +120,7 @@
    2.92   	DBG_FAULT(6)
    2.93   	FAULT(6)
    2.94   END(ikey_miss)
    2.95 -@@ -460,9 +513,16 @@
    2.96 +@@ -460,9 +527,16 @@
    2.97   	srlz.i
    2.98   	;;
    2.99   	SAVE_MIN_WITH_COVER
   2.100 @@ -123,7 +137,7 @@
   2.101   	adds r3=8,r2				// set up second base pointer
   2.102   	;;
   2.103   	ssm psr.ic | PSR_DEFAULT_BITS
   2.104 -@@ -483,6 +543,9 @@
   2.105 +@@ -483,6 +557,9 @@
   2.106   /////////////////////////////////////////////////////////////////////////////////////////
   2.107   // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
   2.108   ENTRY(dkey_miss)
   2.109 @@ -133,7 +147,7 @@
   2.110   	DBG_FAULT(7)
   2.111   	FAULT(7)
   2.112   END(dkey_miss)
   2.113 -@@ -491,6 +554,9 @@
   2.114 +@@ -491,6 +568,9 @@
   2.115   /////////////////////////////////////////////////////////////////////////////////////////
   2.116   // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
   2.117   ENTRY(dirty_bit)
   2.118 @@ -143,7 +157,7 @@
   2.119   	DBG_FAULT(8)
   2.120   	/*
   2.121   	 * What we do here is to simply turn on the dirty bit in the PTE.  We need to
   2.122 -@@ -553,6 +619,9 @@
   2.123 +@@ -553,6 +633,9 @@
   2.124   /////////////////////////////////////////////////////////////////////////////////////////
   2.125   // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
   2.126   ENTRY(iaccess_bit)
   2.127 @@ -153,7 +167,7 @@
   2.128   	DBG_FAULT(9)
   2.129   	// Like Entry 8, except for instruction access
   2.130   	mov r16=cr.ifa				// get the address that caused the fault
   2.131 -@@ -618,6 +687,9 @@
   2.132 +@@ -618,6 +701,9 @@
   2.133   /////////////////////////////////////////////////////////////////////////////////////////
   2.134   // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
   2.135   ENTRY(daccess_bit)
   2.136 @@ -163,7 +177,7 @@
   2.137   	DBG_FAULT(10)
   2.138   	// Like Entry 8, except for data access
   2.139   	mov r16=cr.ifa				// get the address that caused the fault
   2.140 -@@ -686,6 +758,16 @@
   2.141 +@@ -686,6 +772,16 @@
   2.142   	 * to prevent leaking bits from kernel to user level.
   2.143   	 */
   2.144   	DBG_FAULT(11)
   2.145 @@ -180,7 +194,7 @@
   2.146   	mov r16=IA64_KR(CURRENT)		// r16 = current task; 12 cycle read lat.
   2.147   	mov r17=cr.iim
   2.148   	mov r18=__IA64_BREAK_SYSCALL
   2.149 -@@ -696,7 +778,9 @@
   2.150 +@@ -696,7 +792,9 @@
   2.151   	mov r27=ar.rsc
   2.152   	mov r26=ar.pfs
   2.153   	mov r28=cr.iip
   2.154 @@ -190,7 +204,7 @@
   2.155   	mov r20=r1
   2.156   	;;
   2.157   	adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
   2.158 -@@ -792,6 +876,36 @@
   2.159 +@@ -792,6 +890,36 @@
   2.160   	DBG_FAULT(13)
   2.161   	FAULT(13)
   2.162   
   2.163 @@ -227,7 +241,7 @@
   2.164   	.org ia64_ivt+0x3800
   2.165   /////////////////////////////////////////////////////////////////////////////////////////
   2.166   // 0x3800 Entry 14 (size 64 bundles) Reserved
   2.167 -@@ -842,9 +956,11 @@
   2.168 +@@ -842,9 +970,11 @@
   2.169   	 *	- ar.fpsr: set to kernel settings
   2.170   	 */
   2.171   GLOBAL_ENTRY(ia64_syscall_setup)
   2.172 @@ -239,7 +253,7 @@
   2.173   	st8 [r1]=r19				// save b6
   2.174   	add r16=PT(CR_IPSR),r1			// initialize first base pointer
   2.175   	add r17=PT(R11),r1			// initialize second base pointer
   2.176 -@@ -974,6 +1090,37 @@
   2.177 +@@ -974,6 +1104,37 @@
   2.178   	DBG_FAULT(16)
   2.179   	FAULT(16)
   2.180   
   2.181 @@ -277,7 +291,7 @@
   2.182   	.org ia64_ivt+0x4400
   2.183   /////////////////////////////////////////////////////////////////////////////////////////
   2.184   // 0x4400 Entry 17 (size 64 bundles) Reserved
   2.185 -@@ -1090,6 +1237,9 @@
   2.186 +@@ -1090,6 +1251,9 @@
   2.187   /////////////////////////////////////////////////////////////////////////////////////////
   2.188   // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
   2.189   ENTRY(page_not_present)
   2.190 @@ -287,7 +301,7 @@
   2.191   	DBG_FAULT(20)
   2.192   	mov r16=cr.ifa
   2.193   	rsm psr.dt
   2.194 -@@ -1110,6 +1260,9 @@
   2.195 +@@ -1110,6 +1274,9 @@
   2.196   /////////////////////////////////////////////////////////////////////////////////////////
   2.197   // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
   2.198   ENTRY(key_permission)
   2.199 @@ -297,7 +311,7 @@
   2.200   	DBG_FAULT(21)
   2.201   	mov r16=cr.ifa
   2.202   	rsm psr.dt
   2.203 -@@ -1123,6 +1276,9 @@
   2.204 +@@ -1123,6 +1290,9 @@
   2.205   /////////////////////////////////////////////////////////////////////////////////////////
   2.206   // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
   2.207   ENTRY(iaccess_rights)
   2.208 @@ -307,7 +321,7 @@
   2.209   	DBG_FAULT(22)
   2.210   	mov r16=cr.ifa
   2.211   	rsm psr.dt
   2.212 -@@ -1136,6 +1292,9 @@
   2.213 +@@ -1136,6 +1306,9 @@
   2.214   /////////////////////////////////////////////////////////////////////////////////////////
   2.215   // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
   2.216   ENTRY(daccess_rights)
   2.217 @@ -317,7 +331,7 @@
   2.218   	DBG_FAULT(23)
   2.219   	mov r16=cr.ifa
   2.220   	rsm psr.dt
   2.221 -@@ -1153,8 +1312,13 @@
   2.222 +@@ -1153,8 +1326,13 @@
   2.223   	mov r16=cr.isr
   2.224   	mov r31=pr
   2.225   	;;
   2.226 @@ -331,7 +345,7 @@
   2.227   	;;
   2.228   	mov r19=24		// fault number
   2.229   	br.sptk.many dispatch_to_fault_handler
   2.230 -@@ -1164,6 +1328,9 @@
   2.231 +@@ -1164,6 +1342,9 @@
   2.232   /////////////////////////////////////////////////////////////////////////////////////////
   2.233   // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
   2.234   ENTRY(disabled_fp_reg)
   2.235 @@ -341,7 +355,7 @@
   2.236   	DBG_FAULT(25)
   2.237   	rsm psr.dfh		// ensure we can access fph
   2.238   	;;
   2.239 -@@ -1177,6 +1344,9 @@
   2.240 +@@ -1177,6 +1358,9 @@
   2.241   /////////////////////////////////////////////////////////////////////////////////////////
   2.242   // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
   2.243   ENTRY(nat_consumption)
   2.244 @@ -351,7 +365,7 @@
   2.245   	DBG_FAULT(26)
   2.246   	FAULT(26)
   2.247   END(nat_consumption)
   2.248 -@@ -1185,6 +1355,10 @@
   2.249 +@@ -1185,6 +1369,10 @@
   2.250   /////////////////////////////////////////////////////////////////////////////////////////
   2.251   // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
   2.252   ENTRY(speculation_vector)
   2.253 @@ -362,7 +376,7 @@
   2.254   	DBG_FAULT(27)
   2.255   	/*
   2.256   	 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
   2.257 -@@ -1228,6 +1402,9 @@
   2.258 +@@ -1228,6 +1416,9 @@
   2.259   /////////////////////////////////////////////////////////////////////////////////////////
   2.260   // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
   2.261   ENTRY(debug_vector)
   2.262 @@ -372,7 +386,7 @@
   2.263   	DBG_FAULT(29)
   2.264   	FAULT(29)
   2.265   END(debug_vector)
   2.266 -@@ -1236,6 +1413,9 @@
   2.267 +@@ -1236,6 +1427,9 @@
   2.268   /////////////////////////////////////////////////////////////////////////////////////////
   2.269   // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
   2.270   ENTRY(unaligned_access)
   2.271 @@ -382,7 +396,7 @@
   2.272   	DBG_FAULT(30)
   2.273   	mov r16=cr.ipsr
   2.274   	mov r31=pr		// prepare to save predicates
   2.275 -@@ -1247,6 +1427,9 @@
   2.276 +@@ -1247,6 +1441,9 @@
   2.277   /////////////////////////////////////////////////////////////////////////////////////////
   2.278   // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
   2.279   ENTRY(unsupported_data_reference)
   2.280 @@ -392,7 +406,7 @@
   2.281   	DBG_FAULT(31)
   2.282   	FAULT(31)
   2.283   END(unsupported_data_reference)
   2.284 -@@ -1255,6 +1438,9 @@
   2.285 +@@ -1255,6 +1452,9 @@
   2.286   /////////////////////////////////////////////////////////////////////////////////////////
   2.287   // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
   2.288   ENTRY(floating_point_fault)
   2.289 @@ -402,7 +416,7 @@
   2.290   	DBG_FAULT(32)
   2.291   	FAULT(32)
   2.292   END(floating_point_fault)
   2.293 -@@ -1263,6 +1449,9 @@
   2.294 +@@ -1263,6 +1463,9 @@
   2.295   /////////////////////////////////////////////////////////////////////////////////////////
   2.296   // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
   2.297   ENTRY(floating_point_trap)
   2.298 @@ -412,7 +426,7 @@
   2.299   	DBG_FAULT(33)
   2.300   	FAULT(33)
   2.301   END(floating_point_trap)
   2.302 -@@ -1271,6 +1460,9 @@
   2.303 +@@ -1271,6 +1474,9 @@
   2.304   /////////////////////////////////////////////////////////////////////////////////////////
   2.305   // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
   2.306   ENTRY(lower_privilege_trap)
   2.307 @@ -422,7 +436,7 @@
   2.308   	DBG_FAULT(34)
   2.309   	FAULT(34)
   2.310   END(lower_privilege_trap)
   2.311 -@@ -1279,6 +1471,9 @@
   2.312 +@@ -1279,6 +1485,9 @@
   2.313   /////////////////////////////////////////////////////////////////////////////////////////
   2.314   // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
   2.315   ENTRY(taken_branch_trap)
   2.316 @@ -432,7 +446,7 @@
   2.317   	DBG_FAULT(35)
   2.318   	FAULT(35)
   2.319   END(taken_branch_trap)
   2.320 -@@ -1287,6 +1482,9 @@
   2.321 +@@ -1287,6 +1496,9 @@
   2.322   /////////////////////////////////////////////////////////////////////////////////////////
   2.323   // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
   2.324   ENTRY(single_step_trap)
   2.325 @@ -442,7 +456,7 @@
   2.326   	DBG_FAULT(36)
   2.327   	FAULT(36)
   2.328   END(single_step_trap)
   2.329 -@@ -1343,6 +1541,9 @@
   2.330 +@@ -1343,6 +1555,9 @@
   2.331   /////////////////////////////////////////////////////////////////////////////////////////
   2.332   // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
   2.333   ENTRY(ia32_exception)
   2.334 @@ -452,7 +466,7 @@
   2.335   	DBG_FAULT(45)
   2.336   	FAULT(45)
   2.337   END(ia32_exception)
   2.338 -@@ -1351,6 +1552,9 @@
   2.339 +@@ -1351,6 +1566,9 @@
   2.340   /////////////////////////////////////////////////////////////////////////////////////////
   2.341   // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept  (30,31,59,70,71)
   2.342   ENTRY(ia32_intercept)
   2.343 @@ -462,7 +476,7 @@
   2.344   	DBG_FAULT(46)
   2.345   #ifdef	CONFIG_IA32_SUPPORT
   2.346   	mov r31=pr
   2.347 -@@ -1381,6 +1585,9 @@
   2.348 +@@ -1381,6 +1599,9 @@
   2.349   /////////////////////////////////////////////////////////////////////////////////////////
   2.350   // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt  (74)
   2.351   ENTRY(ia32_interrupt)
   2.352 @@ -472,7 +486,7 @@
   2.353   	DBG_FAULT(47)
   2.354   #ifdef CONFIG_IA32_SUPPORT
   2.355   	mov r31=pr
   2.356 -@@ -1510,6 +1717,39 @@
   2.357 +@@ -1510,6 +1731,39 @@
   2.358   	DBG_FAULT(67)
   2.359   	FAULT(67)
   2.360   
     3.1 --- a/xen/arch/ia64/regionreg.c	Fri Apr 01 17:44:42 2005 +0000
     3.2 +++ b/xen/arch/ia64/regionreg.c	Fri Apr 01 20:46:13 2005 +0000
     3.3 @@ -189,7 +189,7 @@ int deallocate_rid_range(struct domain *
     3.4  //  it should be unmangled
     3.5  
     3.6  //This appears to work in Xen... turn it on later so no complications yet
     3.7 -//#define CONFIG_MANGLE_RIDS
     3.8 +#define CONFIG_MANGLE_RIDS
     3.9  #ifdef CONFIG_MANGLE_RIDS
    3.10  static inline unsigned long
    3.11  vmMangleRID(unsigned long RIDVal)
     4.1 --- a/xen/arch/ia64/vcpu.c	Fri Apr 01 17:44:42 2005 +0000
     4.2 +++ b/xen/arch/ia64/vcpu.c	Fri Apr 01 20:46:13 2005 +0000
     4.3 @@ -1491,10 +1491,27 @@ void vcpu_itc_no_srlz(VCPU *vcpu, UINT64
     4.4  
     4.5  	// FIXME: validate ifa here (not in Xen space), COULD MACHINE CHECK!
     4.6  	// FIXME, must be inlined or potential for nested fault here!
     4.7 +	if ((vcpu->domain==dom0) && (logps < PAGE_SHIFT)) {
     4.8 +		printf("vcpu_itc_no_srlz: domain0 use of smaller page size!\n");
     4.9 +		//FIXME: kill domain here
    4.10 +		while(1);
    4.11 +	}
    4.12  	psr = ia64_clear_ic();
    4.13  	ia64_itc(IorD,vaddr,pte,ps); // FIXME: look for bigger mappings
    4.14  	ia64_set_psr(psr);
    4.15  	// ia64_srlz_i(); // no srls req'd, will rfi later
    4.16 +#ifdef VHPT_GLOBAL
    4.17 +	if (vcpu->domain==dom0 && ((vaddr >> 61) == 7)) {
    4.18 +		// FIXME: this is dangerous... vhpt_flush_address ensures these
    4.19 +		// addresses never get flushed.  More work needed if this
    4.20 +		// ever happens.
    4.21 +//printf("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
    4.22 +		vhpt_insert(vaddr,pte,logps<<2);
    4.23 +	}
    4.24 +	// even if domain pagesize is larger than PAGE_SIZE, just put
    4.25 +	// PAGE_SIZE mapping in the vhpt for now, else purging is complicated
    4.26 +	else vhpt_insert(vaddr,pte,PAGE_SHIFT<<2);
    4.27 +#endif
    4.28  	if (IorD & 0x4) return;  // don't place in 1-entry TLB
    4.29  	if (IorD & 0x1) {
    4.30  		vcpu_set_tr_entry(&PSCB(vcpu,itlb),pte,ps<<2,vaddr);
    4.31 @@ -1613,6 +1630,9 @@ IA64FAULT vcpu_ptc_e(VCPU *vcpu, UINT64 
    4.32  	//  base = stride1 = stride2 = 0, count0 = count 1 = 1
    4.33  
    4.34  	// FIXME: When VHPT is in place, flush that too!
    4.35 +#ifdef VHPT_GLOBAL
    4.36 +	vhpt_flush();	// FIXME: This is overdoing it
    4.37 +#endif
    4.38  	local_flush_tlb_all();
    4.39  	// just invalidate the "whole" tlb
    4.40  	vcpu_purge_tr_entry(&PSCB(vcpu,dtlb));
    4.41 @@ -1632,6 +1652,9 @@ IA64FAULT vcpu_ptc_ga(VCPU *vcpu,UINT64 
    4.42  	// FIXME: validate not flushing Xen addresses
    4.43  	// if (Xen address) return(IA64_ILLOP_FAULT);
    4.44  	// FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
    4.45 +#ifdef VHPT_GLOBAL
    4.46 +	vhpt_flush_address(vadr,addr_range);
    4.47 +#endif
    4.48  	ia64_global_tlb_purge(vadr,vadr+addr_range,PAGE_SHIFT);
    4.49  	vcpu_purge_tr_entry(&PSCB(vcpu,dtlb));
    4.50  	vcpu_purge_tr_entry(&PSCB(vcpu,itlb));
     5.1 --- a/xen/arch/ia64/vhpt.c	Fri Apr 01 17:44:42 2005 +0000
     5.2 +++ b/xen/arch/ia64/vhpt.c	Fri Apr 01 20:46:13 2005 +0000
     5.3 @@ -20,7 +20,7 @@ unsigned long vhpt_paddr, vhpt_pend, vhp
     5.4  void vhpt_flush(void)
     5.5  {
     5.6  	struct vhpt_lf_entry *v = (void *)VHPT_ADDR;
     5.7 -	int i;
     5.8 +	int i, cnt = 0;
     5.9  
    5.10  	for (i = 0; i < VHPT_NUM_ENTRIES; i++, v++) {
    5.11  		v->itir = 0;
    5.12 @@ -31,6 +31,39 @@ void vhpt_flush(void)
    5.13  	// initialize cache too???
    5.14  }
    5.15  
    5.16 +#ifdef VHPT_GLOBAL
    5.17 +void vhpt_flush_address(unsigned long vadr, unsigned long addr_range)
    5.18 +{
    5.19 +	unsigned long ps;
    5.20 +	struct vhpt_lf_entry *vlfe;
    5.21 +
    5.22 +	if ((vadr >> 61) == 7) {
    5.23 +		// no vhpt for region 7 yet, see vcpu_itc_no_srlz
    5.24 +		printf("vhpt_flush_address: region 7, spinning...\n");
    5.25 +		while(1);
    5.26 +	}
    5.27 +#if 0
    5.28 +	// this only seems to occur at shutdown, but it does occur
    5.29 +	if ((!addr_range) || addr_range & (addr_range - 1)) {
    5.30 +		printf("vhpt_flush_address: weird range, spinning...\n");
    5.31 +		while(1);
    5.32 +	}
    5.33 +//printf("************** vhpt_flush_address(%p,%p)\n",vadr,addr_range);
    5.34 +#endif
    5.35 +	while ((long)addr_range > 0) {
    5.36 +		vlfe = (struct vhpt_lf_entry *)ia64_thash(vadr);
    5.37 +		// FIXME: for now, just blow it away even if it belongs to
    5.38 +		// another domain.  Later, use ttag to check for match
    5.39 +//if (!(vlfe->ti_tag & INVALID_TI_TAG)) {
    5.40 +//printf("vhpt_flush_address: blowing away valid tag for vadr=%p\n",vadr);
    5.41 +//}
    5.42 +		vlfe->ti_tag |= INVALID_TI_TAG;
    5.43 +		addr_range -= PAGE_SIZE;
    5.44 +		vadr += PAGE_SIZE;
    5.45 +	}
    5.46 +}
    5.47 +#endif
    5.48 +
    5.49  void vhpt_map(void)
    5.50  {
    5.51  	unsigned long psr;
     6.1 --- a/xen/arch/ia64/xenasm.S	Fri Apr 01 17:44:42 2005 +0000
     6.2 +++ b/xen/arch/ia64/xenasm.S	Fri Apr 01 20:46:13 2005 +0000
     6.3 @@ -465,3 +465,16 @@ 1:
     6.4  stacked:
     6.5  	br.ret.sptk.few rp
     6.6  END(pal_emulator_static)
     6.7 +
     6.8 +GLOBAL_ENTRY(vhpt_insert)
     6.9 +//	alloc loc0 = ar.pfs, 3, 1, 0, 0
    6.10 +	mov r16=r32
    6.11 +	mov r26=r33
    6.12 +	mov r27=r34
    6.13 +	;;
    6.14 +	VHPT_INSERT()
    6.15 +//	VHPT_INSERT1()	... add collision chains later
    6.16 +//	mov ar.pfs = loc0
    6.17 +	br.ret.sptk.few rp
    6.18 +	;;
    6.19 +END(vhpt_insert)
     7.1 --- a/xen/arch/ia64/xensetup.c	Fri Apr 01 17:44:42 2005 +0000
     7.2 +++ b/xen/arch/ia64/xensetup.c	Fri Apr 01 20:46:13 2005 +0000
     7.3 @@ -309,7 +309,8 @@ printk("CONSTRUCTING DOMAIN0 CLONE #%d\n
     7.4      /* The stash space for the initial kernel image can now be freed up. */
     7.5      init_domheap_pages(ia64_boot_param->initrd_start,
     7.6  		       ia64_boot_param->initrd_start + ia64_boot_param->initrd_size);
     7.7 -    scrub_heap_pages();
     7.8 +    if (!running_on_sim)  // slow on ski and pages are pre-initialized to zero
     7.9 +	scrub_heap_pages();
    7.10  
    7.11  printk("About to call init_trace_bufs()\n");
    7.12      init_trace_bufs();
     8.1 --- a/xen/include/asm-ia64/config.h	Fri Apr 01 17:44:42 2005 +0000
     8.2 +++ b/xen/include/asm-ia64/config.h	Fri Apr 01 20:46:13 2005 +0000
     8.3 @@ -2,6 +2,7 @@
     8.4  #undef CLONE_DOMAIN0
     8.5  //#define CLONE_DOMAIN0 5
     8.6  #define DOMU_BUILD_STAGING
     8.7 +#define VHPT_GLOBAL
     8.8  
     8.9  // manufactured from component pieces
    8.10  
     9.1 --- a/xen/include/asm-ia64/vhpt.h	Fri Apr 01 17:44:42 2005 +0000
     9.2 +++ b/xen/include/asm-ia64/vhpt.h	Fri Apr 01 20:46:13 2005 +0000
     9.3 @@ -19,6 +19,7 @@
     9.4  //#define	VHPT_NUM_ENTRIES		131072
     9.5  //#define	VHPT_CACHE_MASK			131071
     9.6  //#define	VHPT_SIZE_LOG2			22	//????
     9.7 +#define	VHPT_CACHE_ENTRY_SIZE		64
     9.8  #define	VHPT_CACHE_NUM_ENTRIES		8192
     9.9  #define	VHPT_NUM_ENTRIES		524288
    9.10  #define	VHPT_CACHE_MASK			524287
    9.11 @@ -353,7 +354,7 @@ FindOne:;\
    9.12  		and r23 = r23, r24;\
    9.13  \
    9.14  \
    9.15 -		movl r17 = G_VHPT_Cache;\
    9.16 +		movl r17 = VHPT_ADDR;\
    9.17  		;;\
    9.18  \
    9.19  \