ia64/xen-unstable

changeset 5160:ebdeb9b86189

bitkeeper revision 1.1509.1.4 (4294ddbdS0zXLWNl7GY3vmRtzKddcQ)

Implement virtual short format VHPT walker

Signed-off-by: Matthew Chapman <matthewc@hp.com>
Signed-off by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Wed May 25 20:19:09 2005 +0000 (2005-05-25)
parents fa3c1c925b22
children a9d48e7fb8c5 1f630bfd83f5
files xen/arch/ia64/patch/linux-2.6.11/kregs.h xen/arch/ia64/process.c xen/arch/ia64/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/patch/linux-2.6.11/kregs.h	Tue May 24 21:40:01 2005 +0000
     1.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/kregs.h	Wed May 25 20:19:09 2005 +0000
     1.3 @@ -45,7 +45,7 @@
     1.4   #define IA64_ISR_CODE_LFETCH	4
     1.5   #define IA64_ISR_CODE_PROBEF	5
     1.6   
     1.7 -+#ifdef CONFIG_VTI
     1.8 ++#ifdef XEN
     1.9  +/* Interruption Function State */
    1.10  +#define IA64_IFS_V_BIT		63
    1.11  +#define IA64_IFS_V	(__IA64_UL(1) << IA64_IFS_V_BIT)
    1.12 @@ -60,6 +60,6 @@
    1.13  +#define IA64_PTA_SIZE   (__IA64_UL(0x3f) << IA64_PTA_SIZE_BIT)
    1.14  +#define IA64_PTA_VF     (__IA64_UL(1) << IA64_PTA_VF_BIT)
    1.15  +#define IA64_PTA_BASE   (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
    1.16 -+#endif // CONFIG_VTI
    1.17 ++#endif
    1.18  +
    1.19   #endif /* _ASM_IA64_kREGS_H */
     2.1 --- a/xen/arch/ia64/process.c	Tue May 24 21:40:01 2005 +0000
     2.2 +++ b/xen/arch/ia64/process.c	Wed May 25 20:19:09 2005 +0000
     2.3 @@ -153,7 +153,8 @@ void reflect_interruption(unsigned long 
     2.4  		}
     2.5  		vector &= ~0xf;
     2.6  		if (vector != IA64_DATA_TLB_VECTOR &&
     2.7 -		    vector != IA64_ALT_DATA_TLB_VECTOR) {
     2.8 +		    vector != IA64_ALT_DATA_TLB_VECTOR &&
     2.9 +		    vector != IA64_VHPT_TRANS_VECTOR) {
    2.10  panic_domain(regs,"psr.ic off, delivering fault=%lx,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
    2.11  	vector,regs->cr_iip,ifa,isr,PSCB(ed,iip));
    2.12  			
    2.13 @@ -167,15 +168,12 @@ panic_domain(regs,"psr.ic off, deliverin
    2.14  		return;
    2.15  
    2.16  	}
    2.17 -	if ((vector & 0xf) != IA64_FORCED_IFA) PSCB(ed,ifa) = ifa;
    2.18 -	else ifa = PSCB(ed,ifa);
    2.19 +	if ((vector & 0xf) == IA64_FORCED_IFA)
    2.20 +		ifa = PSCB(ed,tmp[0]);
    2.21  	vector &= ~0xf;
    2.22 -	if (vector == IA64_DATA_TLB_VECTOR
    2.23 -		|| vector == IA64_ALT_DATA_TLB_VECTOR
    2.24 -		|| vector == IA64_INST_TLB_VECTOR
    2.25 -		|| vector == IA64_ALT_INST_TLB_VECTOR) {
    2.26 +	PSCB(ed,ifa) = ifa;
    2.27 +	if (vector < IA64_DATA_NESTED_TLB_VECTOR) /* VHPT miss, TLB miss, Alt TLB miss */
    2.28  		vcpu_thash(ed,ifa,&PSCB(current,iha));
    2.29 -	}
    2.30  	PSCB(ed,unat) = regs->ar_unat;  // not sure if this is really needed?
    2.31  	PSCB(ed,precover_ifs) = regs->cr_ifs;
    2.32  	vcpu_bsw0(ed);
    2.33 @@ -320,7 +318,7 @@ void ia64_do_page_fault (unsigned long a
    2.34  	unsigned long psr = regs->cr_ipsr, mask, flags;
    2.35  	unsigned long iip = regs->cr_iip;
    2.36  	// FIXME should validate address here
    2.37 -	unsigned long pteval, mpaddr;
    2.38 +	unsigned long iha, pteval, mpaddr;
    2.39  	unsigned long lookup_domain_mpa(struct domain *,unsigned long);
    2.40  	unsigned long is_data = !((isr >> IA64_ISR_X_BIT) & 1UL);
    2.41  	unsigned long vector;
    2.42 @@ -346,8 +344,8 @@ void ia64_do_page_fault (unsigned long a
    2.43  		// FIXME should validate mpaddr here
    2.44  		if (d == dom0) {
    2.45  			if (address < dom0_start || address >= dom0_start + dom0_size) {
    2.46 -				//printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, iip=%p! continuing...\n",address,iip);
    2.47 -				//printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, old iip=%p!\n",address,current->vcpu_info->arch.iip);
    2.48 +				printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, iip=%p! continuing...\n",address,iip);
    2.49 +				printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, old iip=%p!\n",address,current->vcpu_info->arch.iip);
    2.50  				tdpfoo();
    2.51  			}
    2.52  		}
    2.53 @@ -365,7 +363,7 @@ void ia64_do_page_fault (unsigned long a
    2.54  
    2.55  	if (handle_lazy_cover(current, isr, regs)) return;
    2.56  if (!(address>>61)) {
    2.57 -panic_domain(0,"ia64_do_page_fault: @%p???, iip=%p, itc=%p (spinning...)\n",address,iip,ia64_get_itc());
    2.58 +panic_domain(0,"ia64_do_page_fault: @%p???, iip=%p, b0=%p, itc=%p (spinning...)\n",address,iip,regs->b0,ia64_get_itc());
    2.59  }
    2.60  	if ((isr & IA64_ISR_SP)
    2.61  	    || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH))
    2.62 @@ -378,9 +376,37 @@ panic_domain(0,"ia64_do_page_fault: @%p?
    2.63  		ia64_psr(regs)->ed = 1;
    2.64  		return;
    2.65  	}
    2.66 -	vector = vcpu_get_rr_ve(current, address) ? 
    2.67 -			(is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR)
    2.68 -			: (is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR);
    2.69 +
    2.70 +	if (vcpu_get_rr_ve(current, address) && (PSCB(current,pta) & IA64_PTA_VE))
    2.71 +	{
    2.72 +		if (PSCB(current,pta) & IA64_PTA_VF)
    2.73 +		{
    2.74 +			/* long format VHPT - not implemented */
    2.75 +			vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
    2.76 +		}
    2.77 +		else
    2.78 +		{
    2.79 +			/* short format VHPT */
    2.80 +			vcpu_thash(current, address, &iha);
    2.81 +			if (__copy_from_user(&pteval, iha, sizeof(pteval)) == 0)
    2.82 +			{
    2.83 +				/* 
    2.84 +				 * Optimisation: this VHPT walker aborts on not-present pages
    2.85 +				 * instead of inserting a not-present translation, this allows
    2.86 +				 * vectoring directly to the miss handler.
    2.87 +	\			 */
    2.88 +				if (pteval & _PAGE_P)
    2.89 +				{
    2.90 +					pteval = translate_domain_pte(pteval,address,itir);
    2.91 +					vcpu_itc_no_srlz(current,is_data?2:1,address,pteval,-1UL,(itir>>2)&0x3f);
    2.92 +					return;
    2.93 +				}
    2.94 +				else vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
    2.95 +			}
    2.96 +			else vector = IA64_VHPT_TRANS_VECTOR;
    2.97 +		}
    2.98 +	}
    2.99 +	else vector = is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR;
   2.100  	reflect_interruption(address, isr, itir, regs, vector);
   2.101  }
   2.102  
   2.103 @@ -744,11 +770,7 @@ ia64_handle_privop (unsigned long ifa, s
   2.104  	// AND ACTUALLY reflect_interruption doesn't use it anyway!
   2.105  	itir = vcpu_get_itir_on_fault(ed,ifa);
   2.106  	vector = priv_emulate(current,regs,isr);
   2.107 -	if (vector == IA64_RETRY) {
   2.108 -		reflect_interruption(ifa,isr,itir,regs,
   2.109 -			IA64_ALT_DATA_TLB_VECTOR | IA64_FORCED_IFA);
   2.110 -	}
   2.111 -	else if (vector != IA64_NO_FAULT && vector != IA64_RFI_IN_PROGRESS) {
   2.112 +	if (vector != IA64_NO_FAULT && vector != IA64_RFI_IN_PROGRESS) {
   2.113  		reflect_interruption(ifa,isr,itir,regs,vector);
   2.114  	}
   2.115  }
     3.1 --- a/xen/arch/ia64/vcpu.c	Tue May 24 21:40:01 2005 +0000
     3.2 +++ b/xen/arch/ia64/vcpu.c	Wed May 25 20:19:09 2005 +0000
     3.3 @@ -1117,7 +1117,7 @@ Privileged operation emulation routines
     3.4  
     3.5  IA64FAULT vcpu_force_data_miss(VCPU *vcpu, UINT64 ifa)
     3.6  {
     3.7 -	PSCB(vcpu,ifa) = ifa;	// privop traps don't set ifa so do it here
     3.8 +	PSCB(vcpu,tmp[0]) = ifa;	// save ifa in vcpu structure, then specify IA64_FORCED_IFA
     3.9  	return (vcpu_get_rr_ve(vcpu,ifa) ? IA64_DATA_TLB_VECTOR : IA64_ALT_DATA_TLB_VECTOR) | IA64_FORCED_IFA;
    3.10  }
    3.11  
    3.12 @@ -1206,7 +1206,7 @@ IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 
    3.13  		((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
    3.14  	UINT64 VHPT_addr2b =
    3.15  		((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;;
    3.16 -	UINT64 VHPT_addr3 = VHPT_offset & 0x3fff;
    3.17 +	UINT64 VHPT_addr3 = VHPT_offset & 0x7fff;
    3.18  	UINT64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
    3.19  			VHPT_addr3;
    3.20