ia64/xen-unstable

changeset 9852:e8383c2fcd50

[IA64] Fix vm_summary info in VTi domain

This patch fixed vm_summary info and provide correct max_itr_entry,
max_dtr_entry,impl_va_msb, rid_size and so on.

Signed-off-by: Zhang xiantao <xiantao.zhang@intel.com>
author awilliam@xenbuild.aw
date Wed Apr 26 12:40:56 2006 -0600 (2006-04-26)
parents 83f7dfe273a0
children fcfc614d3713
files xen/arch/ia64/vmx/pal_emul.c xen/include/asm-ia64/vmx_mm_def.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/pal_emul.c	Tue Apr 25 23:38:09 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/pal_emul.c	Wed Apr 26 12:40:56 2006 -0600
     1.3 @@ -21,6 +21,8 @@
     1.4  #include <asm/vmx_vcpu.h>
     1.5  #include <asm/pal.h>
     1.6  #include <asm/sal.h>
     1.7 +#include <asm/tlb.h>
     1.8 +#include <asm/vmx_mm_def.h>
     1.9  
    1.10  static void
    1.11  get_pal_parameters (VCPU *vcpu, UINT64 *gr29,
    1.12 @@ -285,9 +287,20 @@ pal_test_info(VCPU *vcpu){
    1.13  
    1.14  static struct ia64_pal_retval
    1.15  pal_vm_summary(VCPU *vcpu){
    1.16 +	pal_vm_info_1_u_t vminfo1;
    1.17 +	pal_vm_info_2_u_t vminfo2;	
    1.18  	struct ia64_pal_retval result;
    1.19 -
    1.20 -	result.status= -1; //unimplemented
    1.21 +	
    1.22 +	PAL_CALL(result,PAL_VM_SUMMARY,0,0,0);
    1.23 +	if(!result.status){
    1.24 +		vminfo1.pvi1_val = result.v0;
    1.25 +		vminfo1.pal_vm_info_1_s.max_itr_entry = NITRS -1;
    1.26 +		vminfo1.pal_vm_info_1_s.max_dtr_entry = NDTRS -1;
    1.27 +		result.v0 = vminfo1.pvi1_val;
    1.28 +		vminfo2.pal_vm_info_2_s.impl_va_msb = GUEST_IMPL_VA_MSB;
    1.29 +		vminfo2.pal_vm_info_2_s.rid_size = current->domain->arch.rid_bits;
    1.30 +		result.v1 = vminfo2.pvi2_val;
    1.31 +	} 
    1.32  	return result;
    1.33  }
    1.34  
     2.1 --- a/xen/include/asm-ia64/vmx_mm_def.h	Tue Apr 25 23:38:09 2006 -0600
     2.2 +++ b/xen/include/asm-ia64/vmx_mm_def.h	Wed Apr 26 12:40:56 2006 -0600
     2.3 @@ -28,6 +28,7 @@
     2.4  #define ARCH_PAGE_SHIFT   12
     2.5  #define ARCH_PAGE_SIZE    PSIZE(ARCH_PAGE_SHIFT)
     2.6  #define MAX_PHYS_ADDR_BITS  50
     2.7 +#define GUEST_IMPL_VA_MSB   59
     2.8  #define PMASK(size)         (~((size) - 1))
     2.9  #define PSIZE(size)         (1UL<<(size))
    2.10  //#define PAGE_SIZE_4K        PSIZE(12)