ia64/xen-unstable
changeset 18817:e3a0c3c9fd7b
x86, hpet: Fix initialisation of secondary timers.
Each channel may have different settings, and in the original
implementation, other Tn configuration will accidently overwrite T0
configuration.
Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
Each channel may have different settings, and in the original
implementation, other Tn configuration will accidently overwrite T0
configuration.
Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
author | Keir Fraser <keir.fraser@citrix.com> |
---|---|
date | Thu Nov 20 14:15:50 2008 +0000 (2008-11-20) |
parents | 368e072feb29 |
children | 857bda0c15b3 |
files | xen/arch/x86/hpet.c xen/include/asm-x86/hpet.h |
line diff
1.1 --- a/xen/arch/x86/hpet.c Thu Nov 20 14:14:20 2008 +0000 1.2 +++ b/xen/arch/x86/hpet.c Thu Nov 20 14:15:50 2008 +0000 1.3 @@ -276,9 +276,9 @@ u64 hpet_setup(void) 1.4 set_fixmap_nocache(FIX_HPET_BASE, hpet_address); 1.5 1.6 hpet_id = hpet_read32(HPET_ID); 1.7 - if ( hpet_id == 0 ) 1.8 + if ( (hpet_id & HPET_ID_REV) == 0 ) 1.9 { 1.10 - printk("BAD HPET vendor id.\n"); 1.11 + printk("BAD HPET revision id.\n"); 1.12 return 0; 1.13 } 1.14 1.15 @@ -296,9 +296,9 @@ u64 hpet_setup(void) 1.16 1.17 for ( i = 0; i <= ((hpet_id >> 8) & 31); i++ ) 1.18 { 1.19 - cfg = hpet_read32(HPET_T0_CFG + i*0x20); 1.20 + cfg = hpet_read32(HPET_Tn_CFG(i)); 1.21 cfg &= ~HPET_TN_ENABLE; 1.22 - hpet_write32(cfg & ~HPET_TN_ENABLE, HPET_T0_CFG); 1.23 + hpet_write32(cfg, HPET_Tn_CFG(i)); 1.24 } 1.25 1.26 cfg = hpet_read32(HPET_CFG);
2.1 --- a/xen/include/asm-x86/hpet.h Thu Nov 20 14:14:20 2008 +0000 2.2 +++ b/xen/include/asm-x86/hpet.h Thu Nov 20 14:15:50 2008 +0000 2.3 @@ -24,6 +24,10 @@ 2.4 #define HPET_T2_CMP 0x148 2.5 #define HPET_T2_ROUTE 0x150 2.6 2.7 +#define HPET_Tn_CFG(n) (HPET_T0_CFG + n * 0x20) 2.8 +#define HPET_Tn_CMP(n) (HPET_T0_CMP + n * 0x20) 2.9 +#define HPET_Tn_ROUTE(n) (HPET_T0_ROUTE + n * 0x20) 2.10 + 2.11 #define HPET_ID_VENDOR 0xffff0000 2.12 #define HPET_ID_LEGSUP 0x00008000 2.13 #define HPET_ID_NUMBER 0x00001f00