1.1 --- a/xen/arch/x86/hvm/vmx/intr.c	Mon Sep 10 16:13:13 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/vmx/intr.c	Mon Sep 10 16:13:35 2007 +0100
     1.3 @@ -107,22 +107,35 @@ static void enable_intr_window(struct vc
     1.4      }
     1.5  }
     1.6  
     1.7 -static void update_tpr_threshold(struct vlapic *vlapic)
     1.8 +static void update_tpr_threshold(
     1.9 +    struct vcpu *v, enum hvm_intack masked_intr_source)
    1.10  {
    1.11 -    int max_irr, tpr;
    1.12 +    struct vlapic *vlapic = vcpu_vlapic(v);
    1.13 +    int max_irr, tpr, threshold = 0;
    1.14  
    1.15      if ( !cpu_has_vmx_tpr_shadow )
    1.16          return;
    1.17  
    1.18 +    /*
    1.19 +     * If ExtInts are masked then that dominates the TPR --- the 'interrupt
    1.20 +     * window' has already been enabled in this case.
    1.21 +     */
    1.22 +    if ( (masked_intr_source == hvm_intack_lapic) ||
    1.23 +         (masked_intr_source == hvm_intack_pic) )
    1.24 +        goto out;
    1.25 +
    1.26 +    /* Is there an interrupt pending at the LAPIC? Nothing to do if not. */
    1.27      if ( !vlapic_enabled(vlapic) || 
    1.28           ((max_irr = vlapic_find_highest_irr(vlapic)) == -1) )
    1.29 -    {
    1.30 -        __vmwrite(TPR_THRESHOLD, 0);
    1.31 -        return;
    1.32 -    }
    1.33 +        goto out;
    1.34  
    1.35 +    /* Highest-priority pending interrupt is masked by the TPR? */
    1.36      tpr = vlapic_get_reg(vlapic, APIC_TASKPRI) & 0xF0;
    1.37 -    __vmwrite(TPR_THRESHOLD, (max_irr > tpr) ? (tpr >> 4) : (max_irr >> 4));
    1.38 +    if ( (tpr >> 4) >= (max_irr >> 4) )
    1.39 +        threshold = max_irr >> 4;
    1.40 +
    1.41 + out:
    1.42 +    __vmwrite(TPR_THRESHOLD, threshold);
    1.43  }
    1.44  
    1.45  asmlinkage void vmx_intr_assist(void)
    1.46 @@ -171,7 +184,7 @@ asmlinkage void vmx_intr_assist(void)
    1.47          enable_intr_window(v, intr_source);
    1.48  
    1.49   out:
    1.50 -    update_tpr_threshold(vcpu_vlapic(v));
    1.51 +    update_tpr_threshold(v, intr_source);
    1.52  }
    1.53  
    1.54  /*