ia64/xen-unstable

changeset 2239:e14eabd8803b

bitkeeper revision 1.1159.31.1 (411e31a8whkN5pph5aGYDZEaAAg8eg)

Update some Xen files to Linux 2.4.26. Hopefully will fix some IRQ
routing problems that have been reported.
author kaf24@scramble.cl.cam.ac.uk
date Sat Aug 14 15:37:12 2004 +0000 (2004-08-14)
parents 10b75f2911b6
children 4f0616f9dffe
files .rootkeys xen/arch/x86/acpi.c xen/arch/x86/io_apic.c xen/arch/x86/pci-irq.c xen/arch/x86/setup.c xen/drivers/pci/setup-bus.c xen/drivers/pci/setup-irq.c xen/drivers/pci/syscall.c xen/include/asm-x86/acpi.h xen/include/xen/pci_ids.h
line diff
     1.1 --- a/.rootkeys	Sat Aug 14 02:37:54 2004 +0000
     1.2 +++ b/.rootkeys	Sat Aug 14 15:37:12 2004 +0000
     1.3 @@ -585,10 +585,7 @@ 3ddb79bfoQcFKLf5P6wZlDl36alWdQ xen/drive
     1.4  3ddb79bfyX7-pD6XdxY_mdNrJR20iw xen/drivers/pci/pci.c
     1.5  3ddb79bf2AS7YBGwooE_Kbv7XgUqNQ xen/drivers/pci/pci.ids
     1.6  3ddb79bf7sTn85WtP_8Nc2YEmmVExQ xen/drivers/pci/quirks.c
     1.7 -3ddb79bfkVLMq5CWjZLACPDivqxq_w xen/drivers/pci/setup-bus.c
     1.8 -3ddb79bfl1H1arbB0pzAEC2uPmY_3g xen/drivers/pci/setup-irq.c
     1.9  3ddb79bfJaf0bkE1Y67bnll8-kjEPg xen/drivers/pci/setup-res.c
    1.10 -3ddb79bfIcCWJsBDNcQQE3ok2Azn-Q xen/drivers/pci/syscall.c
    1.11  3eb3c87fc79FXLA6R9TvdBJNTvQDwA xen/figlet/LICENSE
    1.12  3eb3c87fPL2T_zBb0bHlbZY-ACEKRw xen/figlet/Makefile
    1.13  3eb3c87fmKYTC5GCh_rydFakZp9ayw xen/figlet/README
     2.1 --- a/xen/arch/x86/acpi.c	Sat Aug 14 02:37:54 2004 +0000
     2.2 +++ b/xen/arch/x86/acpi.c	Sat Aug 14 15:37:12 2004 +0000
     2.3 @@ -37,7 +37,6 @@
     2.4  #include <asm/apic.h>
     2.5  #include <asm/apicdef.h>
     2.6  #include <asm/page.h>
     2.7 -#include <asm/flushtlb.h>
     2.8  #include <asm/io_apic.h>
     2.9  #include <asm/acpi.h>
    2.10  #include <asm/smpboot.h>
    2.11 @@ -45,14 +44,16 @@
    2.12  
    2.13  #define PREFIX			"ACPI: "
    2.14  
    2.15 -int acpi_lapic = 0;
    2.16 -int acpi_ioapic = 0;
    2.17 +int acpi_lapic;
    2.18 +int acpi_ioapic;
    2.19 +int acpi_strict;
    2.20  
    2.21 +acpi_interrupt_flags acpi_sci_flags __initdata;
    2.22 +int acpi_sci_override_gsi __initdata;
    2.23  /* --------------------------------------------------------------------------
    2.24                                Boot-time Configuration
    2.25     -------------------------------------------------------------------------- */
    2.26  
    2.27 -#ifdef CONFIG_ACPI_BOOT
    2.28  int acpi_noirq __initdata = 0;  /* skip ACPI IRQ initialization */
    2.29  int acpi_ht __initdata = 1;     /* enable HT */
    2.30  
    2.31 @@ -210,6 +211,59 @@ acpi_parse_ioapic (
    2.32  	return 0;
    2.33  }
    2.34  
    2.35 +/*
    2.36 + * Parse Interrupt Source Override for the ACPI SCI
    2.37 + */
    2.38 +static void
    2.39 +acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
    2.40 +{
    2.41 +	if (trigger == 0)	/* compatible SCI trigger is level */
    2.42 +		trigger = 3;
    2.43 +
    2.44 +	if (polarity == 0)	/* compatible SCI polarity is low */
    2.45 +		polarity = 3;
    2.46 +
    2.47 +	/* Command-line over-ride via acpi_sci= */
    2.48 +	if (acpi_sci_flags.trigger)
    2.49 +		trigger = acpi_sci_flags.trigger;
    2.50 +
    2.51 +	if (acpi_sci_flags.polarity)
    2.52 +		polarity = acpi_sci_flags.polarity;
    2.53 +
    2.54 +	/*
    2.55 + 	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
    2.56 +	 * If GSI is < 16, this will update its flags,
    2.57 +	 * else it will create a new mp_irqs[] entry.
    2.58 +	 */
    2.59 +	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
    2.60 +
    2.61 +	/*
    2.62 +	 * stash over-ride to indicate we've been here
    2.63 +	 * and for later update of acpi_fadt
    2.64 +	 */
    2.65 +	acpi_sci_override_gsi = gsi;
    2.66 +	return;
    2.67 +}
    2.68 +
    2.69 +static int __init
    2.70 +acpi_parse_fadt(unsigned long phys, unsigned long size)
    2.71 +{
    2.72 +        struct fadt_descriptor_rev2 *fadt =0;
    2.73 +
    2.74 +        fadt = (struct fadt_descriptor_rev2*) __acpi_map_table(phys,size);
    2.75 +        if (!fadt) {
    2.76 +                printk(KERN_WARNING PREFIX "Unable to map FADT\n");
    2.77 +                return 0;
    2.78 +        }
    2.79 +
    2.80 +#ifdef  CONFIG_ACPI_INTERPRETER
    2.81 +        /* initialize sci_int early for INT_SRC_OVR MADT parsing */
    2.82 +        acpi_fadt.sci_int = fadt->sci_int;
    2.83 +#endif
    2.84 +
    2.85 +        return 0;
    2.86 +}
    2.87 +
    2.88  
    2.89  static int __init
    2.90  acpi_parse_int_src_ovr (
    2.91 @@ -223,6 +277,12 @@ acpi_parse_int_src_ovr (
    2.92  
    2.93  	acpi_table_print_madt_entry(header);
    2.94  
    2.95 +	if (intsrc->bus_irq == acpi_fadt.sci_int) {
    2.96 +		acpi_sci_ioapic_setup(intsrc->global_irq,
    2.97 +			intsrc->flags.polarity, intsrc->flags.trigger);
    2.98 +		return 0;
    2.99 +	}
   2.100 +
   2.101  	mp_override_legacy_irq (
   2.102  		intsrc->bus_irq,
   2.103  		intsrc->flags.polarity,
   2.104 @@ -303,7 +363,7 @@ acpi_find_rsdp (void)
   2.105   * 	acpi_lapic = 1 if LAPIC found
   2.106   *	acpi_ioapic = 1 if IOAPIC found
   2.107   *	if (acpi_lapic && acpi_ioapic) smp_found_config = 1;
   2.108 - *	if acpi_blacklisted() acpi_disabled = 1;
   2.109 + *	if acpi_blacklisted() disable_acpi()
   2.110   *	acpi_irq_model=...
   2.111   *	...
   2.112   *
   2.113 @@ -330,14 +390,14 @@ acpi_boot_init (void)
   2.114  	 */
   2.115  	result = acpi_table_init();
   2.116  	if (result) {
   2.117 -		acpi_disabled = 1;
   2.118 +		disable_acpi();
   2.119  		return result;
   2.120  	}
   2.121  
   2.122  	result = acpi_blacklisted();
   2.123  	if (result) {
   2.124  		printk(KERN_NOTICE PREFIX "BIOS listed in blacklist, disabling ACPI support\n");
   2.125 -		acpi_disabled = 1;
   2.126 +		disable_acpi();
   2.127  		return result;
   2.128  	}
   2.129  
   2.130 @@ -440,6 +500,9 @@ acpi_boot_init (void)
   2.131  	/* Build a default routing table for legacy (ISA) interrupts. */
   2.132  	mp_config_acpi_legacy_irqs();
   2.133  
   2.134 +	/* Record sci_int for use when looking for MADT sci_int override */
   2.135 +	acpi_table_parse(ACPI_FADT, acpi_parse_fadt);
   2.136 +
   2.137  	result = acpi_table_parse_madt(ACPI_MADT_INT_SRC_OVR, acpi_parse_int_src_ovr);
   2.138  	if (result < 0) {
   2.139  		printk(KERN_ERR PREFIX "Error parsing interrupt source overrides entry\n");
   2.140 @@ -447,6 +510,13 @@ acpi_boot_init (void)
   2.141  		return result;
   2.142  	}
   2.143  
   2.144 +	/*
   2.145 +	 * If BIOS did not supply an INT_SRC_OVR for the SCI
   2.146 +	 * pretend we got one so we can set the SCI flags.
   2.147 +	 */
   2.148 +	if (!acpi_sci_override_gsi)
   2.149 +		acpi_sci_ioapic_setup(acpi_fadt.sci_int, 0, 0);
   2.150 +
   2.151  	result = acpi_table_parse_madt(ACPI_MADT_NMI_SRC, acpi_parse_nmi_src);
   2.152  	if (result < 0) {
   2.153  		printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
   2.154 @@ -468,17 +538,15 @@ acpi_boot_init (void)
   2.155  	return 0;
   2.156  }
   2.157  
   2.158 -#endif /*CONFIG_ACPI_BOOT*/
   2.159  
   2.160  #ifdef	CONFIG_ACPI_BUS
   2.161  /*
   2.162 - * "acpi_pic_sci=level" (current default)
   2.163 - * programs the PIC-mode SCI to Level Trigger.
   2.164 - * (NO-OP if the BIOS set Level Trigger already)
   2.165 + * acpi_pic_sci_set_trigger()
   2.166   *
   2.167 - * If a PIC-mode SCI is not recogznied or gives spurious IRQ7's
   2.168 - * it may require Edge Trigger -- use "acpi_pic_sci=edge"
   2.169 - * (NO-OP if the BIOS set Edge Trigger already)
   2.170 + * use ELCR to set PIC-mode trigger type for SCI
   2.171 + *
   2.172 + * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
   2.173 + * it may require Edge Trigger -- use "acpi_sci=edge"
   2.174   *
   2.175   * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
   2.176   * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
   2.177 @@ -486,56 +554,36 @@ acpi_boot_init (void)
   2.178   * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
   2.179   */
   2.180  
   2.181 -static __initdata int	acpi_pic_sci_trigger;	/* 0: level, 1: edge */
   2.182 -
   2.183  void __init
   2.184 -acpi_pic_sci_set_trigger(unsigned int irq)
   2.185 +acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
   2.186  {
   2.187  	unsigned char mask = 1 << (irq & 7);
   2.188  	unsigned int port = 0x4d0 + (irq >> 3);
   2.189  	unsigned char val = inb(port);
   2.190  
   2.191 -	
   2.192 +
   2.193  	printk(PREFIX "IRQ%d SCI:", irq);
   2.194  	if (!(val & mask)) {
   2.195  		printk(" Edge");
   2.196  
   2.197 -		if (!acpi_pic_sci_trigger) {
   2.198 +		if (trigger == 3) {
   2.199  			printk(" set to Level");
   2.200  			outb(val | mask, port);
   2.201  		}
   2.202  	} else {
   2.203  		printk(" Level");
   2.204  
   2.205 -		if (acpi_pic_sci_trigger) {
   2.206 +		if (trigger == 1) {
   2.207  			printk(" set to Edge");
   2.208 -			outb(val | mask, port);
   2.209 +			outb(val & ~mask, port);
   2.210  		}
   2.211  	}
   2.212  	printk(" Trigger.\n");
   2.213  }
   2.214  
   2.215 -int __init
   2.216 -acpi_pic_sci_setup(char *str)
   2.217 -{
   2.218 -	while (str && *str) {
   2.219 -		if (strncmp(str, "level", 5) == 0)
   2.220 -			acpi_pic_sci_trigger = 0;	/* force level trigger */
   2.221 -		if (strncmp(str, "edge", 4) == 0)
   2.222 -			acpi_pic_sci_trigger = 1;	/* force edge trigger */
   2.223 -		str = strchr(str, ',');
   2.224 -		if (str)
   2.225 -			str += strspn(str, ", \t");
   2.226 -	}
   2.227 -	return 1;
   2.228 -}
   2.229 -
   2.230 -__setup("acpi_pic_sci=", acpi_pic_sci_setup);
   2.231 -
   2.232  #endif /* CONFIG_ACPI_BUS */
   2.233  
   2.234  
   2.235 -
   2.236  /* --------------------------------------------------------------------------
   2.237                                Low-Level Sleep Support
   2.238     -------------------------------------------------------------------------- */
   2.239 @@ -578,7 +626,7 @@ static void acpi_create_identity_pmd (vo
   2.240  	pgd_t *pgd;
   2.241  	int i;
   2.242  
   2.243 -	ptep = (pte_t*)alloc_xenheap_page();
   2.244 +	ptep = (pte_t*)__get_free_page(GFP_KERNEL);
   2.245  
   2.246  	/* fill page with low mapping */
   2.247  	for (i = 0; i < PTRS_PER_PTE; i++)
   2.248 @@ -607,7 +655,7 @@ static void acpi_restore_pmd (void)
   2.249  {
   2.250  	set_pmd(pmd, saved_pmd);
   2.251  	local_flush_tlb();
   2.252 -	free_xenheap_page((unsigned long)ptep);
   2.253 +	free_page((unsigned long)ptep);
   2.254  }
   2.255  
   2.256  /**
   2.257 @@ -652,7 +700,8 @@ void acpi_restore_state_mem (void)
   2.258  void __init acpi_reserve_bootmem(void)
   2.259  {
   2.260  	acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE);
   2.261 -	printk(KERN_DEBUG "ACPI: have wakeup address 0x%8.8lx\n", acpi_wakeup_address);
   2.262 +	if (!acpi_wakeup_address)
   2.263 +		printk(KERN_ERR "ACPI: Cannot allocate lowmem, S3 disabled.\n");
   2.264  }
   2.265  
   2.266  void do_suspend_lowlevel_s4bios(int resume)
     3.1 --- a/xen/arch/x86/io_apic.c	Sat Aug 14 02:37:54 2004 +0000
     3.2 +++ b/xen/arch/x86/io_apic.c	Sat Aug 14 15:37:12 2004 +0000
     3.3 @@ -1797,7 +1797,11 @@ int io_apic_set_pci_routing (int ioapic,
     3.4  	entry.trigger = edge_level;
     3.5  	entry.polarity = active_high_low;
     3.6  
     3.7 -	add_pin_to_irq(irq, ioapic, pin);
     3.8 +	/*
     3.9 +	 * IRQs < 16 are already in the irq_2_pin[] map
    3.10 +	 */
    3.11 +	if (irq >= 16)
    3.12 +		add_pin_to_irq(irq, ioapic, pin);
    3.13  
    3.14  	entry.vector = assign_irq_vector(irq);
    3.15  
     4.1 --- a/xen/arch/x86/pci-irq.c	Sat Aug 14 02:37:54 2004 +0000
     4.2 +++ b/xen/arch/x86/pci-irq.c	Sat Aug 14 15:37:12 2004 +0000
     4.3 @@ -592,6 +592,7 @@ static __init int intel_router_probe(str
     4.4  		case PCI_DEVICE_ID_INTEL_82801E_0:
     4.5  		case PCI_DEVICE_ID_INTEL_82801EB_0:
     4.6  		case PCI_DEVICE_ID_INTEL_ESB_0:
     4.7 +		case PCI_DEVICE_ID_INTEL_ICH6_0:
     4.8  			r->name = "PIIX/ICH";
     4.9  			r->get = pirq_piix_get;
    4.10  			r->set = pirq_piix_set;
     5.1 --- a/xen/arch/x86/setup.c	Sat Aug 14 02:37:54 2004 +0000
     5.2 +++ b/xen/arch/x86/setup.c	Sat Aug 14 15:37:12 2004 +0000
     5.3 @@ -46,11 +46,6 @@ int acpi_disabled = 1;
     5.4  #endif
     5.5  EXPORT_SYMBOL(acpi_disabled);
     5.6  
     5.7 -#ifdef	CONFIG_ACPI_BOOT
     5.8 -extern	int __initdata acpi_ht;
     5.9 -int acpi_force __initdata = 0;
    5.10 -#endif
    5.11 -
    5.12  int phys_proc_id[NR_CPUS];
    5.13  int logical_proc_id[NR_CPUS];
    5.14  
     6.1 --- a/xen/drivers/pci/setup-bus.c	Sat Aug 14 02:37:54 2004 +0000
     6.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.3 @@ -1,400 +0,0 @@
     6.4 -/*
     6.5 - *	drivers/pci/setup-bus.c
     6.6 - *
     6.7 - * Extruded from code written by
     6.8 - *      Dave Rusling (david.rusling@reo.mts.dec.com)
     6.9 - *      David Mosberger (davidm@cs.arizona.edu)
    6.10 - *	David Miller (davem@redhat.com)
    6.11 - *
    6.12 - * Support routines for initializing a PCI subsystem.
    6.13 - */
    6.14 -
    6.15 -/*
    6.16 - * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
    6.17 - *	     PCI-PCI bridges cleanup, sorted resource allocation.
    6.18 - * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
    6.19 - *	     Converted to allocation in 3 passes, which gives
    6.20 - *	     tighter packing. Prefetchable range support.
    6.21 - */
    6.22 -
    6.23 -#include <linux/init.h>
    6.24 -#include <linux/kernel.h>
    6.25 -#include <linux/pci.h>
    6.26 -#include <linux/errno.h>
    6.27 -#include <linux/ioport.h>
    6.28 -#include <linux/cache.h>
    6.29 -#include <linux/slab.h>
    6.30 -
    6.31 -
    6.32 -#define DEBUG_CONFIG 1
    6.33 -#if DEBUG_CONFIG
    6.34 -# define DBGC(args)     printk args
    6.35 -#else
    6.36 -# define DBGC(args)
    6.37 -#endif
    6.38 -
    6.39 -#define ROUND_UP(x, a)		(((x) + (a) - 1) & ~((a) - 1))
    6.40 -
    6.41 -static int __init
    6.42 -pbus_assign_resources_sorted(struct pci_bus *bus)
    6.43 -{
    6.44 -	struct list_head *ln;
    6.45 -	struct resource *res;
    6.46 -	struct resource_list head, *list, *tmp;
    6.47 -	int idx, found_vga = 0;
    6.48 -
    6.49 -	head.next = NULL;
    6.50 -	for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
    6.51 -		struct pci_dev *dev = pci_dev_b(ln);
    6.52 -		u16 class = dev->class >> 8;
    6.53 -		u16 cmd;
    6.54 -
    6.55 -		/* First, disable the device to avoid side
    6.56 -		   effects of possibly overlapping I/O and
    6.57 -		   memory ranges.
    6.58 -		   Leave VGA enabled - for obvious reason. :-)
    6.59 -		   Same with all sorts of bridges - they may
    6.60 -		   have VGA behind them.  */
    6.61 -		if (class == PCI_CLASS_DISPLAY_VGA
    6.62 -				|| class == PCI_CLASS_NOT_DEFINED_VGA)
    6.63 -			found_vga = 1;
    6.64 -		else if (class >> 8 != PCI_BASE_CLASS_BRIDGE) {
    6.65 -			pci_read_config_word(dev, PCI_COMMAND, &cmd);
    6.66 -			cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY
    6.67 -						| PCI_COMMAND_MASTER);
    6.68 -			pci_write_config_word(dev, PCI_COMMAND, cmd);
    6.69 -		}
    6.70 -
    6.71 -		pdev_sort_resources(dev, &head);
    6.72 -	}
    6.73 -
    6.74 -	for (list = head.next; list;) {
    6.75 -		res = list->res;
    6.76 -		idx = res - &list->dev->resource[0];
    6.77 -		pci_assign_resource(list->dev, idx);
    6.78 -		tmp = list;
    6.79 -		list = list->next;
    6.80 -		xfree(tmp);
    6.81 -	}
    6.82 -
    6.83 -	return found_vga;
    6.84 -}
    6.85 -
    6.86 -/* Initialize bridges with base/limit values we have collected.
    6.87 -   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
    6.88 -   requires that if there is no I/O ports or memory behind the
    6.89 -   bridge, corresponding range must be turned off by writing base
    6.90 -   value greater than limit to the bridge's base/limit registers.  */
    6.91 -static void __init
    6.92 -pci_setup_bridge(struct pci_bus *bus)
    6.93 -{
    6.94 -	struct pbus_set_ranges_data ranges;
    6.95 -	struct pci_dev *bridge = bus->self;
    6.96 -	u32 l;
    6.97 -
    6.98 -	if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
    6.99 -		return;
   6.100 -
   6.101 -	ranges.io_start = bus->resource[0]->start;
   6.102 -	ranges.io_end = bus->resource[0]->end;
   6.103 -	ranges.mem_start = bus->resource[1]->start;
   6.104 -	ranges.mem_end = bus->resource[1]->end;
   6.105 -	ranges.prefetch_start = bus->resource[2]->start;
   6.106 -	ranges.prefetch_end = bus->resource[2]->end;
   6.107 -	pcibios_fixup_pbus_ranges(bus, &ranges);
   6.108 -
   6.109 -	DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
   6.110 -			bus->number, bridge->name));
   6.111 -
   6.112 -	/* Set up the top and bottom of the PCI I/O segment for this bus. */
   6.113 -	if (bus->resource[0]->flags & IORESOURCE_IO) {
   6.114 -		pci_read_config_dword(bridge, PCI_IO_BASE, &l);
   6.115 -		l &= 0xffff0000;
   6.116 -		l |= (ranges.io_start >> 8) & 0x00f0;
   6.117 -		l |= ranges.io_end & 0xf000;
   6.118 -		/* Set up upper 16 bits of I/O base/limit. */
   6.119 -		pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
   6.120 -				      ranges.io_start >> 16);
   6.121 -		pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
   6.122 -				      ranges.io_end >> 16);
   6.123 -		DBGC((KERN_INFO "  IO window: %04lx-%04lx\n",
   6.124 -				ranges.io_start, ranges.io_end));
   6.125 -	}
   6.126 -	else {
   6.127 -		/* Clear upper 16 bits of I/O base/limit. */
   6.128 -		pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0);
   6.129 -		l = 0x00f0;
   6.130 -		DBGC((KERN_INFO "  IO window: disabled.\n"));
   6.131 -	}
   6.132 -	pci_write_config_dword(bridge, PCI_IO_BASE, l);
   6.133 -
   6.134 -	/* Set up the top and bottom of the PCI Memory segment
   6.135 -	   for this bus. */
   6.136 -	if (bus->resource[1]->flags & IORESOURCE_MEM) {
   6.137 -		l = (ranges.mem_start >> 16) & 0xfff0;
   6.138 -		l |= ranges.mem_end & 0xfff00000;
   6.139 -		DBGC((KERN_INFO "  MEM window: %08lx-%08lx\n",
   6.140 -				ranges.mem_start, ranges.mem_end));
   6.141 -	}
   6.142 -	else {
   6.143 -		l = 0x0000fff0;
   6.144 -		DBGC((KERN_INFO "  MEM window: disabled.\n"));
   6.145 -	}
   6.146 -	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
   6.147 -
   6.148 -	/* Clear out the upper 32 bits of PREF base/limit. */
   6.149 -	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
   6.150 -	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
   6.151 -
   6.152 -	/* Set up PREF base/limit. */
   6.153 -	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
   6.154 -		l = (ranges.prefetch_start >> 16) & 0xfff0;
   6.155 -		l |= ranges.prefetch_end & 0xfff00000;
   6.156 -		DBGC((KERN_INFO "  PREFETCH window: %08lx-%08lx\n",
   6.157 -				ranges.prefetch_start, ranges.prefetch_end));
   6.158 -	}
   6.159 -	else {
   6.160 -		l = 0x0000fff0;
   6.161 -		DBGC((KERN_INFO "  PREFETCH window: disabled.\n"));
   6.162 -	}
   6.163 -	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
   6.164 -
   6.165 -	/* Check if we have VGA behind the bridge.
   6.166 -	   Enable ISA in either case (FIXME!). */
   6.167 -	l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04;
   6.168 -	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l);
   6.169 -}
   6.170 -
   6.171 -/* Check whether the bridge supports optional I/O and
   6.172 -   prefetchable memory ranges. If not, the respective
   6.173 -   base/limit registers must be read-only and read as 0. */
   6.174 -static void __init
   6.175 -pci_bridge_check_ranges(struct pci_bus *bus)
   6.176 -{
   6.177 -	u16 io;
   6.178 -	u32 pmem;
   6.179 -	struct pci_dev *bridge = bus->self;
   6.180 -	struct resource *b_res;
   6.181 -
   6.182 -	if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
   6.183 -		return;
   6.184 -
   6.185 -	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
   6.186 -	b_res[1].flags |= IORESOURCE_MEM;
   6.187 -
   6.188 -	pci_read_config_word(bridge, PCI_IO_BASE, &io);
   6.189 -	if (!io) {
   6.190 -		pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
   6.191 -		pci_read_config_word(bridge, PCI_IO_BASE, &io);
   6.192 - 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
   6.193 - 	}
   6.194 - 	if (io)
   6.195 -		b_res[0].flags |= IORESOURCE_IO;
   6.196 -	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
   6.197 -	    disconnect boundary by one PCI data phase.
   6.198 -	    Workaround: do not use prefetching on this device. */
   6.199 -	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
   6.200 -		return;
   6.201 -	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
   6.202 -	if (!pmem) {
   6.203 -		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
   6.204 -					       0xfff0fff0);
   6.205 -		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
   6.206 -		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
   6.207 -	}
   6.208 -	if (pmem)
   6.209 -		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
   6.210 -}
   6.211 -
   6.212 -/* Sizing the IO windows of the PCI-PCI bridge is trivial,
   6.213 -   since these windows have 4K granularity and the IO ranges
   6.214 -   of non-bridge PCI devices are limited to 256 bytes.
   6.215 -   We must be careful with the ISA aliasing though. */
   6.216 -static void __init
   6.217 -pbus_size_io(struct pci_bus *bus)
   6.218 -{
   6.219 -	struct list_head *ln;
   6.220 -	struct resource *b_res = bus->resource[0];
   6.221 -	unsigned long size = 0, size1 = 0;
   6.222 -
   6.223 -	if (!(b_res->flags & IORESOURCE_IO))
   6.224 -		return;
   6.225 -
   6.226 -	for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
   6.227 -		struct pci_dev *dev = pci_dev_b(ln);
   6.228 -		int i;
   6.229 -		
   6.230 -		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
   6.231 -			struct resource *r = &dev->resource[i];
   6.232 -			unsigned long r_size;
   6.233 -
   6.234 -			if (r->parent || !(r->flags & IORESOURCE_IO))
   6.235 -				continue;
   6.236 -			r_size = r->end - r->start + 1;
   6.237 -
   6.238 -			if (r_size < 0x400)
   6.239 -				/* Might be re-aligned for ISA */
   6.240 -				size += r_size;
   6.241 -			else
   6.242 -				size1 += r_size;
   6.243 -		}
   6.244 -		/* ??? Reserve some resources for CardBus. */
   6.245 -		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS)
   6.246 -			size1 += 4*1024;
   6.247 -	}
   6.248 -/* To be fixed in 2.5: we should have sort of HAVE_ISA
   6.249 -   flag in the struct pci_bus. */
   6.250 -#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
   6.251 -	size = (size & 0xff) + ((size & ~0xffUL) << 2);
   6.252 -#endif
   6.253 -	size = ROUND_UP(size + size1, 4096);
   6.254 -	if (!size) {
   6.255 -		b_res->flags = 0;
   6.256 -		return;
   6.257 -	}
   6.258 -	/* Alignment of the IO window is always 4K */
   6.259 -	b_res->start = 4096;
   6.260 -	b_res->end = b_res->start + size - 1;
   6.261 -}
   6.262 -
   6.263 -/* Calculate the size of the bus and minimal alignment which
   6.264 -   guarantees that all child resources fit in this size. */
   6.265 -static void __init
   6.266 -pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
   6.267 -{
   6.268 -	struct list_head *ln;
   6.269 -	unsigned long min_align, align, size;
   6.270 -	unsigned long aligns[12];	/* Alignments from 1Mb to 2Gb */
   6.271 -	int order, max_order;
   6.272 -	struct resource *b_res = (type & IORESOURCE_PREFETCH) ?
   6.273 -				 bus->resource[2] : bus->resource[1];
   6.274 -
   6.275 -	memset(aligns, 0, sizeof(aligns));
   6.276 -	max_order = 0;
   6.277 -	size = 0;
   6.278 -
   6.279 -	for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
   6.280 -		struct pci_dev *dev = pci_dev_b(ln);
   6.281 -		int i;
   6.282 -		
   6.283 -		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
   6.284 -			struct resource *r = &dev->resource[i];
   6.285 -			unsigned long r_size;
   6.286 -
   6.287 -			if (r->parent || (r->flags & mask) != type)
   6.288 -				continue;
   6.289 -			r_size = r->end - r->start + 1;
   6.290 -			/* For bridges size != alignment */
   6.291 -			align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
   6.292 -			order = ffz(~align) - 20;
   6.293 -			if (order > 11) {
   6.294 -				printk(KERN_WARNING "PCI: region %s/%d "
   6.295 -				       "too large: %lx-%lx\n",
   6.296 -				       dev->slot_name, i, r->start, r->end);
   6.297 -				r->flags = 0;
   6.298 -				continue;
   6.299 -			}
   6.300 -			size += r_size;
   6.301 -			if (order < 0)
   6.302 -				order = 0;
   6.303 -			/* Exclude ranges with size > align from
   6.304 -			   calculation of the alignment. */
   6.305 -			if (r_size == align)
   6.306 -				aligns[order] += align;
   6.307 -			if (order > max_order)
   6.308 -				max_order = order;
   6.309 -		}
   6.310 -		/* ??? Reserve some resources for CardBus. */
   6.311 -		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_CARDBUS) {
   6.312 -			size += 1UL << 24;		/* 16 Mb */
   6.313 -			aligns[24 - 20] += 1UL << 24;
   6.314 -		}
   6.315 -	}
   6.316 -
   6.317 -	align = 0;
   6.318 -	min_align = 0;
   6.319 -	for (order = 0; order <= max_order; order++) {
   6.320 -		unsigned long align1 = 1UL << (order + 20);
   6.321 -
   6.322 -		if (!align)
   6.323 -			min_align = align1;
   6.324 -		else if (ROUND_UP(align + min_align, min_align) < align1)
   6.325 -			min_align = align1 >> 1;
   6.326 -		align += aligns[order];
   6.327 -	}
   6.328 -	size = ROUND_UP(size, min_align);
   6.329 -	if (!size) {
   6.330 -		b_res->flags = 0;
   6.331 -		return;
   6.332 -	}
   6.333 -	b_res->start = min_align;
   6.334 -	b_res->end = size + min_align - 1;
   6.335 -}
   6.336 -
   6.337 -void __init
   6.338 -pbus_size_bridges(struct pci_bus *bus)
   6.339 -{
   6.340 -	struct list_head *ln;
   6.341 -	unsigned long mask, type;
   6.342 -
   6.343 -	for (ln=bus->children.next; ln != &bus->children; ln=ln->next)
   6.344 -		pbus_size_bridges(pci_bus_b(ln));
   6.345 -
   6.346 -	/* The root bus? */
   6.347 -	if (!bus->self)
   6.348 -		return;
   6.349 -
   6.350 -	pci_bridge_check_ranges(bus);
   6.351 -
   6.352 -	pbus_size_io(bus);
   6.353 -
   6.354 -	mask = type = IORESOURCE_MEM;
   6.355 -	/* If the bridge supports prefetchable range, size it separately. */
   6.356 -	if (bus->resource[2] &&
   6.357 -	    bus->resource[2]->flags & IORESOURCE_PREFETCH) {
   6.358 -		pbus_size_mem(bus, IORESOURCE_PREFETCH, IORESOURCE_PREFETCH);
   6.359 -		mask |= IORESOURCE_PREFETCH;	/* Size non-prefetch only. */
   6.360 -	}
   6.361 -	pbus_size_mem(bus, mask, type);
   6.362 -}
   6.363 -
   6.364 -void __init
   6.365 -pbus_assign_resources(struct pci_bus *bus)
   6.366 -{
   6.367 -	struct list_head *ln;
   6.368 -	int found_vga = pbus_assign_resources_sorted(bus);
   6.369 -
   6.370 -	if (found_vga) {
   6.371 -		struct pci_bus *b;
   6.372 -
   6.373 -		/* Propagate presence of the VGA to upstream bridges */
   6.374 -		for (b = bus; b->parent; b = b->parent) {
   6.375 -			b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA;
   6.376 -		}
   6.377 -	}
   6.378 -	for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
   6.379 -		struct pci_bus *b = pci_bus_b(ln);
   6.380 -
   6.381 -		pbus_assign_resources(b);
   6.382 -		pci_setup_bridge(b);
   6.383 -	}
   6.384 -}
   6.385 -
   6.386 -void __init
   6.387 -pci_assign_unassigned_resources(void)
   6.388 -{
   6.389 -	struct list_head *ln;
   6.390 -	struct pci_dev *dev;
   6.391 -
   6.392 -	/* Depth first, calculate sizes and alignments of all
   6.393 -	   subordinate buses. */
   6.394 -	for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
   6.395 -		pbus_size_bridges(pci_bus_b(ln));
   6.396 -	/* Depth last, allocate resources and update the hardware. */
   6.397 -	for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
   6.398 -		pbus_assign_resources(pci_bus_b(ln));
   6.399 -
   6.400 -	pci_for_each_dev(dev) {
   6.401 -		pdev_enable_device(dev);
   6.402 -	}
   6.403 -}
     7.1 --- a/xen/drivers/pci/setup-irq.c	Sat Aug 14 02:37:54 2004 +0000
     7.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.3 @@ -1,71 +0,0 @@
     7.4 -/*
     7.5 - *	drivers/pci/setup-irq.c
     7.6 - *
     7.7 - * Extruded from code written by
     7.8 - *      Dave Rusling (david.rusling@reo.mts.dec.com)
     7.9 - *      David Mosberger (davidm@cs.arizona.edu)
    7.10 - *	David Miller (davem@redhat.com)
    7.11 - *
    7.12 - * Support routines for initializing a PCI subsystem.
    7.13 - */
    7.14 -
    7.15 -
    7.16 -#include <xen/init.h>
    7.17 -#include <xen/kernel.h>
    7.18 -#include <xen/pci.h>
    7.19 -#include <xen/errno.h>
    7.20 -#include <xen/ioport.h>
    7.21 -#include <xen/cache.h>
    7.22 -
    7.23 -
    7.24 -#define DEBUG_CONFIG 0
    7.25 -#if DEBUG_CONFIG
    7.26 -# define DBGC(args)     printk args
    7.27 -#else
    7.28 -# define DBGC(args)
    7.29 -#endif
    7.30 -
    7.31 -
    7.32 -static void __init
    7.33 -pdev_fixup_irq(struct pci_dev *dev,
    7.34 -	       u8 (*swizzle)(struct pci_dev *, u8 *),
    7.35 -	       int (*map_irq)(struct pci_dev *, u8, u8))
    7.36 -{
    7.37 -	u8 pin, slot;
    7.38 -	int irq;
    7.39 -
    7.40 -	/* If this device is not on the primary bus, we need to figure out
    7.41 -	   which interrupt pin it will come in on.   We know which slot it
    7.42 -	   will come in on 'cos that slot is where the bridge is.   Each
    7.43 -	   time the interrupt line passes through a PCI-PCI bridge we must
    7.44 -	   apply the swizzle function.  */
    7.45 -
    7.46 -	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
    7.47 -	/* Cope with 0 and illegal. */
    7.48 -	if (pin == 0 || pin > 4)
    7.49 -		pin = 1;
    7.50 -
    7.51 -	/* Follow the chain of bridges, swizzling as we go.  */
    7.52 -	slot = (*swizzle)(dev, &pin);
    7.53 -
    7.54 -	irq = (*map_irq)(dev, slot, pin);
    7.55 -	if (irq == -1)
    7.56 -		irq = 0;
    7.57 -	dev->irq = irq;
    7.58 -
    7.59 -	DBGC((KERN_ERR "PCI fixup irq: (%s) got %d\n", dev->name, dev->irq));
    7.60 -
    7.61 -	/* Always tell the device, so the driver knows what is
    7.62 -	   the real IRQ to use; the device does not use it. */
    7.63 -	pcibios_update_irq(dev, irq);
    7.64 -}
    7.65 -
    7.66 -void __init
    7.67 -pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
    7.68 -	       int (*map_irq)(struct pci_dev *, u8, u8))
    7.69 -{
    7.70 -	struct pci_dev *dev;
    7.71 -	pci_for_each_dev(dev) {
    7.72 -		pdev_fixup_irq(dev, swizzle, map_irq);
    7.73 -	}
    7.74 -}
     8.1 --- a/xen/drivers/pci/syscall.c	Sat Aug 14 02:37:54 2004 +0000
     8.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.3 @@ -1,144 +0,0 @@
     8.4 -/*
     8.5 - *	pci_syscall.c
     8.6 - *
     8.7 - * For architectures where we want to allow direct access
     8.8 - * to the PCI config stuff - it would probably be preferable
     8.9 - * on PCs too, but there people just do it by hand with the
    8.10 - * magic northbridge registers..
    8.11 - */
    8.12 -
    8.13 -#include <xen/sched.h>
    8.14 -#include <xen/errno.h>
    8.15 -#include <xen/pci.h>
    8.16 -#include <xen/smp_lock.h>
    8.17 -#include <asm/uaccess.h>
    8.18 -
    8.19 -
    8.20 -asmlinkage long
    8.21 -sys_pciconfig_read(unsigned long bus, unsigned long dfn,
    8.22 -		   unsigned long off, unsigned long len, void *buf)
    8.23 -{
    8.24 -	struct pci_dev *dev;
    8.25 -	u8 byte;
    8.26 -	u16 word;
    8.27 -	u32 dword;
    8.28 -	long err, cfg_ret;
    8.29 -
    8.30 -	err = -EPERM;
    8.31 -	if (!capable(CAP_SYS_ADMIN))
    8.32 -		goto error;
    8.33 -
    8.34 -	err = -ENODEV;
    8.35 -	dev = pci_find_slot(bus, dfn);
    8.36 -	if (!dev)
    8.37 -		goto error;
    8.38 -
    8.39 -	lock_kernel();
    8.40 -	switch (len) {
    8.41 -	case 1:
    8.42 -		cfg_ret = pci_read_config_byte(dev, off, &byte);
    8.43 -		break;
    8.44 -	case 2:
    8.45 -		cfg_ret = pci_read_config_word(dev, off, &word);
    8.46 -		break;
    8.47 -	case 4:
    8.48 -		cfg_ret = pci_read_config_dword(dev, off, &dword);
    8.49 -		break;
    8.50 -	default:
    8.51 -		err = -EINVAL;
    8.52 -		unlock_kernel();
    8.53 -		goto error;
    8.54 -	};
    8.55 -	unlock_kernel();
    8.56 -
    8.57 -	err = -EIO;
    8.58 -	if (cfg_ret != PCIBIOS_SUCCESSFUL)
    8.59 -		goto error;
    8.60 -
    8.61 -	switch (len) {
    8.62 -	case 1:
    8.63 -		err = put_user(byte, (unsigned char *)buf);
    8.64 -		break;
    8.65 -	case 2:
    8.66 -		err = put_user(word, (unsigned short *)buf);
    8.67 -		break;
    8.68 -	case 4:
    8.69 -		err = put_user(dword, (unsigned int *)buf);
    8.70 -		break;
    8.71 -	};
    8.72 -	return err;
    8.73 -
    8.74 -error:
    8.75 -	/* ??? XFree86 doesn't even check the return value.  They
    8.76 -	   just look for 0xffffffff in the output, since that's what
    8.77 -	   they get instead of a machine check on x86.  */
    8.78 -	switch (len) {
    8.79 -	case 1:
    8.80 -		put_user(-1, (unsigned char *)buf);
    8.81 -		break;
    8.82 -	case 2:
    8.83 -		put_user(-1, (unsigned short *)buf);
    8.84 -		break;
    8.85 -	case 4:
    8.86 -		put_user(-1, (unsigned int *)buf);
    8.87 -		break;
    8.88 -	};
    8.89 -	return err;
    8.90 -}
    8.91 -
    8.92 -asmlinkage long
    8.93 -sys_pciconfig_write(unsigned long bus, unsigned long dfn,
    8.94 -		    unsigned long off, unsigned long len, void *buf)
    8.95 -{
    8.96 -	struct pci_dev *dev;
    8.97 -	u8 byte;
    8.98 -	u16 word;
    8.99 -	u32 dword;
   8.100 -	int err = 0;
   8.101 -
   8.102 -	if (!capable(CAP_SYS_ADMIN))
   8.103 -		return -EPERM;
   8.104 -	if (!pcibios_present())
   8.105 -		return -ENOSYS;
   8.106 -
   8.107 -	dev = pci_find_slot(bus, dfn);
   8.108 -	if (!dev)
   8.109 -		return -ENODEV;
   8.110 -
   8.111 -	lock_kernel();
   8.112 -	switch(len) {
   8.113 -	case 1:
   8.114 -		err = get_user(byte, (u8 *)buf);
   8.115 -		if (err)
   8.116 -			break;
   8.117 -		err = pci_write_config_byte(dev, off, byte);
   8.118 -		if (err != PCIBIOS_SUCCESSFUL)
   8.119 -			err = -EIO;
   8.120 -		break;
   8.121 -
   8.122 -	case 2:
   8.123 -		err = get_user(word, (u16 *)buf);
   8.124 -		if (err)
   8.125 -			break;
   8.126 -		err = pci_write_config_word(dev, off, word);
   8.127 -		if (err != PCIBIOS_SUCCESSFUL)
   8.128 -			err = -EIO;
   8.129 -		break;
   8.130 -
   8.131 -	case 4:
   8.132 -		err = get_user(dword, (u32 *)buf);
   8.133 -		if (err)
   8.134 -			break;
   8.135 -		err = pci_write_config_dword(dev, off, dword);
   8.136 -		if (err != PCIBIOS_SUCCESSFUL)
   8.137 -			err = -EIO;
   8.138 -		break;
   8.139 -
   8.140 -	default:
   8.141 -		err = -EINVAL;
   8.142 -		break;
   8.143 -	};
   8.144 -	unlock_kernel();
   8.145 -
   8.146 -	return err;
   8.147 -}
     9.1 --- a/xen/include/asm-x86/acpi.h	Sat Aug 14 02:37:54 2004 +0000
     9.2 +++ b/xen/include/asm-x86/acpi.h	Sat Aug 14 15:37:12 2004 +0000
     9.3 @@ -26,6 +26,9 @@
     9.4  #ifndef _ASM_ACPI_H
     9.5  #define _ASM_ACPI_H
     9.6  
     9.7 +#include <xen/config.h>
     9.8 +#include <asm/system.h>
     9.9 +
    9.10  #define COMPILER_DEPENDENT_INT64   long long
    9.11  #define COMPILER_DEPENDENT_UINT64  unsigned long long
    9.12  
    9.13 @@ -50,42 +53,36 @@
    9.14  #define ACPI_ENABLE_IRQS()  __sti()
    9.15  #define ACPI_FLUSH_CPU_CACHE()	wbinvd()
    9.16  
    9.17 -/*
    9.18 - * A brief explanation as GNU inline assembly is a bit hairy
    9.19 - *  %0 is the output parameter in EAX ("=a")
    9.20 - *  %1 and %2 are the input parameters in ECX ("c")
    9.21 - *  and an immediate value ("i") respectively
    9.22 - *  All actual register references are preceded with "%%" as in "%%edx"
    9.23 - *  Immediate values in the assembly are preceded by "$" as in "$0x1"
    9.24 - *  The final asm parameter are the operation altered non-output registers.
    9.25 - */
    9.26 +
    9.27 +static inline int
    9.28 +__acpi_acquire_global_lock (unsigned int *lock)
    9.29 +{
    9.30 +	unsigned int old, new, val;
    9.31 +	do {
    9.32 +		old = *lock;
    9.33 +		new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1));
    9.34 +		val = cmpxchg(lock, old, new);
    9.35 +	} while (unlikely (val != old));
    9.36 +	return (new < 3) ? -1 : 0;
    9.37 +}
    9.38 +
    9.39 +static inline int
    9.40 +__acpi_release_global_lock (unsigned int *lock)
    9.41 +{
    9.42 +	unsigned int old, new, val;
    9.43 +	do {
    9.44 +		old = *lock;
    9.45 +		new = old & ~0x3;
    9.46 +		val = cmpxchg(lock, old, new);
    9.47 +	} while (unlikely (val != old));
    9.48 +	return old & 0x1;
    9.49 +}
    9.50 +
    9.51  #define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \
    9.52 -    do { \
    9.53 -        int dummy; \
    9.54 -        asm("1:     movl (%1),%%eax;" \
    9.55 -            "movl   %%eax,%%edx;" \
    9.56 -            "andl   %2,%%edx;" \
    9.57 -            "btsl   $0x1,%%edx;" \
    9.58 -            "adcl   $0x0,%%edx;" \
    9.59 -            "lock;  cmpxchgl %%edx,(%1);" \
    9.60 -            "jnz    1b;" \
    9.61 -            "cmpb   $0x3,%%dl;" \
    9.62 -            "sbbl   %%eax,%%eax" \
    9.63 -            :"=a"(Acq),"=c"(dummy):"c"(GLptr),"i"(~1L):"dx"); \
    9.64 -    } while(0)
    9.65 +	((Acq) = __acpi_acquire_global_lock((unsigned int *) GLptr))
    9.66  
    9.67  #define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \
    9.68 -    do { \
    9.69 -        int dummy; \
    9.70 -        asm("1:     movl (%1),%%eax;" \
    9.71 -            "movl   %%eax,%%edx;" \
    9.72 -            "andl   %2,%%edx;" \
    9.73 -            "lock;  cmpxchgl %%edx,(%1);" \
    9.74 -            "jnz    1b;" \
    9.75 -            "andl   $0x1,%%eax" \
    9.76 -            :"=a"(Acq),"=c"(dummy):"c"(GLptr),"i"(~3L):"dx"); \
    9.77 -    } while(0)
    9.78 -
    9.79 +	((Acq) = __acpi_release_global_lock((unsigned int *) GLptr))
    9.80  
    9.81  /*
    9.82   * Math helper asm macros
    9.83 @@ -108,7 +105,10 @@
    9.84  extern int acpi_lapic;
    9.85  extern int acpi_ioapic;
    9.86  extern int acpi_noirq;
    9.87 +extern int acpi_strict;
    9.88  extern int acpi_disabled;
    9.89 +extern int acpi_ht;
    9.90 +static inline void disable_acpi(void) { acpi_disabled = 1; acpi_ht = 0; }
    9.91  
    9.92  /* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */
    9.93  #define FIX_ACPI_PAGES 4
    10.1 --- a/xen/include/xen/pci_ids.h	Sat Aug 14 02:37:54 2004 +0000
    10.2 +++ b/xen/include/xen/pci_ids.h	Sat Aug 14 15:37:12 2004 +0000
    10.3 @@ -287,6 +287,8 @@
    10.4  #define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
    10.5  /* Radeon RV280 (9200) */
    10.6  #define PCI_DEVICE_ID_ATI_RADEON_Y_	0x5960
    10.7 +#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
    10.8 +#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
    10.9  /* Radeon R300 (9700) */
   10.10  #define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
   10.11  #define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
   10.12 @@ -315,6 +317,8 @@
   10.13  #define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
   10.14  /* RadeonIGP */
   10.15  #define PCI_DEVICE_ID_ATI_RADEON_IGP	0xCAB0
   10.16 +/* ATI IXP Chipset */
   10.17 +#define PCI_DEVICE_ID_ATI_IXP_IDE	0x4349
   10.18  
   10.19  #define PCI_VENDOR_ID_VLSI		0x1004
   10.20  #define PCI_DEVICE_ID_VLSI_82C592	0x0005
   10.21 @@ -425,6 +429,7 @@
   10.22  #define PCI_DEVICE_ID_AMD_LANCE		0x2000
   10.23  #define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
   10.24  #define PCI_DEVICE_ID_AMD_SCSI		0x2020
   10.25 +#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
   10.26  #define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
   10.27  #define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
   10.28  #define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
   10.29 @@ -523,6 +528,7 @@
   10.30  #define PCI_DEVICE_ID_SI_6202		0x0002
   10.31  #define PCI_DEVICE_ID_SI_503		0x0008
   10.32  #define PCI_DEVICE_ID_SI_ACPI		0x0009
   10.33 +#define PCI_DEVICE_ID_SI_180		0x0180
   10.34  #define PCI_DEVICE_ID_SI_5597_VGA	0x0200
   10.35  #define PCI_DEVICE_ID_SI_6205		0x0205
   10.36  #define PCI_DEVICE_ID_SI_501		0x0406
   10.37 @@ -657,6 +663,8 @@
   10.38  #define PCI_DEVICE_ID_TI_4410		0xac41
   10.39  #define PCI_DEVICE_ID_TI_4451		0xac42
   10.40  #define PCI_DEVICE_ID_TI_1420		0xac51
   10.41 +#define PCI_DEVICE_ID_TI_1520		0xac55
   10.42 +#define PCI_DEVICE_ID_TI_1510		0xac56
   10.43  
   10.44  #define PCI_VENDOR_ID_SONY		0x104d
   10.45  #define PCI_DEVICE_ID_SONY_CXD3222	0x8039
   10.46 @@ -750,6 +758,7 @@
   10.47  #define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
   10.48  #define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
   10.49  #define PCI_DEVICE_ID_APPLE_UNI_N_FW2	0x0030
   10.50 +#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
   10.51  
   10.52  #define PCI_VENDOR_ID_YAMAHA		0x1073
   10.53  #define PCI_DEVICE_ID_YAMAHA_724	0x0004
   10.54 @@ -969,9 +978,15 @@
   10.55  #define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
   10.56  #define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
   10.57  #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
   10.58 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
   10.59 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
   10.60  #define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
   10.61  #define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
   10.62 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
   10.63  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
   10.64 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
   10.65 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
   10.66 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
   10.67  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
   10.68  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
   10.69  #define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
   10.70 @@ -1677,6 +1692,12 @@
   10.71  #define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
   10.72  #define PCI_DEVICE_ID_BCM4401		0x4401
   10.73  
   10.74 +#define PCI_VENDOR_ID_ENE		0x1524
   10.75 +#define PCI_DEVICE_ID_ENE_1211		0x1211
   10.76 +#define PCI_DEVICE_ID_ENE_1225		0x1225
   10.77 +#define PCI_DEVICE_ID_ENE_1410		0x1410
   10.78 +#define PCI_DEVICE_ID_ENE_1420		0x1420
   10.79 +
   10.80  #define PCI_VENDOR_ID_SYBA		0x1592
   10.81  #define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
   10.82  #define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
   10.83 @@ -1853,7 +1874,7 @@
   10.84  #define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
   10.85  #define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
   10.86  #define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
   10.87 -#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
   10.88 +#define PCI_DEVICE_ID_INTEL_82801DB_12	0x24cc
   10.89  #define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
   10.90  #define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
   10.91  #define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
   10.92 @@ -1880,6 +1901,10 @@
   10.93  #define PCI_DEVICE_ID_INTEL_ESB_11	0x25ac
   10.94  #define PCI_DEVICE_ID_INTEL_ESB_12	0x25ad
   10.95  #define PCI_DEVICE_ID_INTEL_ESB_13	0x25ae
   10.96 +#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
   10.97 +#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
   10.98 +#define PCI_DEVICE_ID_INTEL_ICH6_2	0x266f
   10.99 +#define PCI_DEVICE_ID_INTEL_ICH6_3	0x266e
  10.100  #define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
  10.101  #define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
  10.102  #define PCI_DEVICE_ID_INTEL_80310	0x530d