ia64/xen-unstable

changeset 12294:e10a13f13207

[XEN] Fix 64-bit build.

This required fiddling the asm constraints of the atomic bitops. It
seems gcc isn't entirely happy with "+m": the manual says that the
'+' modifier should be used only when a register constraint is
available.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@localhost.localdomain
date Tue Nov 07 23:14:09 2006 +0000 (2006-11-07)
parents e32b74b2d7f4
children 8d0e06c38c0c
files xen/arch/x86/hvm/vioapic.c xen/arch/x86/hvm/vmx/vmcs.c xen/include/asm-x86/bitops.h
line diff
     1.1 --- a/xen/arch/x86/hvm/vioapic.c	Tue Nov 07 18:13:12 2006 +0000
     1.2 +++ b/xen/arch/x86/hvm/vioapic.c	Tue Nov 07 23:14:09 2006 +0000
     1.3 @@ -399,7 +399,8 @@ static void ioapic_deliver(struct vioapi
     1.4      struct vlapic *target;
     1.5  
     1.6      HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
     1.7 -                "dest %x dest_mode %x delivery_mode %x vector %x trig_mode %x\n",
     1.8 +                "dest=%x dest_mode=%x delivery_mode=%x "
     1.9 +                "vector=%x trig_mode=%x\n",
    1.10                  dest, dest_mode, delivery_mode, vector, trig_mode);
    1.11  
    1.12      deliver_bitmask = ioapic_get_delivery_bitmask(
    1.13 @@ -430,8 +431,8 @@ static void ioapic_deliver(struct vioapi
    1.14          }
    1.15          else
    1.16          {
    1.17 -            HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
    1.18 -                        "null round robin mask %x vector %x delivery_mode %x\n",
    1.19 +            HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "null round robin: "
    1.20 +                        "mask=%x vector=%x delivery_mode=%x\n",
    1.21                          deliver_bitmask, vector, dest_LowestPrio);
    1.22          }
    1.23          break;
     2.1 --- a/xen/arch/x86/hvm/vmx/vmcs.c	Tue Nov 07 18:13:12 2006 +0000
     2.2 +++ b/xen/arch/x86/hvm/vmx/vmcs.c	Tue Nov 07 23:14:09 2006 +0000
     2.3 @@ -420,7 +420,7 @@ static int construct_vmcs(struct vcpu *v
     2.4      error |= __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
     2.5                         v->arch.hvm_vcpu.u.vmx.exec_control);
     2.6      error |= __vmwrite(VIRTUAL_APIC_PAGE_ADDR,
     2.7 -                       page_to_maddr(v->arch.hvm_vcpu.vlapic->regs_page));
     2.8 +                       page_to_maddr(vcpu_vlapic(v)->regs_page));
     2.9      error |= __vmwrite(TPR_THRESHOLD, 0);
    2.10  #endif
    2.11  
     3.1 --- a/xen/include/asm-x86/bitops.h	Tue Nov 07 18:13:12 2006 +0000
     3.2 +++ b/xen/include/asm-x86/bitops.h	Tue Nov 07 23:14:09 2006 +0000
     3.3 @@ -14,10 +14,12 @@
     3.4  #endif
     3.5  
     3.6  /*
     3.7 - * We use the "+m" constraint because the memory operand is both read from
     3.8 - * and written to. Since the operand is in fact a word array, we also
     3.9 - * specify "memory" in the clobbers list to indicate that words other than
    3.10 - * the one directly addressed by the memory operand may be modified.
    3.11 + * We specify the memory operand as both input and output because the memory
    3.12 + * operand is both read from and written to. Since the operand is in fact a
    3.13 + * word array, we also specify "memory" in the clobbers list to indicate that
    3.14 + * words other than the one directly addressed by the memory operand may be
    3.15 + * modified. We don't use "+m" because the gcc manual says that it should be
    3.16 + * used only when the constraint allows the operand to reside in a register.
    3.17   */
    3.18  
    3.19  #define ADDR (*(volatile long *) addr)
    3.20 @@ -36,8 +38,8 @@ static __inline__ void set_bit(int nr, v
    3.21  {
    3.22  	__asm__ __volatile__( LOCK_PREFIX
    3.23  		"btsl %1,%0"
    3.24 -		:"+m" (ADDR)
    3.25 -		:"dIr" (nr) : "memory");
    3.26 +		:"=m" (ADDR)
    3.27 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.28  }
    3.29  
    3.30  /**
    3.31 @@ -53,8 +55,8 @@ static __inline__ void __set_bit(int nr,
    3.32  {
    3.33  	__asm__(
    3.34  		"btsl %1,%0"
    3.35 -		:"+m" (ADDR)
    3.36 -		:"dIr" (nr) : "memory");
    3.37 +		:"=m" (ADDR)
    3.38 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.39  }
    3.40  
    3.41  /**
    3.42 @@ -71,8 +73,8 @@ static __inline__ void clear_bit(int nr,
    3.43  {
    3.44  	__asm__ __volatile__( LOCK_PREFIX
    3.45  		"btrl %1,%0"
    3.46 -		:"+m" (ADDR)
    3.47 -		:"dIr" (nr) : "memory");
    3.48 +		:"=m" (ADDR)
    3.49 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.50  }
    3.51  
    3.52  /**
    3.53 @@ -88,8 +90,8 @@ static __inline__ void __clear_bit(int n
    3.54  {
    3.55  	__asm__(
    3.56  		"btrl %1,%0"
    3.57 -		:"+m" (ADDR)
    3.58 -		:"dIr" (nr) : "memory");
    3.59 +		:"=m" (ADDR)
    3.60 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.61  }
    3.62  
    3.63  #define smp_mb__before_clear_bit()	barrier()
    3.64 @@ -108,8 +110,8 @@ static __inline__ void __change_bit(int 
    3.65  {
    3.66  	__asm__ __volatile__(
    3.67  		"btcl %1,%0"
    3.68 -		:"+m" (ADDR)
    3.69 -		:"dIr" (nr) : "memory");
    3.70 +		:"=m" (ADDR)
    3.71 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.72  }
    3.73  
    3.74  /**
    3.75 @@ -125,8 +127,8 @@ static __inline__ void change_bit(int nr
    3.76  {
    3.77  	__asm__ __volatile__( LOCK_PREFIX
    3.78  		"btcl %1,%0"
    3.79 -		:"+m" (ADDR)
    3.80 -		:"dIr" (nr) : "memory");
    3.81 +		:"=m" (ADDR)
    3.82 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.83  }
    3.84  
    3.85  /**
    3.86 @@ -143,8 +145,8 @@ static __inline__ int test_and_set_bit(i
    3.87  
    3.88  	__asm__ __volatile__( LOCK_PREFIX
    3.89  		"btsl %2,%1\n\tsbbl %0,%0"
    3.90 -		:"=r" (oldbit),"+m" (ADDR)
    3.91 -		:"dIr" (nr) : "memory");
    3.92 +		:"=r" (oldbit),"=m" (ADDR)
    3.93 +		:"dIr" (nr), "m" (ADDR) : "memory");
    3.94  	return oldbit;
    3.95  }
    3.96  
    3.97 @@ -163,8 +165,8 @@ static __inline__ int __test_and_set_bit
    3.98  
    3.99  	__asm__(
   3.100  		"btsl %2,%1\n\tsbbl %0,%0"
   3.101 -		:"=r" (oldbit),"+m" (ADDR)
   3.102 -		:"dIr" (nr) : "memory");
   3.103 +		:"=r" (oldbit),"=m" (ADDR)
   3.104 +		:"dIr" (nr), "m" (ADDR) : "memory");
   3.105  	return oldbit;
   3.106  }
   3.107  
   3.108 @@ -182,8 +184,8 @@ static __inline__ int test_and_clear_bit
   3.109  
   3.110  	__asm__ __volatile__( LOCK_PREFIX
   3.111  		"btrl %2,%1\n\tsbbl %0,%0"
   3.112 -		:"=r" (oldbit),"+m" (ADDR)
   3.113 -		:"dIr" (nr) : "memory");
   3.114 +		:"=r" (oldbit),"=m" (ADDR)
   3.115 +		:"dIr" (nr), "m" (ADDR) : "memory");
   3.116  	return oldbit;
   3.117  }
   3.118  
   3.119 @@ -202,8 +204,8 @@ static __inline__ int __test_and_clear_b
   3.120  
   3.121  	__asm__(
   3.122  		"btrl %2,%1\n\tsbbl %0,%0"
   3.123 -		:"=r" (oldbit),"+m" (ADDR)
   3.124 -		:"dIr" (nr) : "memory");
   3.125 +		:"=r" (oldbit),"=m" (ADDR)
   3.126 +		:"dIr" (nr), "m" (ADDR) : "memory");
   3.127  	return oldbit;
   3.128  }
   3.129  
   3.130 @@ -214,8 +216,8 @@ static __inline__ int __test_and_change_
   3.131  
   3.132  	__asm__ __volatile__(
   3.133  		"btcl %2,%1\n\tsbbl %0,%0"
   3.134 -		:"=r" (oldbit),"+m" (ADDR)
   3.135 -		:"dIr" (nr) : "memory");
   3.136 +		:"=r" (oldbit),"=m" (ADDR)
   3.137 +		:"dIr" (nr), "m" (ADDR) : "memory");
   3.138  	return oldbit;
   3.139  }
   3.140  
   3.141 @@ -233,8 +235,8 @@ static __inline__ int test_and_change_bi
   3.142  
   3.143  	__asm__ __volatile__( LOCK_PREFIX
   3.144  		"btcl %2,%1\n\tsbbl %0,%0"
   3.145 -		:"=r" (oldbit),"+m" (ADDR)
   3.146 -		:"dIr" (nr) : "memory");
   3.147 +		:"=r" (oldbit),"=m" (ADDR)
   3.148 +		:"dIr" (nr), "m" (ADDR) : "memory");
   3.149  	return oldbit;
   3.150  }
   3.151