ia64/xen-unstable

changeset 13093:de3d55c10f16

[IA64] new files from Linux 2.6.19 required for SN2 and machvec support

Signed-off-by: Jes Sorensen <jes@sgi.com>
author awilliam@xenbuild2.aw
date Wed Dec 13 11:08:40 2006 -0700 (2006-12-13)
parents c0d41ac21486
children c3c46d84d8e6
files xen/arch/ia64/linux-xen/sn/Makefile xen/arch/ia64/linux-xen/sn/kernel/Makefile xen/arch/ia64/linux-xen/sn/kernel/README.origin xen/arch/ia64/linux-xen/sn/kernel/io_init.c xen/arch/ia64/linux-xen/sn/kernel/iomv.c xen/arch/ia64/linux-xen/sn/kernel/irq.c xen/arch/ia64/linux-xen/sn/kernel/setup.c xen/arch/ia64/linux-xen/sn/kernel/sn2_smp.c xen/arch/ia64/linux/Makefile xen/arch/ia64/linux/README.origin xen/arch/ia64/linux/dig/Makefile xen/arch/ia64/linux/dig/README.origin xen/arch/ia64/linux/dig/machvec.c xen/arch/ia64/linux/hp/Makefile xen/arch/ia64/linux/hp/zx1/Makefile xen/arch/ia64/linux/hp/zx1/README.origin xen/arch/ia64/linux/hp/zx1/hpzx1_machvec.c xen/arch/ia64/linux/io.c xen/arch/ia64/linux/sn/Makefile xen/arch/ia64/linux/sn/kernel/Makefile xen/arch/ia64/linux/sn/kernel/README.origin xen/arch/ia64/linux/sn/kernel/machvec.c xen/arch/ia64/linux/sn/kernel/pio_phys.S xen/arch/ia64/linux/sn/kernel/ptc_deadlock.S xen/arch/ia64/linux/sn/pci/Makefile xen/arch/ia64/linux/sn/pci/pcibr/Makefile xen/arch/ia64/linux/sn/pci/pcibr/README.origin xen/arch/ia64/linux/sn/pci/pcibr/pcibr_reg.c xen/include/asm-ia64/linux-null/linux/ioport.h xen/include/asm-ia64/linux-xen/asm/README.origin xen/include/asm-ia64/linux-xen/asm/machvec_dig.h xen/include/asm-ia64/linux-xen/asm/machvec_hpzx1.h xen/include/asm-ia64/linux-xen/asm/machvec_sn2.h xen/include/asm-ia64/linux-xen/asm/pci.h xen/include/asm-ia64/linux-xen/asm/sn/README.origin xen/include/asm-ia64/linux-xen/asm/sn/addrs.h xen/include/asm-ia64/linux-xen/asm/sn/arch.h xen/include/asm-ia64/linux-xen/asm/sn/hubdev.h xen/include/asm-ia64/linux-xen/asm/sn/intr.h xen/include/asm-ia64/linux-xen/asm/sn/io.h xen/include/asm-ia64/linux-xen/asm/sn/nodepda.h xen/include/asm-ia64/linux-xen/asm/sn/pcibr_provider.h xen/include/asm-ia64/linux-xen/asm/sn/rw_mmr.h xen/include/asm-ia64/linux-xen/asm/sn/types.h xen/include/asm-ia64/linux-xen/linux/README.origin xen/include/asm-ia64/linux-xen/linux/device.h xen/include/asm-ia64/linux-xen/linux/kobject.h xen/include/asm-ia64/linux-xen/linux/pci.h xen/include/asm-ia64/linux/README.origin xen/include/asm-ia64/linux/asm/README.origin xen/include/asm-ia64/linux/asm/machvec_init.h xen/include/asm-ia64/linux/asm/sn/README.origin xen/include/asm-ia64/linux/asm/sn/geo.h xen/include/asm-ia64/linux/asm/sn/klconfig.h xen/include/asm-ia64/linux/asm/sn/l1.h xen/include/asm-ia64/linux/asm/sn/leds.h xen/include/asm-ia64/linux/asm/sn/module.h xen/include/asm-ia64/linux/asm/sn/pcibus_provider_defs.h xen/include/asm-ia64/linux/asm/sn/pcidev.h xen/include/asm-ia64/linux/asm/sn/pda.h xen/include/asm-ia64/linux/asm/sn/pic.h xen/include/asm-ia64/linux/asm/sn/shub_mmr.h xen/include/asm-ia64/linux/asm/sn/shubio.h xen/include/asm-ia64/linux/asm/sn/simulator.h xen/include/asm-ia64/linux/asm/sn/sn_cpuid.h xen/include/asm-ia64/linux/asm/sn/sn_feature_sets.h xen/include/asm-ia64/linux/asm/sn/tiocp.h xen/include/asm-ia64/linux/asm/sn/xbow.h xen/include/asm-ia64/linux/asm/sn/xwidgetdev.h xen/include/asm-ia64/linux/completion.h xen/include/asm-ia64/linux/ioport.h xen/include/asm-ia64/linux/klist.h xen/include/asm-ia64/linux/kref.h xen/include/asm-ia64/linux/mod_devicetable.h xen/include/asm-ia64/linux/pci_ids.h xen/include/asm-ia64/linux/pci_regs.h xen/include/asm-ia64/linux/pm.h xen/include/asm-ia64/linux/sysfs.h
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/xen/arch/ia64/linux-xen/sn/Makefile	Wed Dec 13 11:08:40 2006 -0700
     1.3 @@ -0,0 +1,1 @@
     1.4 +subdir-y += kernel
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/Makefile	Wed Dec 13 11:08:40 2006 -0700
     2.3 @@ -0,0 +1,5 @@
     2.4 +obj-y += sn2_smp.o
     2.5 +obj-y += setup.o
     2.6 +obj-y += iomv.o
     2.7 +obj-y += irq.o
     2.8 +obj-y += io_init.o
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/README.origin	Wed Dec 13 11:08:40 2006 -0700
     3.3 @@ -0,0 +1,12 @@
     3.4 +# Source files in this directory are near-identical copies of linux-2.6.19
     3.5 +# files:
     3.6 +
     3.7 +# NOTE: ALL changes to these files should be clearly marked
     3.8 +# (e.g. with #ifdef XEN or XEN in a comment) so that they can be
     3.9 +# easily updated to future versions of the corresponding Linux files.
    3.10 +
    3.11 +io_init.c		-> linux/arch/ia64/sn/kernel/io_init.c
    3.12 +iomv.c			-> linux/arch/ia64/sn/kernel/iomv.c
    3.13 +irq.c			-> linux/arch/ia64/sn/kernel/irq.c
    3.14 +setup.c			-> linux/arch/ia64/sn/kernel/setup.c
    3.15 +sn2_smp.c		-> linux/arch/ia64/sn/kernel/sn2/sn2_smp.c
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/io_init.c	Wed Dec 13 11:08:40 2006 -0700
     4.3 @@ -0,0 +1,740 @@
     4.4 +/*
     4.5 + * This file is subject to the terms and conditions of the GNU General Public
     4.6 + * License.  See the file "COPYING" in the main directory of this archive
     4.7 + * for more details.
     4.8 + *
     4.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
    4.10 + */
    4.11 +
    4.12 +#include <linux/bootmem.h>
    4.13 +#include <linux/nodemask.h>
    4.14 +#include <asm/sn/types.h>
    4.15 +#include <asm/sn/addrs.h>
    4.16 +#include <asm/sn/sn_feature_sets.h>
    4.17 +#include <asm/sn/geo.h>
    4.18 +#include <asm/sn/io.h>
    4.19 +#include <asm/sn/l1.h>
    4.20 +#include <asm/sn/module.h>
    4.21 +#include <asm/sn/pcibr_provider.h>
    4.22 +#include <asm/sn/pcibus_provider_defs.h>
    4.23 +#include <asm/sn/pcidev.h>
    4.24 +#include <asm/sn/simulator.h>
    4.25 +#include <asm/sn/sn_sal.h>
    4.26 +#include <asm/sn/tioca_provider.h>
    4.27 +#include <asm/sn/tioce_provider.h>
    4.28 +#include "xtalk/hubdev.h"
    4.29 +#include "xtalk/xwidgetdev.h"
    4.30 +
    4.31 +
    4.32 +extern void sn_init_cpei_timer(void);
    4.33 +extern void register_sn_procfs(void);
    4.34 +
    4.35 +static struct list_head sn_sysdata_list;
    4.36 +
    4.37 +/* sysdata list struct */
    4.38 +struct sysdata_el {
    4.39 +	struct list_head entry;
    4.40 +	void *sysdata;
    4.41 +};
    4.42 +
    4.43 +struct slab_info {
    4.44 +	struct hubdev_info hubdev;
    4.45 +};
    4.46 +
    4.47 +struct brick {
    4.48 +	moduleid_t id;		/* Module ID of this module        */
    4.49 +	struct slab_info slab_info[MAX_SLABS + 1];
    4.50 +};
    4.51 +
    4.52 +int sn_ioif_inited;		/* SN I/O infrastructure initialized? */
    4.53 +
    4.54 +struct sn_pcibus_provider *sn_pci_provider[PCIIO_ASIC_MAX_TYPES];	/* indexed by asic type */
    4.55 +
    4.56 +static int max_segment_number;		 /* Default highest segment number */
    4.57 +static int max_pcibus_number = 255;	/* Default highest pci bus number */
    4.58 +
    4.59 +/*
    4.60 + * Hooks and struct for unsupported pci providers
    4.61 + */
    4.62 +
    4.63 +static dma_addr_t
    4.64 +sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size, int type)
    4.65 +{
    4.66 +	return 0;
    4.67 +}
    4.68 +
    4.69 +static void
    4.70 +sn_default_pci_unmap(struct pci_dev *pdev, dma_addr_t addr, int direction)
    4.71 +{
    4.72 +	return;
    4.73 +}
    4.74 +
    4.75 +static void *
    4.76 +sn_default_pci_bus_fixup(struct pcibus_bussoft *soft, struct pci_controller *controller)
    4.77 +{
    4.78 +	return NULL;
    4.79 +}
    4.80 +
    4.81 +static struct sn_pcibus_provider sn_pci_default_provider = {
    4.82 +	.dma_map = sn_default_pci_map,
    4.83 +	.dma_map_consistent = sn_default_pci_map,
    4.84 +	.dma_unmap = sn_default_pci_unmap,
    4.85 +	.bus_fixup = sn_default_pci_bus_fixup,
    4.86 +};
    4.87 +
    4.88 +/*
    4.89 + * Retrieve the DMA Flush List given nasid, widget, and device.
    4.90 + * This list is needed to implement the WAR - Flush DMA data on PIO Reads.
    4.91 + */
    4.92 +static inline u64
    4.93 +sal_get_device_dmaflush_list(u64 nasid, u64 widget_num, u64 device_num,
    4.94 +			     u64 address)
    4.95 +{
    4.96 +	struct ia64_sal_retval ret_stuff;
    4.97 +	ret_stuff.status = 0;
    4.98 +	ret_stuff.v0 = 0;
    4.99 +
   4.100 +	SAL_CALL_NOLOCK(ret_stuff,
   4.101 +			(u64) SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST,
   4.102 +			(u64) nasid, (u64) widget_num,
   4.103 +			(u64) device_num, (u64) address, 0, 0, 0);
   4.104 +	return ret_stuff.status;
   4.105 +}
   4.106 +
   4.107 +/*
   4.108 + * Retrieve the hub device info structure for the given nasid.
   4.109 + */
   4.110 +static inline u64 sal_get_hubdev_info(u64 handle, u64 address)
   4.111 +{
   4.112 +	struct ia64_sal_retval ret_stuff;
   4.113 +	ret_stuff.status = 0;
   4.114 +	ret_stuff.v0 = 0;
   4.115 +
   4.116 +	SAL_CALL_NOLOCK(ret_stuff,
   4.117 +			(u64) SN_SAL_IOIF_GET_HUBDEV_INFO,
   4.118 +			(u64) handle, (u64) address, 0, 0, 0, 0, 0);
   4.119 +	return ret_stuff.v0;
   4.120 +}
   4.121 +
   4.122 +/*
   4.123 + * Retrieve the pci bus information given the bus number.
   4.124 + */
   4.125 +static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
   4.126 +{
   4.127 +	struct ia64_sal_retval ret_stuff;
   4.128 +	ret_stuff.status = 0;
   4.129 +	ret_stuff.v0 = 0;
   4.130 +
   4.131 +	SAL_CALL_NOLOCK(ret_stuff,
   4.132 +			(u64) SN_SAL_IOIF_GET_PCIBUS_INFO,
   4.133 +			(u64) segment, (u64) busnum, (u64) address, 0, 0, 0, 0);
   4.134 +	return ret_stuff.v0;
   4.135 +}
   4.136 +
   4.137 +/*
   4.138 + * Retrieve the pci device information given the bus and device|function number.
   4.139 + */
   4.140 +static inline u64
   4.141 +sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
   4.142 +		    u64 sn_irq_info)
   4.143 +{
   4.144 +	struct ia64_sal_retval ret_stuff;
   4.145 +	ret_stuff.status = 0;
   4.146 +	ret_stuff.v0 = 0;
   4.147 +
   4.148 +	SAL_CALL_NOLOCK(ret_stuff,
   4.149 +			(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
   4.150 +			(u64) segment, (u64) bus_number, (u64) devfn,
   4.151 +			(u64) pci_dev,
   4.152 +			sn_irq_info, 0, 0);
   4.153 +	return ret_stuff.v0;
   4.154 +}
   4.155 +
   4.156 +/*
   4.157 + * sn_pcidev_info_get() - Retrieve the pcidev_info struct for the specified
   4.158 + *			  device.
   4.159 + */
   4.160 +inline struct pcidev_info *
   4.161 +sn_pcidev_info_get(struct pci_dev *dev)
   4.162 +{
   4.163 +	struct pcidev_info *pcidev;
   4.164 +
   4.165 +	list_for_each_entry(pcidev,
   4.166 +			    &(SN_PCI_CONTROLLER(dev)->pcidev_info), pdi_list) {
   4.167 +		if (pcidev->pdi_linux_pcidev == dev) {
   4.168 +			return pcidev;
   4.169 +		}
   4.170 +	}
   4.171 +	return NULL;
   4.172 +}
   4.173 +
   4.174 +/* Older PROM flush WAR
   4.175 + *
   4.176 + * 01/16/06 -- This war will be in place until a new official PROM is released.
   4.177 + * Additionally note that the struct sn_flush_device_war also has to be
   4.178 + * removed from arch/ia64/sn/include/xtalk/hubdev.h
   4.179 + */
   4.180 +static u8 war_implemented = 0;
   4.181 +
   4.182 +static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device,
   4.183 +			       struct sn_flush_device_common *common)
   4.184 +{
   4.185 +	struct sn_flush_device_war *war_list;
   4.186 +	struct sn_flush_device_war *dev_entry;
   4.187 +	struct ia64_sal_retval isrv = {0,0,0,0};
   4.188 +
   4.189 +	if (!war_implemented) {
   4.190 +		printk(KERN_WARNING "PROM version < 4.50 -- implementing old "
   4.191 +		       "PROM flush WAR\n");
   4.192 +		war_implemented = 1;
   4.193 +	}
   4.194 +
   4.195 +	war_list = kzalloc(DEV_PER_WIDGET * sizeof(*war_list), GFP_KERNEL);
   4.196 +	if (!war_list)
   4.197 +		BUG();
   4.198 +
   4.199 +	SAL_CALL_NOLOCK(isrv, SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST,
   4.200 +			nasid, widget, __pa(war_list), 0, 0, 0 ,0);
   4.201 +	if (isrv.status)
   4.202 +		panic("sn_device_fixup_war failed: %s\n",
   4.203 +		      ia64_sal_strerror(isrv.status));
   4.204 +
   4.205 +	dev_entry = war_list + device;
   4.206 +	memcpy(common,dev_entry, sizeof(*common));
   4.207 +	kfree(war_list);
   4.208 +
   4.209 +	return isrv.status;
   4.210 +}
   4.211 +
   4.212 +/*
   4.213 + * sn_fixup_ionodes() - This routine initializes the HUB data strcuture for
   4.214 + *	each node in the system.
   4.215 + */
   4.216 +static void __init sn_fixup_ionodes(void)
   4.217 +{
   4.218 +	struct sn_flush_device_kernel *sn_flush_device_kernel;
   4.219 +	struct sn_flush_device_kernel *dev_entry;
   4.220 +	struct hubdev_info *hubdev;
   4.221 +	u64 status;
   4.222 +	u64 nasid;
   4.223 +	int i, widget, device, size;
   4.224 +
   4.225 +	/*
   4.226 +	 * Get SGI Specific HUB chipset information.
   4.227 +	 * Inform Prom that this kernel can support domain bus numbering.
   4.228 +	 */
   4.229 +	for (i = 0; i < num_cnodes; i++) {
   4.230 +		hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
   4.231 +		nasid = cnodeid_to_nasid(i);
   4.232 +		hubdev->max_segment_number = 0xffffffff;
   4.233 +		hubdev->max_pcibus_number = 0xff;
   4.234 +		status = sal_get_hubdev_info(nasid, (u64) __pa(hubdev));
   4.235 +		if (status)
   4.236 +			continue;
   4.237 +
   4.238 +		/* Save the largest Domain and pcibus numbers found. */
   4.239 +		if (hubdev->max_segment_number) {
   4.240 +			/*
   4.241 +			 * Dealing with a Prom that supports segments.
   4.242 +			 */
   4.243 +			max_segment_number = hubdev->max_segment_number;
   4.244 +			max_pcibus_number = hubdev->max_pcibus_number;
   4.245 +		}
   4.246 +
   4.247 +		/* Attach the error interrupt handlers */
   4.248 +		if (nasid & 1)
   4.249 +			ice_error_init(hubdev);
   4.250 +		else
   4.251 +			hub_error_init(hubdev);
   4.252 +
   4.253 +		for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++)
   4.254 +			hubdev->hdi_xwidget_info[widget].xwi_hubinfo = hubdev;
   4.255 +
   4.256 +		if (!hubdev->hdi_flush_nasid_list.widget_p)
   4.257 +			continue;
   4.258 +
   4.259 +		size = (HUB_WIDGET_ID_MAX + 1) *
   4.260 +			sizeof(struct sn_flush_device_kernel *);
   4.261 +		hubdev->hdi_flush_nasid_list.widget_p =
   4.262 +			kzalloc(size, GFP_KERNEL);
   4.263 +		if (!hubdev->hdi_flush_nasid_list.widget_p)
   4.264 +			BUG();
   4.265 +
   4.266 +		for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++) {
   4.267 +			size = DEV_PER_WIDGET *
   4.268 +				sizeof(struct sn_flush_device_kernel);
   4.269 +			sn_flush_device_kernel = kzalloc(size, GFP_KERNEL);
   4.270 +			if (!sn_flush_device_kernel)
   4.271 +				BUG();
   4.272 +
   4.273 +			dev_entry = sn_flush_device_kernel;
   4.274 +			for (device = 0; device < DEV_PER_WIDGET;
   4.275 +			     device++,dev_entry++) {
   4.276 +				size = sizeof(struct sn_flush_device_common);
   4.277 +				dev_entry->common = kzalloc(size, GFP_KERNEL);
   4.278 +				if (!dev_entry->common)
   4.279 +					BUG();
   4.280 +
   4.281 +				if (sn_prom_feature_available(
   4.282 +						       PRF_DEVICE_FLUSH_LIST))
   4.283 +					status = sal_get_device_dmaflush_list(
   4.284 +						     nasid, widget, device,
   4.285 +						     (u64)(dev_entry->common));
   4.286 +				else
   4.287 +					status = sn_device_fixup_war(nasid,
   4.288 +						     widget, device,
   4.289 +						     dev_entry->common);
   4.290 +				if (status != SALRET_OK)
   4.291 +					panic("SAL call failed: %s\n",
   4.292 +					      ia64_sal_strerror(status));
   4.293 +
   4.294 +				spin_lock_init(&dev_entry->sfdl_flush_lock);
   4.295 +			}
   4.296 +
   4.297 +			if (sn_flush_device_kernel)
   4.298 +				hubdev->hdi_flush_nasid_list.widget_p[widget] =
   4.299 +						       sn_flush_device_kernel;
   4.300 +	        }
   4.301 +	}
   4.302 +}
   4.303 +
   4.304 +/*
   4.305 + * sn_pci_window_fixup() - Create a pci_window for each device resource.
   4.306 + *			   Until ACPI support is added, we need this code
   4.307 + *			   to setup pci_windows for use by
   4.308 + *			   pcibios_bus_to_resource(),
   4.309 + *			   pcibios_resource_to_bus(), etc.
   4.310 + */
   4.311 +static void
   4.312 +sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
   4.313 +		    s64 * pci_addrs)
   4.314 +{
   4.315 +	struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
   4.316 +	unsigned int i;
   4.317 +	unsigned int idx;
   4.318 +	unsigned int new_count;
   4.319 +	struct pci_window *new_window;
   4.320 +
   4.321 +	if (count == 0)
   4.322 +		return;
   4.323 +	idx = controller->windows;
   4.324 +	new_count = controller->windows + count;
   4.325 +	new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
   4.326 +	if (new_window == NULL)
   4.327 +		BUG();
   4.328 +	if (controller->window) {
   4.329 +		memcpy(new_window, controller->window,
   4.330 +		       sizeof(struct pci_window) * controller->windows);
   4.331 +		kfree(controller->window);
   4.332 +	}
   4.333 +
   4.334 +	/* Setup a pci_window for each device resource. */
   4.335 +	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
   4.336 +		if (pci_addrs[i] == -1)
   4.337 +			continue;
   4.338 +
   4.339 +		new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
   4.340 +		new_window[idx].resource = dev->resource[i];
   4.341 +		idx++;
   4.342 +	}
   4.343 +
   4.344 +	controller->windows = new_count;
   4.345 +	controller->window = new_window;
   4.346 +}
   4.347 +
   4.348 +void sn_pci_unfixup_slot(struct pci_dev *dev)
   4.349 +{
   4.350 +	struct pci_dev *host_pci_dev = SN_PCIDEV_INFO(dev)->host_pci_dev;
   4.351 +
   4.352 +	sn_irq_unfixup(dev);
   4.353 +	pci_dev_put(host_pci_dev);
   4.354 +	pci_dev_put(dev);
   4.355 +}
   4.356 +
   4.357 +/*
   4.358 + * sn_pci_fixup_slot() - This routine sets up a slot's resources
   4.359 + * consistent with the Linux PCI abstraction layer.  Resources acquired
   4.360 + * from our PCI provider include PIO maps to BAR space and interrupt
   4.361 + * objects.
   4.362 + */
   4.363 +void sn_pci_fixup_slot(struct pci_dev *dev)
   4.364 +{
   4.365 +	unsigned int count = 0;
   4.366 +	int idx;
   4.367 +	int segment = pci_domain_nr(dev->bus);
   4.368 +	int status = 0;
   4.369 +	struct pcibus_bussoft *bs;
   4.370 + 	struct pci_bus *host_pci_bus;
   4.371 + 	struct pci_dev *host_pci_dev;
   4.372 +	struct pcidev_info *pcidev_info;
   4.373 +	s64 pci_addrs[PCI_ROM_RESOURCE + 1];
   4.374 + 	struct sn_irq_info *sn_irq_info;
   4.375 + 	unsigned long size;
   4.376 + 	unsigned int bus_no, devfn;
   4.377 +
   4.378 +	pci_dev_get(dev); /* for the sysdata pointer */
   4.379 +	pcidev_info = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
   4.380 +	if (!pcidev_info)
   4.381 +		BUG();		/* Cannot afford to run out of memory */
   4.382 +
   4.383 +	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
   4.384 +	if (!sn_irq_info)
   4.385 +		BUG();		/* Cannot afford to run out of memory */
   4.386 +
   4.387 +	/* Call to retrieve pci device information needed by kernel. */
   4.388 +	status = sal_get_pcidev_info((u64) segment, (u64) dev->bus->number, 
   4.389 +				     dev->devfn,
   4.390 +				     (u64) __pa(pcidev_info),
   4.391 +				     (u64) __pa(sn_irq_info));
   4.392 +	if (status)
   4.393 +		BUG(); /* Cannot get platform pci device information */
   4.394 +
   4.395 +	/* Add pcidev_info to list in sn_pci_controller struct */
   4.396 +	list_add_tail(&pcidev_info->pdi_list,
   4.397 +		      &(SN_PCI_CONTROLLER(dev->bus)->pcidev_info));
   4.398 +
   4.399 +	/* Copy over PIO Mapped Addresses */
   4.400 +	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
   4.401 +		unsigned long start, end, addr;
   4.402 +
   4.403 +		if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
   4.404 +			pci_addrs[idx] = -1;
   4.405 +			continue;
   4.406 +		}
   4.407 +
   4.408 +		start = dev->resource[idx].start;
   4.409 +		end = dev->resource[idx].end;
   4.410 +		size = end - start;
   4.411 +		if (size == 0) {
   4.412 +			pci_addrs[idx] = -1;
   4.413 +			continue;
   4.414 +		}
   4.415 +		pci_addrs[idx] = start;
   4.416 +		count++;
   4.417 +		addr = pcidev_info->pdi_pio_mapped_addr[idx];
   4.418 +		addr = ((addr << 4) >> 4) | __IA64_UNCACHED_OFFSET;
   4.419 +		dev->resource[idx].start = addr;
   4.420 +		dev->resource[idx].end = addr + size;
   4.421 +		if (dev->resource[idx].flags & IORESOURCE_IO)
   4.422 +			dev->resource[idx].parent = &ioport_resource;
   4.423 +		else
   4.424 +			dev->resource[idx].parent = &iomem_resource;
   4.425 +	}
   4.426 +	/* Create a pci_window in the pci_controller struct for
   4.427 +	 * each device resource.
   4.428 +	 */
   4.429 +	if (count > 0)
   4.430 +		sn_pci_window_fixup(dev, count, pci_addrs);
   4.431 +
   4.432 +	/*
   4.433 +	 * Using the PROMs values for the PCI host bus, get the Linux
   4.434 + 	 * PCI host_pci_dev struct and set up host bus linkages
   4.435 + 	 */
   4.436 +
   4.437 +	bus_no = (pcidev_info->pdi_slot_host_handle >> 32) & 0xff;
   4.438 +	devfn = pcidev_info->pdi_slot_host_handle & 0xffffffff;
   4.439 + 	host_pci_bus = pci_find_bus(segment, bus_no);
   4.440 + 	host_pci_dev = pci_get_slot(host_pci_bus, devfn);
   4.441 +
   4.442 +	pcidev_info->host_pci_dev = host_pci_dev;
   4.443 +	pcidev_info->pdi_linux_pcidev = dev;
   4.444 +	pcidev_info->pdi_host_pcidev_info = SN_PCIDEV_INFO(host_pci_dev);
   4.445 +	bs = SN_PCIBUS_BUSSOFT(dev->bus);
   4.446 +	pcidev_info->pdi_pcibus_info = bs;
   4.447 +
   4.448 +	if (bs && bs->bs_asic_type < PCIIO_ASIC_MAX_TYPES) {
   4.449 +		SN_PCIDEV_BUSPROVIDER(dev) = sn_pci_provider[bs->bs_asic_type];
   4.450 +	} else {
   4.451 +		SN_PCIDEV_BUSPROVIDER(dev) = &sn_pci_default_provider;
   4.452 +	}
   4.453 +
   4.454 +	/* Only set up IRQ stuff if this device has a host bus context */
   4.455 +	if (bs && sn_irq_info->irq_irq) {
   4.456 +		pcidev_info->pdi_sn_irq_info = sn_irq_info;
   4.457 +		dev->irq = pcidev_info->pdi_sn_irq_info->irq_irq;
   4.458 +		sn_irq_fixup(dev, sn_irq_info);
   4.459 +	} else {
   4.460 +		pcidev_info->pdi_sn_irq_info = NULL;
   4.461 +		kfree(sn_irq_info);
   4.462 +	}
   4.463 +}
   4.464 +
   4.465 +/*
   4.466 + * sn_pci_controller_fixup() - This routine sets up a bus's resources
   4.467 + * consistent with the Linux PCI abstraction layer.
   4.468 + */
   4.469 +void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
   4.470 +{
   4.471 +	int status;
   4.472 +	int nasid, cnode;
   4.473 +	struct pci_controller *controller;
   4.474 +	struct sn_pci_controller *sn_controller;
   4.475 +	struct pcibus_bussoft *prom_bussoft_ptr;
   4.476 +	struct hubdev_info *hubdev_info;
   4.477 +	void *provider_soft;
   4.478 +	struct sn_pcibus_provider *provider;
   4.479 +
   4.480 + 	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
   4.481 + 				     (u64) ia64_tpa(&prom_bussoft_ptr));
   4.482 + 	if (status > 0)
   4.483 +		return;		/*bus # does not exist */
   4.484 +	prom_bussoft_ptr = __va(prom_bussoft_ptr);
   4.485 +
   4.486 +	/* Allocate a sn_pci_controller, which has a pci_controller struct
   4.487 +	 * as the first member.
   4.488 +	 */
   4.489 +	sn_controller = kzalloc(sizeof(struct sn_pci_controller), GFP_KERNEL);
   4.490 +	if (!sn_controller)
   4.491 +		BUG();
   4.492 +	INIT_LIST_HEAD(&sn_controller->pcidev_info);
   4.493 +	controller = &sn_controller->pci_controller;
   4.494 +	controller->segment = segment;
   4.495 +
   4.496 +	if (bus == NULL) {
   4.497 + 		bus = pci_scan_bus(busnum, &pci_root_ops, controller);
   4.498 + 		if (bus == NULL)
   4.499 + 			goto error_return; /* error, or bus already scanned */
   4.500 + 		bus->sysdata = NULL;
   4.501 +	}
   4.502 +
   4.503 +	if (bus->sysdata)
   4.504 +		goto error_return; /* sysdata already alloc'd */
   4.505 +
   4.506 +	/*
   4.507 +	 * Per-provider fixup.  Copies the contents from prom to local
   4.508 +	 * area and links SN_PCIBUS_BUSSOFT().
   4.509 +	 */
   4.510 +
   4.511 +	if (prom_bussoft_ptr->bs_asic_type >= PCIIO_ASIC_MAX_TYPES)
   4.512 +		goto error_return; /* unsupported asic type */
   4.513 +
   4.514 +	if (prom_bussoft_ptr->bs_asic_type == PCIIO_ASIC_TYPE_PPB)
   4.515 +		goto error_return; /* no further fixup necessary */
   4.516 +
   4.517 +	provider = sn_pci_provider[prom_bussoft_ptr->bs_asic_type];
   4.518 +	if (provider == NULL)
   4.519 +		goto error_return; /* no provider registerd for this asic */
   4.520 +
   4.521 +	bus->sysdata = controller;
   4.522 +	if (provider->bus_fixup)
   4.523 +		provider_soft = (*provider->bus_fixup) (prom_bussoft_ptr, controller);
   4.524 +	else
   4.525 +		provider_soft = NULL;
   4.526 +
   4.527 +	if (provider_soft == NULL) {
   4.528 +		/* fixup failed or not applicable */
   4.529 +		bus->sysdata = NULL;
   4.530 +		goto error_return;
   4.531 +	}
   4.532 +
   4.533 +	/*
   4.534 +	 * Setup pci_windows for legacy IO and MEM space.
   4.535 +	 * (Temporary until ACPI support is in place.)
   4.536 +	 */
   4.537 +	controller->window = kcalloc(2, sizeof(struct pci_window), GFP_KERNEL);
   4.538 +	if (controller->window == NULL)
   4.539 +		BUG();
   4.540 +	controller->window[0].offset = prom_bussoft_ptr->bs_legacy_io;
   4.541 +	controller->window[0].resource.name = "legacy_io";
   4.542 +	controller->window[0].resource.flags = IORESOURCE_IO;
   4.543 +	controller->window[0].resource.start = prom_bussoft_ptr->bs_legacy_io;
   4.544 +	controller->window[0].resource.end =
   4.545 +	    controller->window[0].resource.start + 0xffff;
   4.546 +	controller->window[0].resource.parent = &ioport_resource;
   4.547 +	controller->window[1].offset = prom_bussoft_ptr->bs_legacy_mem;
   4.548 +	controller->window[1].resource.name = "legacy_mem";
   4.549 +	controller->window[1].resource.flags = IORESOURCE_MEM;
   4.550 +	controller->window[1].resource.start = prom_bussoft_ptr->bs_legacy_mem;
   4.551 +	controller->window[1].resource.end =
   4.552 +	    controller->window[1].resource.start + (1024 * 1024) - 1;
   4.553 +	controller->window[1].resource.parent = &iomem_resource;
   4.554 +	controller->windows = 2;
   4.555 +
   4.556 +	/*
   4.557 +	 * Generic bus fixup goes here.  Don't reference prom_bussoft_ptr
   4.558 +	 * after this point.
   4.559 +	 */
   4.560 +
   4.561 +	PCI_CONTROLLER(bus)->platform_data = provider_soft;
   4.562 +	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(bus)->bs_base);
   4.563 +	cnode = nasid_to_cnodeid(nasid);
   4.564 +	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
   4.565 +	SN_PCIBUS_BUSSOFT(bus)->bs_xwidget_info =
   4.566 +	    &(hubdev_info->hdi_xwidget_info[SN_PCIBUS_BUSSOFT(bus)->bs_xid]);
   4.567 +
   4.568 +	/*
   4.569 +	 * If the node information we obtained during the fixup phase is invalid
   4.570 +	 * then set controller->node to -1 (undetermined)
   4.571 +	 */
   4.572 +	if (controller->node >= num_online_nodes()) {
   4.573 +		struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus);
   4.574 +
   4.575 +		printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%u"
   4.576 +				    "L_IO=%lx L_MEM=%lx BASE=%lx\n",
   4.577 +			b->bs_asic_type, b->bs_xid, b->bs_persist_busnum,
   4.578 +			b->bs_legacy_io, b->bs_legacy_mem, b->bs_base);
   4.579 +		printk(KERN_WARNING "on node %d but only %d nodes online."
   4.580 +			"Association set to undetermined.\n",
   4.581 +			controller->node, num_online_nodes());
   4.582 +		controller->node = -1;
   4.583 +	}
   4.584 +	return;
   4.585 +
   4.586 +error_return:
   4.587 +
   4.588 +	kfree(sn_controller);
   4.589 +	return;
   4.590 +}
   4.591 +
   4.592 +void sn_bus_store_sysdata(struct pci_dev *dev)
   4.593 +{
   4.594 +	struct sysdata_el *element;
   4.595 +
   4.596 +	element = kzalloc(sizeof(struct sysdata_el), GFP_KERNEL);
   4.597 +	if (!element) {
   4.598 +		dev_dbg(dev, "%s: out of memory!\n", __FUNCTION__);
   4.599 +		return;
   4.600 +	}
   4.601 +	element->sysdata = SN_PCIDEV_INFO(dev);
   4.602 +	list_add(&element->entry, &sn_sysdata_list);
   4.603 +}
   4.604 +
   4.605 +void sn_bus_free_sysdata(void)
   4.606 +{
   4.607 +	struct sysdata_el *element;
   4.608 +	struct list_head *list, *safe;
   4.609 +
   4.610 +	list_for_each_safe(list, safe, &sn_sysdata_list) {
   4.611 +		element = list_entry(list, struct sysdata_el, entry);
   4.612 +		list_del(&element->entry);
   4.613 +		list_del(&(((struct pcidev_info *)
   4.614 +			     (element->sysdata))->pdi_list));
   4.615 +		kfree(element->sysdata);
   4.616 +		kfree(element);
   4.617 +	}
   4.618 +	return;
   4.619 +}
   4.620 +
   4.621 +/*
   4.622 + * Ugly hack to get PCI setup until we have a proper ACPI namespace.
   4.623 + */
   4.624 +
   4.625 +#define PCI_BUSES_TO_SCAN 256
   4.626 +
   4.627 +static int __init sn_pci_init(void)
   4.628 +{
   4.629 +	int i, j;
   4.630 +	struct pci_dev *pci_dev = NULL;
   4.631 +
   4.632 +	if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
   4.633 +		return 0;
   4.634 +
   4.635 +	/*
   4.636 +	 * prime sn_pci_provider[].  Individial provider init routines will
   4.637 +	 * override their respective default entries.
   4.638 +	 */
   4.639 +
   4.640 +	for (i = 0; i < PCIIO_ASIC_MAX_TYPES; i++)
   4.641 +		sn_pci_provider[i] = &sn_pci_default_provider;
   4.642 +
   4.643 +	pcibr_init_provider();
   4.644 +	tioca_init_provider();
   4.645 +	tioce_init_provider();
   4.646 +
   4.647 +	/*
   4.648 +	 * This is needed to avoid bounce limit checks in the blk layer
   4.649 +	 */
   4.650 +	ia64_max_iommu_merge_mask = ~PAGE_MASK;
   4.651 +	sn_fixup_ionodes();
   4.652 +	sn_irq_lh_init();
   4.653 +	INIT_LIST_HEAD(&sn_sysdata_list);
   4.654 +	sn_init_cpei_timer();
   4.655 +
   4.656 +#ifdef CONFIG_PROC_FS
   4.657 +	register_sn_procfs();
   4.658 +#endif
   4.659 +
   4.660 +	/* busses are not known yet ... */
   4.661 +	for (i = 0; i <= max_segment_number; i++)
   4.662 +		for (j = 0; j <= max_pcibus_number; j++)
   4.663 +			sn_pci_controller_fixup(i, j, NULL);
   4.664 +
   4.665 +	/*
   4.666 +	 * Generic Linux PCI Layer has created the pci_bus and pci_dev 
   4.667 +	 * structures - time for us to add our SN PLatform specific 
   4.668 +	 * information.
   4.669 +	 */
   4.670 +
   4.671 +	while ((pci_dev =
   4.672 +		pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL)
   4.673 +		sn_pci_fixup_slot(pci_dev);
   4.674 +
   4.675 +	sn_ioif_inited = 1;	/* sn I/O infrastructure now initialized */
   4.676 +
   4.677 +	return 0;
   4.678 +}
   4.679 +
   4.680 +/*
   4.681 + * hubdev_init_node() - Creates the HUB data structure and link them to it's 
   4.682 + *	own NODE specific data area.
   4.683 + */
   4.684 +void hubdev_init_node(nodepda_t * npda, cnodeid_t node)
   4.685 +{
   4.686 +	struct hubdev_info *hubdev_info;
   4.687 +	int size;
   4.688 +	pg_data_t *pg;
   4.689 +
   4.690 +	size = sizeof(struct hubdev_info);
   4.691 +
   4.692 +	if (node >= num_online_nodes())	/* Headless/memless IO nodes */
   4.693 +		pg = NODE_DATA(0);
   4.694 +	else
   4.695 +		pg = NODE_DATA(node);
   4.696 +
   4.697 +	hubdev_info = (struct hubdev_info *)alloc_bootmem_node(pg, size);
   4.698 +
   4.699 +	npda->pdinfo = (void *)hubdev_info;
   4.700 +}
   4.701 +
   4.702 +geoid_t
   4.703 +cnodeid_get_geoid(cnodeid_t cnode)
   4.704 +{
   4.705 +	struct hubdev_info *hubdev;
   4.706 +
   4.707 +	hubdev = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
   4.708 +	return hubdev->hdi_geoid;
   4.709 +}
   4.710 +
   4.711 +void sn_generate_path(struct pci_bus *pci_bus, char *address)
   4.712 +{
   4.713 +	nasid_t nasid;
   4.714 +	cnodeid_t cnode;
   4.715 +	geoid_t geoid;
   4.716 +	moduleid_t moduleid;
   4.717 +	u16 bricktype;
   4.718 +
   4.719 +	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
   4.720 +	cnode = nasid_to_cnodeid(nasid);
   4.721 +	geoid = cnodeid_get_geoid(cnode);
   4.722 +	moduleid = geo_module(geoid);
   4.723 +
   4.724 +	sprintf(address, "module_%c%c%c%c%.2d",
   4.725 +		'0'+RACK_GET_CLASS(MODULE_GET_RACK(moduleid)),
   4.726 +		'0'+RACK_GET_GROUP(MODULE_GET_RACK(moduleid)),
   4.727 +		'0'+RACK_GET_NUM(MODULE_GET_RACK(moduleid)),
   4.728 +		MODULE_GET_BTCHAR(moduleid), MODULE_GET_BPOS(moduleid));
   4.729 +
   4.730 +	/* Tollhouse requires slot id to be displayed */
   4.731 +	bricktype = MODULE_GET_BTYPE(moduleid);
   4.732 +	if ((bricktype == L1_BRICKTYPE_191010) ||
   4.733 +	    (bricktype == L1_BRICKTYPE_1932))
   4.734 +			sprintf(address, "%s^%d", address, geo_slot(geoid));
   4.735 +}
   4.736 +
   4.737 +subsys_initcall(sn_pci_init);
   4.738 +EXPORT_SYMBOL(sn_pci_fixup_slot);
   4.739 +EXPORT_SYMBOL(sn_pci_unfixup_slot);
   4.740 +EXPORT_SYMBOL(sn_pci_controller_fixup);
   4.741 +EXPORT_SYMBOL(sn_bus_store_sysdata);
   4.742 +EXPORT_SYMBOL(sn_bus_free_sysdata);
   4.743 +EXPORT_SYMBOL(sn_generate_path);
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/iomv.c	Wed Dec 13 11:08:40 2006 -0700
     5.3 @@ -0,0 +1,76 @@
     5.4 +/* 
     5.5 + * This file is subject to the terms and conditions of the GNU General Public
     5.6 + * License.  See the file "COPYING" in the main directory of this archive
     5.7 + * for more details.
     5.8 + *
     5.9 + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved.
    5.10 + */
    5.11 +
    5.12 +#include <linux/module.h>
    5.13 +#include <asm/io.h>
    5.14 +#include <asm/delay.h>
    5.15 +#include <asm/vga.h>
    5.16 +#include <asm/sn/nodepda.h>
    5.17 +#include <asm/sn/simulator.h>
    5.18 +#include <asm/sn/pda.h>
    5.19 +#include <asm/sn/sn_cpuid.h>
    5.20 +#include <asm/sn/shub_mmr.h>
    5.21 +
    5.22 +#define IS_LEGACY_VGA_IOPORT(p) \
    5.23 +	(((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
    5.24 +
    5.25 +/**
    5.26 + * sn_io_addr - convert an in/out port to an i/o address
    5.27 + * @port: port to convert
    5.28 + *
    5.29 + * Legacy in/out instructions are converted to ld/st instructions
    5.30 + * on IA64.  This routine will convert a port number into a valid 
    5.31 + * SN i/o address.  Used by sn_in*() and sn_out*().
    5.32 + */
    5.33 +void *sn_io_addr(unsigned long port)
    5.34 +{
    5.35 +	if (!IS_RUNNING_ON_SIMULATOR()) {
    5.36 +		if (IS_LEGACY_VGA_IOPORT(port))
    5.37 +			port += vga_console_iobase;
    5.38 +		/* On sn2, legacy I/O ports don't point at anything */
    5.39 +		if (port < (64 * 1024))
    5.40 +			return NULL;
    5.41 +		return ((void *)(port | __IA64_UNCACHED_OFFSET));
    5.42 +	} else {
    5.43 +		/* but the simulator uses them... */
    5.44 +		unsigned long addr;
    5.45 +
    5.46 +		/*
    5.47 +		 * word align port, but need more than 10 bits
    5.48 +		 * for accessing registers in bedrock local block
    5.49 +		 * (so we don't do port&0xfff)
    5.50 +		 */
    5.51 +		addr = (is_shub2() ? 0xc00000028c000000UL : 0xc0000087cc000000UL) | ((port >> 2) << 12);
    5.52 +		if ((port >= 0x1f0 && port <= 0x1f7) || port == 0x3f6 || port == 0x3f7)
    5.53 +			addr |= port;
    5.54 +		return (void *)addr;
    5.55 +	}
    5.56 +}
    5.57 +
    5.58 +EXPORT_SYMBOL(sn_io_addr);
    5.59 +
    5.60 +/**
    5.61 + * __sn_mmiowb - I/O space memory barrier
    5.62 + *
    5.63 + * See include/asm-ia64/io.h and Documentation/DocBook/deviceiobook.tmpl
    5.64 + * for details.
    5.65 + *
    5.66 + * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
    5.67 + * See PV 871084 for details about the WAR about zero value.
    5.68 + *
    5.69 + */
    5.70 +void __sn_mmiowb(void)
    5.71 +{
    5.72 +	volatile unsigned long *adr = pda->pio_write_status_addr;
    5.73 +	unsigned long val = pda->pio_write_status_val;
    5.74 +
    5.75 +	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
    5.76 +		cpu_relax();
    5.77 +}
    5.78 +
    5.79 +EXPORT_SYMBOL(__sn_mmiowb);
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/irq.c	Wed Dec 13 11:08:40 2006 -0700
     6.3 @@ -0,0 +1,444 @@
     6.4 +/*
     6.5 + * Platform dependent support for SGI SN
     6.6 + *
     6.7 + * This file is subject to the terms and conditions of the GNU General Public
     6.8 + * License.  See the file "COPYING" in the main directory of this archive
     6.9 + * for more details.
    6.10 + *
    6.11 + * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
    6.12 + */
    6.13 +
    6.14 +#include <linux/irq.h>
    6.15 +#include <linux/spinlock.h>
    6.16 +#include <linux/init.h>
    6.17 +#include <asm/sn/addrs.h>
    6.18 +#include <asm/sn/arch.h>
    6.19 +#include <asm/sn/intr.h>
    6.20 +#include <asm/sn/pcibr_provider.h>
    6.21 +#include <asm/sn/pcibus_provider_defs.h>
    6.22 +#include <asm/sn/pcidev.h>
    6.23 +#include <asm/sn/shub_mmr.h>
    6.24 +#include <asm/sn/sn_sal.h>
    6.25 +
    6.26 +static void force_interrupt(int irq);
    6.27 +static void register_intr_pda(struct sn_irq_info *sn_irq_info);
    6.28 +static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
    6.29 +
    6.30 +int sn_force_interrupt_flag = 1;
    6.31 +extern int sn_ioif_inited;
    6.32 +struct list_head **sn_irq_lh;
    6.33 +static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
    6.34 +
    6.35 +u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
    6.36 +				     struct sn_irq_info *sn_irq_info,
    6.37 +				     int req_irq, nasid_t req_nasid,
    6.38 +				     int req_slice)
    6.39 +{
    6.40 +	struct ia64_sal_retval ret_stuff;
    6.41 +	ret_stuff.status = 0;
    6.42 +	ret_stuff.v0 = 0;
    6.43 +
    6.44 +	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
    6.45 +			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
    6.46 +			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
    6.47 +			(u64) req_nasid, (u64) req_slice);
    6.48 +
    6.49 +	return ret_stuff.status;
    6.50 +}
    6.51 +
    6.52 +void sn_intr_free(nasid_t local_nasid, int local_widget,
    6.53 +				struct sn_irq_info *sn_irq_info)
    6.54 +{
    6.55 +	struct ia64_sal_retval ret_stuff;
    6.56 +	ret_stuff.status = 0;
    6.57 +	ret_stuff.v0 = 0;
    6.58 +
    6.59 +	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
    6.60 +			(u64) SAL_INTR_FREE, (u64) local_nasid,
    6.61 +			(u64) local_widget, (u64) sn_irq_info->irq_irq,
    6.62 +			(u64) sn_irq_info->irq_cookie, 0, 0);
    6.63 +}
    6.64 +
    6.65 +static unsigned int sn_startup_irq(unsigned int irq)
    6.66 +{
    6.67 +	return 0;
    6.68 +}
    6.69 +
    6.70 +static void sn_shutdown_irq(unsigned int irq)
    6.71 +{
    6.72 +}
    6.73 +
    6.74 +static void sn_disable_irq(unsigned int irq)
    6.75 +{
    6.76 +}
    6.77 +
    6.78 +static void sn_enable_irq(unsigned int irq)
    6.79 +{
    6.80 +}
    6.81 +
    6.82 +static void sn_ack_irq(unsigned int irq)
    6.83 +{
    6.84 +	u64 event_occurred, mask;
    6.85 +
    6.86 +	irq = irq & 0xff;
    6.87 +	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
    6.88 +	mask = event_occurred & SH_ALL_INT_MASK;
    6.89 +	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
    6.90 +	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
    6.91 +
    6.92 +	move_native_irq(irq);
    6.93 +}
    6.94 +
    6.95 +static void sn_end_irq(unsigned int irq)
    6.96 +{
    6.97 +	int ivec;
    6.98 +	u64 event_occurred;
    6.99 +
   6.100 +	ivec = irq & 0xff;
   6.101 +	if (ivec == SGI_UART_VECTOR) {
   6.102 +		event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
   6.103 +		/* If the UART bit is set here, we may have received an
   6.104 +		 * interrupt from the UART that the driver missed.  To
   6.105 +		 * make sure, we IPI ourselves to force us to look again.
   6.106 +		 */
   6.107 +		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
   6.108 +			platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
   6.109 +					  IA64_IPI_DM_INT, 0);
   6.110 +		}
   6.111 +	}
   6.112 +	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
   6.113 +	if (sn_force_interrupt_flag)
   6.114 +		force_interrupt(irq);
   6.115 +}
   6.116 +
   6.117 +static void sn_irq_info_free(struct rcu_head *head);
   6.118 +
   6.119 +struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
   6.120 +				       nasid_t nasid, int slice)
   6.121 +{
   6.122 +	int vector;
   6.123 +	int cpuphys;
   6.124 +	int64_t bridge;
   6.125 +	int local_widget, status;
   6.126 +	nasid_t local_nasid;
   6.127 +	struct sn_irq_info *new_irq_info;
   6.128 +	struct sn_pcibus_provider *pci_provider;
   6.129 +
   6.130 +	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
   6.131 +	if (new_irq_info == NULL)
   6.132 +		return NULL;
   6.133 +
   6.134 +	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
   6.135 +
   6.136 +	bridge = (u64) new_irq_info->irq_bridge;
   6.137 +	if (!bridge) {
   6.138 +		kfree(new_irq_info);
   6.139 +		return NULL; /* irq is not a device interrupt */
   6.140 +	}
   6.141 +
   6.142 +	local_nasid = NASID_GET(bridge);
   6.143 +
   6.144 +	if (local_nasid & 1)
   6.145 +		local_widget = TIO_SWIN_WIDGETNUM(bridge);
   6.146 +	else
   6.147 +		local_widget = SWIN_WIDGETNUM(bridge);
   6.148 +
   6.149 +	vector = sn_irq_info->irq_irq;
   6.150 +	/* Free the old PROM new_irq_info structure */
   6.151 +	sn_intr_free(local_nasid, local_widget, new_irq_info);
   6.152 +	/* Update kernels new_irq_info with new target info */
   6.153 +	unregister_intr_pda(new_irq_info);
   6.154 +
   6.155 +	/* allocate a new PROM new_irq_info struct */
   6.156 +	status = sn_intr_alloc(local_nasid, local_widget,
   6.157 +			       new_irq_info, vector,
   6.158 +			       nasid, slice);
   6.159 +
   6.160 +	/* SAL call failed */
   6.161 +	if (status) {
   6.162 +		kfree(new_irq_info);
   6.163 +		return NULL;
   6.164 +	}
   6.165 +
   6.166 +	cpuphys = nasid_slice_to_cpuid(nasid, slice);
   6.167 +	new_irq_info->irq_cpuid = cpuphys;
   6.168 +	register_intr_pda(new_irq_info);
   6.169 +
   6.170 +	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
   6.171 +
   6.172 +	/*
   6.173 +	 * If this represents a line interrupt, target it.  If it's
   6.174 +	 * an msi (irq_int_bit < 0), it's already targeted.
   6.175 +	 */
   6.176 +	if (new_irq_info->irq_int_bit >= 0 &&
   6.177 +	    pci_provider && pci_provider->target_interrupt)
   6.178 +		(pci_provider->target_interrupt)(new_irq_info);
   6.179 +
   6.180 +	spin_lock(&sn_irq_info_lock);
   6.181 +	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
   6.182 +	spin_unlock(&sn_irq_info_lock);
   6.183 +	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
   6.184 +
   6.185 +#ifdef CONFIG_SMP
   6.186 +	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
   6.187 +#endif
   6.188 +
   6.189 +	return new_irq_info;
   6.190 +}
   6.191 +
   6.192 +static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
   6.193 +{
   6.194 +	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
   6.195 +	nasid_t nasid;
   6.196 +	int slice;
   6.197 +
   6.198 +	nasid = cpuid_to_nasid(first_cpu(mask));
   6.199 +	slice = cpuid_to_slice(first_cpu(mask));
   6.200 +
   6.201 +	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
   6.202 +				 sn_irq_lh[irq], list)
   6.203 +		(void)sn_retarget_vector(sn_irq_info, nasid, slice);
   6.204 +}
   6.205 +
   6.206 +struct hw_interrupt_type irq_type_sn = {
   6.207 +	.name		= "SN hub",
   6.208 +	.startup	= sn_startup_irq,
   6.209 +	.shutdown	= sn_shutdown_irq,
   6.210 +	.enable		= sn_enable_irq,
   6.211 +	.disable	= sn_disable_irq,
   6.212 +	.ack		= sn_ack_irq,
   6.213 +	.end		= sn_end_irq,
   6.214 +	.set_affinity	= sn_set_affinity_irq
   6.215 +};
   6.216 +
   6.217 +unsigned int sn_local_vector_to_irq(u8 vector)
   6.218 +{
   6.219 +	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
   6.220 +}
   6.221 +
   6.222 +void sn_irq_init(void)
   6.223 +{
   6.224 +	int i;
   6.225 +	irq_desc_t *base_desc = irq_desc;
   6.226 +
   6.227 +	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
   6.228 +	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
   6.229 +
   6.230 +	for (i = 0; i < NR_IRQS; i++) {
   6.231 +		if (base_desc[i].chip == &no_irq_type) {
   6.232 +			base_desc[i].chip = &irq_type_sn;
   6.233 +		}
   6.234 +	}
   6.235 +}
   6.236 +
   6.237 +static void register_intr_pda(struct sn_irq_info *sn_irq_info)
   6.238 +{
   6.239 +	int irq = sn_irq_info->irq_irq;
   6.240 +	int cpu = sn_irq_info->irq_cpuid;
   6.241 +
   6.242 +	if (pdacpu(cpu)->sn_last_irq < irq) {
   6.243 +		pdacpu(cpu)->sn_last_irq = irq;
   6.244 +	}
   6.245 +
   6.246 +	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
   6.247 +		pdacpu(cpu)->sn_first_irq = irq;
   6.248 +}
   6.249 +
   6.250 +static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
   6.251 +{
   6.252 +	int irq = sn_irq_info->irq_irq;
   6.253 +	int cpu = sn_irq_info->irq_cpuid;
   6.254 +	struct sn_irq_info *tmp_irq_info;
   6.255 +	int i, foundmatch;
   6.256 +
   6.257 +	rcu_read_lock();
   6.258 +	if (pdacpu(cpu)->sn_last_irq == irq) {
   6.259 +		foundmatch = 0;
   6.260 +		for (i = pdacpu(cpu)->sn_last_irq - 1;
   6.261 +		     i && !foundmatch; i--) {
   6.262 +			list_for_each_entry_rcu(tmp_irq_info,
   6.263 +						sn_irq_lh[i],
   6.264 +						list) {
   6.265 +				if (tmp_irq_info->irq_cpuid == cpu) {
   6.266 +					foundmatch = 1;
   6.267 +					break;
   6.268 +				}
   6.269 +			}
   6.270 +		}
   6.271 +		pdacpu(cpu)->sn_last_irq = i;
   6.272 +	}
   6.273 +
   6.274 +	if (pdacpu(cpu)->sn_first_irq == irq) {
   6.275 +		foundmatch = 0;
   6.276 +		for (i = pdacpu(cpu)->sn_first_irq + 1;
   6.277 +		     i < NR_IRQS && !foundmatch; i++) {
   6.278 +			list_for_each_entry_rcu(tmp_irq_info,
   6.279 +						sn_irq_lh[i],
   6.280 +						list) {
   6.281 +				if (tmp_irq_info->irq_cpuid == cpu) {
   6.282 +					foundmatch = 1;
   6.283 +					break;
   6.284 +				}
   6.285 +			}
   6.286 +		}
   6.287 +		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
   6.288 +	}
   6.289 +	rcu_read_unlock();
   6.290 +}
   6.291 +
   6.292 +static void sn_irq_info_free(struct rcu_head *head)
   6.293 +{
   6.294 +	struct sn_irq_info *sn_irq_info;
   6.295 +
   6.296 +	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
   6.297 +	kfree(sn_irq_info);
   6.298 +}
   6.299 +
   6.300 +void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
   6.301 +{
   6.302 +	nasid_t nasid = sn_irq_info->irq_nasid;
   6.303 +	int slice = sn_irq_info->irq_slice;
   6.304 +	int cpu = nasid_slice_to_cpuid(nasid, slice);
   6.305 +
   6.306 +	pci_dev_get(pci_dev);
   6.307 +	sn_irq_info->irq_cpuid = cpu;
   6.308 +	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
   6.309 +
   6.310 +	/* link it into the sn_irq[irq] list */
   6.311 +	spin_lock(&sn_irq_info_lock);
   6.312 +	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
   6.313 +	reserve_irq_vector(sn_irq_info->irq_irq);
   6.314 +	spin_unlock(&sn_irq_info_lock);
   6.315 +
   6.316 +	register_intr_pda(sn_irq_info);
   6.317 +}
   6.318 +
   6.319 +void sn_irq_unfixup(struct pci_dev *pci_dev)
   6.320 +{
   6.321 +	struct sn_irq_info *sn_irq_info;
   6.322 +
   6.323 +	/* Only cleanup IRQ stuff if this device has a host bus context */
   6.324 +	if (!SN_PCIDEV_BUSSOFT(pci_dev))
   6.325 +		return;
   6.326 +
   6.327 +	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
   6.328 +	if (!sn_irq_info)
   6.329 +		return;
   6.330 +	if (!sn_irq_info->irq_irq) {
   6.331 +		kfree(sn_irq_info);
   6.332 +		return;
   6.333 +	}
   6.334 +
   6.335 +	unregister_intr_pda(sn_irq_info);
   6.336 +	spin_lock(&sn_irq_info_lock);
   6.337 +	list_del_rcu(&sn_irq_info->list);
   6.338 +	spin_unlock(&sn_irq_info_lock);
   6.339 +	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
   6.340 +		free_irq_vector(sn_irq_info->irq_irq);
   6.341 +	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
   6.342 +	pci_dev_put(pci_dev);
   6.343 +
   6.344 +}
   6.345 +
   6.346 +static inline void
   6.347 +sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
   6.348 +{
   6.349 +	struct sn_pcibus_provider *pci_provider;
   6.350 +
   6.351 +	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
   6.352 +	if (pci_provider && pci_provider->force_interrupt)
   6.353 +		(*pci_provider->force_interrupt)(sn_irq_info);
   6.354 +}
   6.355 +
   6.356 +static void force_interrupt(int irq)
   6.357 +{
   6.358 +	struct sn_irq_info *sn_irq_info;
   6.359 +
   6.360 +	if (!sn_ioif_inited)
   6.361 +		return;
   6.362 +
   6.363 +	rcu_read_lock();
   6.364 +	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
   6.365 +		sn_call_force_intr_provider(sn_irq_info);
   6.366 +
   6.367 +	rcu_read_unlock();
   6.368 +}
   6.369 +
   6.370 +/*
   6.371 + * Check for lost interrupts.  If the PIC int_status reg. says that
   6.372 + * an interrupt has been sent, but not handled, and the interrupt
   6.373 + * is not pending in either the cpu irr regs or in the soft irr regs,
   6.374 + * and the interrupt is not in service, then the interrupt may have
   6.375 + * been lost.  Force an interrupt on that pin.  It is possible that
   6.376 + * the interrupt is in flight, so we may generate a spurious interrupt,
   6.377 + * but we should never miss a real lost interrupt.
   6.378 + */
   6.379 +static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
   6.380 +{
   6.381 +	u64 regval;
   6.382 +	struct pcidev_info *pcidev_info;
   6.383 +	struct pcibus_info *pcibus_info;
   6.384 +
   6.385 +	/*
   6.386 +	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
   6.387 +	 * since they do not target Shub II interrupt registers.  If that
   6.388 +	 * ever changes, this check needs to accomodate.
   6.389 +	 */
   6.390 +	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
   6.391 +		return;
   6.392 +
   6.393 +	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
   6.394 +	if (!pcidev_info)
   6.395 +		return;
   6.396 +
   6.397 +	pcibus_info =
   6.398 +	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
   6.399 +	    pdi_pcibus_info;
   6.400 +	regval = pcireg_intr_status_get(pcibus_info);
   6.401 +
   6.402 +	if (!ia64_get_irr(irq_to_vector(irq))) {
   6.403 +		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
   6.404 +			regval &= 0xff;
   6.405 +			if (sn_irq_info->irq_int_bit & regval &
   6.406 +			    sn_irq_info->irq_last_intr) {
   6.407 +				regval &= ~(sn_irq_info->irq_int_bit & regval);
   6.408 +				sn_call_force_intr_provider(sn_irq_info);
   6.409 +			}
   6.410 +		}
   6.411 +	}
   6.412 +	sn_irq_info->irq_last_intr = regval;
   6.413 +}
   6.414 +
   6.415 +void sn_lb_int_war_check(void)
   6.416 +{
   6.417 +	struct sn_irq_info *sn_irq_info;
   6.418 +	int i;
   6.419 +
   6.420 +	if (!sn_ioif_inited || pda->sn_first_irq == 0)
   6.421 +		return;
   6.422 +
   6.423 +	rcu_read_lock();
   6.424 +	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
   6.425 +		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
   6.426 +			sn_check_intr(i, sn_irq_info);
   6.427 +		}
   6.428 +	}
   6.429 +	rcu_read_unlock();
   6.430 +}
   6.431 +
   6.432 +void __init sn_irq_lh_init(void)
   6.433 +{
   6.434 +	int i;
   6.435 +
   6.436 +	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
   6.437 +	if (!sn_irq_lh)
   6.438 +		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
   6.439 +
   6.440 +	for (i = 0; i < NR_IRQS; i++) {
   6.441 +		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
   6.442 +		if (!sn_irq_lh[i])
   6.443 +			panic("SN PCI INIT: Failed IRQ memory allocation\n");
   6.444 +
   6.445 +		INIT_LIST_HEAD(sn_irq_lh[i]);
   6.446 +	}
   6.447 +}
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/setup.c	Wed Dec 13 11:08:40 2006 -0700
     7.3 @@ -0,0 +1,755 @@
     7.4 +/*
     7.5 + * This file is subject to the terms and conditions of the GNU General Public
     7.6 + * License.  See the file "COPYING" in the main directory of this archive
     7.7 + * for more details.
     7.8 + *
     7.9 + * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved.
    7.10 + */
    7.11 +
    7.12 +#include <linux/module.h>
    7.13 +#include <linux/init.h>
    7.14 +#include <linux/delay.h>
    7.15 +#include <linux/kernel.h>
    7.16 +#include <linux/kdev_t.h>
    7.17 +#include <linux/string.h>
    7.18 +#include <linux/screen_info.h>
    7.19 +#include <linux/console.h>
    7.20 +#include <linux/timex.h>
    7.21 +#include <linux/sched.h>
    7.22 +#include <linux/ioport.h>
    7.23 +#include <linux/mm.h>
    7.24 +#include <linux/serial.h>
    7.25 +#include <linux/irq.h>
    7.26 +#include <linux/bootmem.h>
    7.27 +#include <linux/mmzone.h>
    7.28 +#include <linux/interrupt.h>
    7.29 +#include <linux/acpi.h>
    7.30 +#include <linux/compiler.h>
    7.31 +#include <linux/sched.h>
    7.32 +#include <linux/root_dev.h>
    7.33 +#include <linux/nodemask.h>
    7.34 +#include <linux/pm.h>
    7.35 +#include <linux/efi.h>
    7.36 +
    7.37 +#include <asm/io.h>
    7.38 +#include <asm/sal.h>
    7.39 +#include <asm/machvec.h>
    7.40 +#include <asm/system.h>
    7.41 +#include <asm/processor.h>
    7.42 +#include <asm/vga.h>
    7.43 +#include <asm/sn/arch.h>
    7.44 +#include <asm/sn/addrs.h>
    7.45 +#include <asm/sn/pda.h>
    7.46 +#include <asm/sn/nodepda.h>
    7.47 +#include <asm/sn/sn_cpuid.h>
    7.48 +#include <asm/sn/simulator.h>
    7.49 +#include <asm/sn/leds.h>
    7.50 +#include <asm/sn/bte.h>
    7.51 +#include <asm/sn/shub_mmr.h>
    7.52 +#include <asm/sn/clksupport.h>
    7.53 +#include <asm/sn/sn_sal.h>
    7.54 +#include <asm/sn/geo.h>
    7.55 +#include <asm/sn/sn_feature_sets.h>
    7.56 +#include "xtalk/xwidgetdev.h"
    7.57 +#include "xtalk/hubdev.h"
    7.58 +#include <asm/sn/klconfig.h>
    7.59 +
    7.60 +
    7.61 +DEFINE_PER_CPU(struct pda_s, pda_percpu);
    7.62 +
    7.63 +#define MAX_PHYS_MEMORY		(1UL << IA64_MAX_PHYS_BITS)	/* Max physical address supported */
    7.64 +
    7.65 +extern void bte_init_node(nodepda_t *, cnodeid_t);
    7.66 +
    7.67 +extern void sn_timer_init(void);
    7.68 +extern unsigned long last_time_offset;
    7.69 +extern void (*ia64_mark_idle) (int);
    7.70 +extern void snidle(int);
    7.71 +extern unsigned long long (*ia64_printk_clock)(void);
    7.72 +
    7.73 +unsigned long sn_rtc_cycles_per_second;
    7.74 +EXPORT_SYMBOL(sn_rtc_cycles_per_second);
    7.75 +
    7.76 +DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
    7.77 +EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
    7.78 +
    7.79 +DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
    7.80 +EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
    7.81 +
    7.82 +DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
    7.83 +EXPORT_PER_CPU_SYMBOL(__sn_nodepda);
    7.84 +
    7.85 +char sn_system_serial_number_string[128];
    7.86 +EXPORT_SYMBOL(sn_system_serial_number_string);
    7.87 +u64 sn_partition_serial_number;
    7.88 +EXPORT_SYMBOL(sn_partition_serial_number);
    7.89 +u8 sn_partition_id;
    7.90 +EXPORT_SYMBOL(sn_partition_id);
    7.91 +u8 sn_system_size;
    7.92 +EXPORT_SYMBOL(sn_system_size);
    7.93 +u8 sn_sharing_domain_size;
    7.94 +EXPORT_SYMBOL(sn_sharing_domain_size);
    7.95 +u8 sn_coherency_id;
    7.96 +EXPORT_SYMBOL(sn_coherency_id);
    7.97 +u8 sn_region_size;
    7.98 +EXPORT_SYMBOL(sn_region_size);
    7.99 +int sn_prom_type;	/* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
   7.100 +
   7.101 +short physical_node_map[MAX_NUMALINK_NODES];
   7.102 +static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS];
   7.103 +
   7.104 +EXPORT_SYMBOL(physical_node_map);
   7.105 +
   7.106 +int num_cnodes;
   7.107 +
   7.108 +static void sn_init_pdas(char **);
   7.109 +static void build_cnode_tables(void);
   7.110 +
   7.111 +static nodepda_t *nodepdaindr[MAX_COMPACT_NODES];
   7.112 +
   7.113 +/*
   7.114 + * The format of "screen_info" is strange, and due to early i386-setup
   7.115 + * code. This is just enough to make the console code think we're on a
   7.116 + * VGA color display.
   7.117 + */
   7.118 +struct screen_info sn_screen_info = {
   7.119 +	.orig_x = 0,
   7.120 +	.orig_y = 0,
   7.121 +	.orig_video_mode = 3,
   7.122 +	.orig_video_cols = 80,
   7.123 +	.orig_video_ega_bx = 3,
   7.124 +	.orig_video_lines = 25,
   7.125 +	.orig_video_isVGA = 1,
   7.126 +	.orig_video_points = 16
   7.127 +};
   7.128 +
   7.129 +/*
   7.130 + * This routine can only be used during init, since
   7.131 + * smp_boot_data is an init data structure.
   7.132 + * We have to use smp_boot_data.cpu_phys_id to find
   7.133 + * the physical id of the processor because the normal
   7.134 + * cpu_physical_id() relies on data structures that
   7.135 + * may not be initialized yet.
   7.136 + */
   7.137 +
   7.138 +static int __init pxm_to_nasid(int pxm)
   7.139 +{
   7.140 +	int i;
   7.141 +	int nid;
   7.142 +
   7.143 +	nid = pxm_to_node(pxm);
   7.144 +	for (i = 0; i < num_node_memblks; i++) {
   7.145 +		if (node_memblk[i].nid == nid) {
   7.146 +			return NASID_GET(node_memblk[i].start_paddr);
   7.147 +		}
   7.148 +	}
   7.149 +	return -1;
   7.150 +}
   7.151 +
   7.152 +/**
   7.153 + * early_sn_setup - early setup routine for SN platforms
   7.154 + *
   7.155 + * Sets up an initial console to aid debugging.  Intended primarily
   7.156 + * for bringup.  See start_kernel() in init/main.c.
   7.157 + */
   7.158 +
   7.159 +void __init early_sn_setup(void)
   7.160 +{
   7.161 +	efi_system_table_t *efi_systab;
   7.162 +	efi_config_table_t *config_tables;
   7.163 +	struct ia64_sal_systab *sal_systab;
   7.164 +	struct ia64_sal_desc_entry_point *ep;
   7.165 +	char *p;
   7.166 +	int i, j;
   7.167 +
   7.168 +	/*
   7.169 +	 * Parse enough of the SAL tables to locate the SAL entry point. Since, console
   7.170 +	 * IO on SN2 is done via SAL calls, early_printk won't work without this.
   7.171 +	 *
   7.172 +	 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c.
   7.173 +	 * Any changes to those file may have to be made hereas well.
   7.174 +	 */
   7.175 +	efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab);
   7.176 +	config_tables = __va(efi_systab->tables);
   7.177 +	for (i = 0; i < efi_systab->nr_tables; i++) {
   7.178 +		if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) ==
   7.179 +		    0) {
   7.180 +			sal_systab = __va(config_tables[i].table);
   7.181 +			p = (char *)(sal_systab + 1);
   7.182 +			for (j = 0; j < sal_systab->entry_count; j++) {
   7.183 +				if (*p == SAL_DESC_ENTRY_POINT) {
   7.184 +					ep = (struct ia64_sal_desc_entry_point
   7.185 +					      *)p;
   7.186 +					ia64_sal_handler_init(__va
   7.187 +							      (ep->sal_proc),
   7.188 +							      __va(ep->gp));
   7.189 +					return;
   7.190 +				}
   7.191 +				p += SAL_DESC_SIZE(*p);
   7.192 +			}
   7.193 +		}
   7.194 +	}
   7.195 +	/* Uh-oh, SAL not available?? */
   7.196 +	printk(KERN_ERR "failed to find SAL entry point\n");
   7.197 +}
   7.198 +
   7.199 +extern int platform_intr_list[];
   7.200 +static int __initdata shub_1_1_found;
   7.201 +
   7.202 +/*
   7.203 + * sn_check_for_wars
   7.204 + *
   7.205 + * Set flag for enabling shub specific wars
   7.206 + */
   7.207 +
   7.208 +static inline int __init is_shub_1_1(int nasid)
   7.209 +{
   7.210 +	unsigned long id;
   7.211 +	int rev;
   7.212 +
   7.213 +	if (is_shub2())
   7.214 +		return 0;
   7.215 +	id = REMOTE_HUB_L(nasid, SH1_SHUB_ID);
   7.216 +	rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT;
   7.217 +	return rev <= 2;
   7.218 +}
   7.219 +
   7.220 +static void __init sn_check_for_wars(void)
   7.221 +{
   7.222 +	int cnode;
   7.223 +
   7.224 +	if (is_shub2()) {
   7.225 +		/* none yet */
   7.226 +	} else {
   7.227 +		for_each_online_node(cnode) {
   7.228 +			if (is_shub_1_1(cnodeid_to_nasid(cnode)))
   7.229 +				shub_1_1_found = 1;
   7.230 +		}
   7.231 +	}
   7.232 +}
   7.233 +
   7.234 +/*
   7.235 + * Scan the EFI PCDP table (if it exists) for an acceptable VGA console
   7.236 + * output device.  If one exists, pick it and set sn_legacy_{io,mem} to
   7.237 + * reflect the bus offsets needed to address it.
   7.238 + *
   7.239 + * Since pcdp support in SN is not supported in the 2.4 kernel (or at least
   7.240 + * the one lbs is based on) just declare the needed structs here.
   7.241 + *
   7.242 + * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf
   7.243 + *
   7.244 + * Returns 0 if no acceptable vga is found, !0 otherwise.
   7.245 + *
   7.246 + * Note:  This stuff is duped here because Altix requires the PCDP to
   7.247 + * locate a usable VGA device due to lack of proper ACPI support.  Structures
   7.248 + * could be used from drivers/firmware/pcdp.h, but it was decided that moving
   7.249 + * this file to a more public location just for Altix use was undesireable.
   7.250 + */
   7.251 +
   7.252 +struct hcdp_uart_desc {
   7.253 +	u8	pad[45];
   7.254 +};
   7.255 +
   7.256 +struct pcdp {
   7.257 +	u8	signature[4];	/* should be 'HCDP' */
   7.258 +	u32	length;
   7.259 +	u8	rev;		/* should be >=3 for pcdp, <3 for hcdp */
   7.260 +	u8	sum;
   7.261 +	u8	oem_id[6];
   7.262 +	u64	oem_tableid;
   7.263 +	u32	oem_rev;
   7.264 +	u32	creator_id;
   7.265 +	u32	creator_rev;
   7.266 +	u32	num_type0;
   7.267 +	struct hcdp_uart_desc uart[0];	/* num_type0 of these */
   7.268 +	/* pcdp descriptors follow */
   7.269 +}  __attribute__((packed));
   7.270 +
   7.271 +struct pcdp_device_desc {
   7.272 +	u8	type;
   7.273 +	u8	primary;
   7.274 +	u16	length;
   7.275 +	u16	index;
   7.276 +	/* interconnect specific structure follows */
   7.277 +	/* device specific structure follows that */
   7.278 +}  __attribute__((packed));
   7.279 +
   7.280 +struct pcdp_interface_pci {
   7.281 +	u8	type;		/* 1 == pci */
   7.282 +	u8	reserved;
   7.283 +	u16	length;
   7.284 +	u8	segment;
   7.285 +	u8	bus;
   7.286 +	u8 	dev;
   7.287 +	u8	fun;
   7.288 +	u16	devid;
   7.289 +	u16	vendid;
   7.290 +	u32	acpi_interrupt;
   7.291 +	u64	mmio_tra;
   7.292 +	u64	ioport_tra;
   7.293 +	u8	flags;
   7.294 +	u8	translation;
   7.295 +}  __attribute__((packed));
   7.296 +
   7.297 +struct pcdp_vga_device {
   7.298 +	u8	num_eas_desc;
   7.299 +	/* ACPI Extended Address Space Desc follows */
   7.300 +}  __attribute__((packed));
   7.301 +
   7.302 +/* from pcdp_device_desc.primary */
   7.303 +#define PCDP_PRIMARY_CONSOLE	0x01
   7.304 +
   7.305 +/* from pcdp_device_desc.type */
   7.306 +#define PCDP_CONSOLE_INOUT	0x0
   7.307 +#define PCDP_CONSOLE_DEBUG	0x1
   7.308 +#define PCDP_CONSOLE_OUT	0x2
   7.309 +#define PCDP_CONSOLE_IN		0x3
   7.310 +#define PCDP_CONSOLE_TYPE_VGA	0x8
   7.311 +
   7.312 +#define PCDP_CONSOLE_VGA	(PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT)
   7.313 +
   7.314 +/* from pcdp_interface_pci.type */
   7.315 +#define PCDP_IF_PCI		1
   7.316 +
   7.317 +/* from pcdp_interface_pci.translation */
   7.318 +#define PCDP_PCI_TRANS_IOPORT	0x02
   7.319 +#define PCDP_PCI_TRANS_MMIO	0x01
   7.320 +
   7.321 +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
   7.322 +static void
   7.323 +sn_scan_pcdp(void)
   7.324 +{
   7.325 +	u8 *bp;
   7.326 +	struct pcdp *pcdp;
   7.327 +	struct pcdp_device_desc device;
   7.328 +	struct pcdp_interface_pci if_pci;
   7.329 +	extern struct efi efi;
   7.330 +
   7.331 +	if (efi.hcdp == EFI_INVALID_TABLE_ADDR)
   7.332 +		return;		/* no hcdp/pcdp table */
   7.333 +
   7.334 +	pcdp = __va(efi.hcdp);
   7.335 +
   7.336 +	if (pcdp->rev < 3)
   7.337 +		return;		/* only support PCDP (rev >= 3) */
   7.338 +
   7.339 +	for (bp = (u8 *)&pcdp->uart[pcdp->num_type0];
   7.340 +	     bp < (u8 *)pcdp + pcdp->length;
   7.341 +	     bp += device.length) {
   7.342 +		memcpy(&device, bp, sizeof(device));
   7.343 +		if (! (device.primary & PCDP_PRIMARY_CONSOLE))
   7.344 +			continue;	/* not primary console */
   7.345 +
   7.346 +		if (device.type != PCDP_CONSOLE_VGA)
   7.347 +			continue;	/* not VGA descriptor */
   7.348 +
   7.349 +		memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci));
   7.350 +		if (if_pci.type != PCDP_IF_PCI)
   7.351 +			continue;	/* not PCI interconnect */
   7.352 +
   7.353 +		if (if_pci.translation & PCDP_PCI_TRANS_IOPORT)
   7.354 +			vga_console_iobase =
   7.355 +				if_pci.ioport_tra | __IA64_UNCACHED_OFFSET;
   7.356 +
   7.357 +		if (if_pci.translation & PCDP_PCI_TRANS_MMIO)
   7.358 +			vga_console_membase =
   7.359 +				if_pci.mmio_tra | __IA64_UNCACHED_OFFSET;
   7.360 +
   7.361 +		break; /* once we find the primary, we're done */
   7.362 +	}
   7.363 +}
   7.364 +#endif
   7.365 +
   7.366 +static unsigned long sn2_rtc_initial;
   7.367 +
   7.368 +static unsigned long long ia64_sn2_printk_clock(void)
   7.369 +{
   7.370 +	unsigned long rtc_now = rtc_time();
   7.371 +
   7.372 +	return (rtc_now - sn2_rtc_initial) *
   7.373 +		(1000000000 / sn_rtc_cycles_per_second);
   7.374 +}
   7.375 +
   7.376 +/**
   7.377 + * sn_setup - SN platform setup routine
   7.378 + * @cmdline_p: kernel command line
   7.379 + *
   7.380 + * Handles platform setup for SN machines.  This includes determining
   7.381 + * the RTC frequency (via a SAL call), initializing secondary CPUs, and
   7.382 + * setting up per-node data areas.  The console is also initialized here.
   7.383 + */
   7.384 +void __init sn_setup(char **cmdline_p)
   7.385 +{
   7.386 +	long status, ticks_per_sec, drift;
   7.387 +	u32 version = sn_sal_rev();
   7.388 +	extern void sn_cpu_init(void);
   7.389 +
   7.390 +	sn2_rtc_initial = rtc_time();
   7.391 +	ia64_sn_plat_set_error_handling_features();	// obsolete
   7.392 +	ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV);
   7.393 +	ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES);
   7.394 +
   7.395 +
   7.396 +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
   7.397 +	/*
   7.398 +	 * Handle SN vga console.
   7.399 +	 *
   7.400 +	 * SN systems do not have enough ACPI table information
   7.401 +	 * being passed from prom to identify VGA adapters and the legacy
   7.402 +	 * addresses to access them.  Until that is done, SN systems rely
   7.403 +	 * on the PCDP table to identify the primary VGA console if one
   7.404 +	 * exists.
   7.405 +	 *
   7.406 +	 * However, kernel PCDP support is optional, and even if it is built
   7.407 +	 * into the kernel, it will not be used if the boot cmdline contains
   7.408 +	 * console= directives.
   7.409 +	 *
   7.410 +	 * So, to work around this mess, we duplicate some of the PCDP code
   7.411 +	 * here so that the primary VGA console (as defined by PCDP) will
   7.412 +	 * work on SN systems even if a different console (e.g. serial) is
   7.413 +	 * selected on the boot line (or CONFIG_EFI_PCDP is off).
   7.414 +	 */
   7.415 +
   7.416 +	if (! vga_console_membase)
   7.417 +		sn_scan_pcdp();
   7.418 +
   7.419 +	if (vga_console_membase) {
   7.420 +		/* usable vga ... make tty0 the preferred default console */
   7.421 +		if (!strstr(*cmdline_p, "console="))
   7.422 +			add_preferred_console("tty", 0, NULL);
   7.423 +	} else {
   7.424 +		printk(KERN_DEBUG "SGI: Disabling VGA console\n");
   7.425 +		if (!strstr(*cmdline_p, "console="))
   7.426 +			add_preferred_console("ttySG", 0, NULL);
   7.427 +#ifdef CONFIG_DUMMY_CONSOLE
   7.428 +		conswitchp = &dummy_con;
   7.429 +#else
   7.430 +		conswitchp = NULL;
   7.431 +#endif				/* CONFIG_DUMMY_CONSOLE */
   7.432 +	}
   7.433 +#endif				/* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */
   7.434 +
   7.435 +	MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
   7.436 +
   7.437 +	/*
   7.438 +	 * Build the tables for managing cnodes.
   7.439 +	 */
   7.440 +	build_cnode_tables();
   7.441 +
   7.442 +	status =
   7.443 +	    ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
   7.444 +			       &drift);
   7.445 +	if (status != 0 || ticks_per_sec < 100000) {
   7.446 +		printk(KERN_WARNING
   7.447 +		       "unable to determine platform RTC clock frequency, guessing.\n");
   7.448 +		/* PROM gives wrong value for clock freq. so guess */
   7.449 +		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
   7.450 +	} else
   7.451 +		sn_rtc_cycles_per_second = ticks_per_sec;
   7.452 +
   7.453 +	platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR;
   7.454 +
   7.455 +	ia64_printk_clock = ia64_sn2_printk_clock;
   7.456 +
   7.457 +	printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF);
   7.458 +
   7.459 +	/*
   7.460 +	 * we set the default root device to /dev/hda
   7.461 +	 * to make simulation easy
   7.462 +	 */
   7.463 +	ROOT_DEV = Root_HDA1;
   7.464 +
   7.465 +	/*
   7.466 +	 * Create the PDAs and NODEPDAs for all the cpus.
   7.467 +	 */
   7.468 +	sn_init_pdas(cmdline_p);
   7.469 +
   7.470 +	ia64_mark_idle = &snidle;
   7.471 +
   7.472 +	/*
   7.473 +	 * For the bootcpu, we do this here. All other cpus will make the
   7.474 +	 * call as part of cpu_init in slave cpu initialization.
   7.475 +	 */
   7.476 +	sn_cpu_init();
   7.477 +
   7.478 +#ifdef CONFIG_SMP
   7.479 +	init_smp_config();
   7.480 +#endif
   7.481 +	screen_info = sn_screen_info;
   7.482 +
   7.483 +	sn_timer_init();
   7.484 +
   7.485 +	/*
   7.486 +	 * set pm_power_off to a SAL call to allow
   7.487 +	 * sn machines to power off. The SAL call can be replaced
   7.488 +	 * by an ACPI interface call when ACPI is fully implemented
   7.489 +	 * for sn.
   7.490 +	 */
   7.491 +	pm_power_off = ia64_sn_power_down;
   7.492 +	current->thread.flags |= IA64_THREAD_MIGRATION;
   7.493 +}
   7.494 +
   7.495 +/**
   7.496 + * sn_init_pdas - setup node data areas
   7.497 + *
   7.498 + * One time setup for Node Data Area.  Called by sn_setup().
   7.499 + */
   7.500 +static void __init sn_init_pdas(char **cmdline_p)
   7.501 +{
   7.502 +	cnodeid_t cnode;
   7.503 +
   7.504 +	/*
   7.505 +	 * Allocate & initalize the nodepda for each node.
   7.506 +	 */
   7.507 +	for_each_online_node(cnode) {
   7.508 +		nodepdaindr[cnode] =
   7.509 +		    alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
   7.510 +		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
   7.511 +		memset(nodepdaindr[cnode]->phys_cpuid, -1,
   7.512 +		    sizeof(nodepdaindr[cnode]->phys_cpuid));
   7.513 +		spin_lock_init(&nodepdaindr[cnode]->ptc_lock);
   7.514 +	}
   7.515 +
   7.516 +	/*
   7.517 +	 * Allocate & initialize nodepda for TIOs.  For now, put them on node 0.
   7.518 +	 */
   7.519 +	for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) {
   7.520 +		nodepdaindr[cnode] =
   7.521 +		    alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t));
   7.522 +		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
   7.523 +	}
   7.524 +
   7.525 +	/*
   7.526 +	 * Now copy the array of nodepda pointers to each nodepda.
   7.527 +	 */
   7.528 +	for (cnode = 0; cnode < num_cnodes; cnode++)
   7.529 +		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr,
   7.530 +		       sizeof(nodepdaindr));
   7.531 +
   7.532 +	/*
   7.533 +	 * Set up IO related platform-dependent nodepda fields.
   7.534 +	 * The following routine actually sets up the hubinfo struct
   7.535 +	 * in nodepda.
   7.536 +	 */
   7.537 +	for_each_online_node(cnode) {
   7.538 +		bte_init_node(nodepdaindr[cnode], cnode);
   7.539 +	}
   7.540 +
   7.541 +	/*
   7.542 +	 * Initialize the per node hubdev.  This includes IO Nodes and
   7.543 +	 * headless/memless nodes.
   7.544 +	 */
   7.545 +	for (cnode = 0; cnode < num_cnodes; cnode++) {
   7.546 +		hubdev_init_node(nodepdaindr[cnode], cnode);
   7.547 +	}
   7.548 +}
   7.549 +
   7.550 +/**
   7.551 + * sn_cpu_init - initialize per-cpu data areas
   7.552 + * @cpuid: cpuid of the caller
   7.553 + *
   7.554 + * Called during cpu initialization on each cpu as it starts.
   7.555 + * Currently, initializes the per-cpu data area for SNIA.
   7.556 + * Also sets up a few fields in the nodepda.  Also known as
   7.557 + * platform_cpu_init() by the ia64 machvec code.
   7.558 + */
   7.559 +void __cpuinit sn_cpu_init(void)
   7.560 +{
   7.561 +	int cpuid;
   7.562 +	int cpuphyid;
   7.563 +	int nasid;
   7.564 +	int subnode;
   7.565 +	int slice;
   7.566 +	int cnode;
   7.567 +	int i;
   7.568 +	static int wars_have_been_checked;
   7.569 +
   7.570 +	cpuid = smp_processor_id();
   7.571 +	if (cpuid == 0 && IS_MEDUSA()) {
   7.572 +		if (ia64_sn_is_fake_prom())
   7.573 +			sn_prom_type = 2;
   7.574 +		else
   7.575 +			sn_prom_type = 1;
   7.576 +		printk(KERN_INFO "Running on medusa with %s PROM\n",
   7.577 +		       (sn_prom_type == 1) ? "real" : "fake");
   7.578 +	}
   7.579 +
   7.580 +	memset(pda, 0, sizeof(pda));
   7.581 +	if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2,
   7.582 +				&sn_hub_info->nasid_bitmask,
   7.583 +				&sn_hub_info->nasid_shift,
   7.584 +				&sn_system_size, &sn_sharing_domain_size,
   7.585 +				&sn_partition_id, &sn_coherency_id,
   7.586 +				&sn_region_size))
   7.587 +		BUG();
   7.588 +	sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2;
   7.589 +
   7.590 +	/*
   7.591 +	 * Don't check status. The SAL call is not supported on all PROMs
   7.592 +	 * but a failure is harmless.
   7.593 +	 */
   7.594 +	(void) ia64_sn_set_cpu_number(cpuid);
   7.595 +
   7.596 +	/*
   7.597 +	 * The boot cpu makes this call again after platform initialization is
   7.598 +	 * complete.
   7.599 +	 */
   7.600 +	if (nodepdaindr[0] == NULL)
   7.601 +		return;
   7.602 +
   7.603 +	for (i = 0; i < MAX_PROM_FEATURE_SETS; i++)
   7.604 +		if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0)
   7.605 +			break;
   7.606 +
   7.607 +	cpuphyid = get_sapicid();
   7.608 +
   7.609 +	if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice))
   7.610 +		BUG();
   7.611 +
   7.612 +	for (i=0; i < MAX_NUMNODES; i++) {
   7.613 +		if (nodepdaindr[i]) {
   7.614 +			nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid;
   7.615 +			nodepdaindr[i]->phys_cpuid[cpuid].slice = slice;
   7.616 +			nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode;
   7.617 +		}
   7.618 +	}
   7.619 +
   7.620 +	cnode = nasid_to_cnodeid(nasid);
   7.621 +
   7.622 +	sn_nodepda = nodepdaindr[cnode];
   7.623 +
   7.624 +	pda->led_address =
   7.625 +	    (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT));
   7.626 +	pda->led_state = LED_ALWAYS_SET;
   7.627 +	pda->hb_count = HZ / 2;
   7.628 +	pda->hb_state = 0;
   7.629 +	pda->idle_flag = 0;
   7.630 +
   7.631 +	if (cpuid != 0) {
   7.632 +		/* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */
   7.633 +		memcpy(sn_cnodeid_to_nasid,
   7.634 +		       (&per_cpu(__sn_cnodeid_to_nasid, 0)),
   7.635 +		       sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
   7.636 +	}
   7.637 +
   7.638 +	/*
   7.639 +	 * Check for WARs.
   7.640 +	 * Only needs to be done once, on BSP.
   7.641 +	 * Has to be done after loop above, because it uses this cpu's
   7.642 +	 * sn_cnodeid_to_nasid table which was just initialized if this
   7.643 +	 * isn't cpu 0.
   7.644 +	 * Has to be done before assignment below.
   7.645 +	 */
   7.646 +	if (!wars_have_been_checked) {
   7.647 +		sn_check_for_wars();
   7.648 +		wars_have_been_checked = 1;
   7.649 +	}
   7.650 +	sn_hub_info->shub_1_1_found = shub_1_1_found;
   7.651 +
   7.652 +	/*
   7.653 +	 * Set up addresses of PIO/MEM write status registers.
   7.654 +	 */
   7.655 +	{
   7.656 +		u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
   7.657 +		u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2,
   7.658 +			SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
   7.659 +		u64 *pio;
   7.660 +		pio = is_shub1() ? pio1 : pio2;
   7.661 +		pda->pio_write_status_addr =
   7.662 +		   (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]);
   7.663 +		pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
   7.664 +	}
   7.665 +
   7.666 +	/*
   7.667 +	 * WAR addresses for SHUB 1.x.
   7.668 +	 */
   7.669 +	if (local_node_data->active_cpu_count++ == 0 && is_shub1()) {
   7.670 +		int buddy_nasid;
   7.671 +		buddy_nasid =
   7.672 +		    cnodeid_to_nasid(numa_node_id() ==
   7.673 +				     num_online_nodes() - 1 ? 0 : numa_node_id() + 1);
   7.674 +		pda->pio_shub_war_cam_addr =
   7.675 +		    (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid,
   7.676 +							      SH1_PI_CAM_CONTROL);
   7.677 +	}
   7.678 +}
   7.679 +
   7.680 +/*
   7.681 + * Build tables for converting between NASIDs and cnodes.
   7.682 + */
   7.683 +static inline int __init board_needs_cnode(int type)
   7.684 +{
   7.685 +	return (type == KLTYPE_SNIA || type == KLTYPE_TIO);
   7.686 +}
   7.687 +
   7.688 +void __init build_cnode_tables(void)
   7.689 +{
   7.690 +	int nasid;
   7.691 +	int node;
   7.692 +	lboard_t *brd;
   7.693 +
   7.694 +	memset(physical_node_map, -1, sizeof(physical_node_map));
   7.695 +	memset(sn_cnodeid_to_nasid, -1,
   7.696 +			sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
   7.697 +
   7.698 +	/*
   7.699 +	 * First populate the tables with C/M bricks. This ensures that
   7.700 +	 * cnode == node for all C & M bricks.
   7.701 +	 */
   7.702 +	for_each_online_node(node) {
   7.703 +		nasid = pxm_to_nasid(node_to_pxm(node));
   7.704 +		sn_cnodeid_to_nasid[node] = nasid;
   7.705 +		physical_node_map[nasid] = node;
   7.706 +	}
   7.707 +
   7.708 +	/*
   7.709 +	 * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node
   7.710 +	 * limit on the number of nodes, we can't use the generic node numbers 
   7.711 +	 * for this. Note that num_cnodes is incremented below as TIOs or
   7.712 +	 * headless/memoryless nodes are discovered.
   7.713 +	 */
   7.714 +	num_cnodes = num_online_nodes();
   7.715 +
   7.716 +	/* fakeprom does not support klgraph */
   7.717 +	if (IS_RUNNING_ON_FAKE_PROM())
   7.718 +		return;
   7.719 +
   7.720 +	/* Find TIOs & headless/memoryless nodes and add them to the tables */
   7.721 +	for_each_online_node(node) {
   7.722 +		kl_config_hdr_t *klgraph_header;
   7.723 +		nasid = cnodeid_to_nasid(node);
   7.724 +		klgraph_header = ia64_sn_get_klconfig_addr(nasid);
   7.725 +		if (klgraph_header == NULL)
   7.726 +			BUG();
   7.727 +		brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info);
   7.728 +		while (brd) {
   7.729 +			if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) {
   7.730 +				sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid;
   7.731 +				physical_node_map[brd->brd_nasid] = num_cnodes++;
   7.732 +			}
   7.733 +			brd = find_lboard_next(brd);
   7.734 +		}
   7.735 +	}
   7.736 +}
   7.737 +
   7.738 +int
   7.739 +nasid_slice_to_cpuid(int nasid, int slice)
   7.740 +{
   7.741 +	long cpu;
   7.742 +
   7.743 +	for (cpu = 0; cpu < NR_CPUS; cpu++)
   7.744 +		if (cpuid_to_nasid(cpu) == nasid &&
   7.745 +					cpuid_to_slice(cpu) == slice)
   7.746 +			return cpu;
   7.747 +
   7.748 +	return -1;
   7.749 +}
   7.750 +
   7.751 +int sn_prom_feature_available(int id)
   7.752 +{
   7.753 +	if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS)
   7.754 +		return 0;
   7.755 +	return test_bit(id, sn_prom_features);
   7.756 +}
   7.757 +EXPORT_SYMBOL(sn_prom_feature_available);
   7.758 +
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/sn2_smp.c	Wed Dec 13 11:08:40 2006 -0700
     8.3 @@ -0,0 +1,489 @@
     8.4 +/*
     8.5 + * SN2 Platform specific SMP Support
     8.6 + *
     8.7 + * This file is subject to the terms and conditions of the GNU General Public
     8.8 + * License.  See the file "COPYING" in the main directory of this archive
     8.9 + * for more details.
    8.10 + *
    8.11 + * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
    8.12 + */
    8.13 +
    8.14 +#include <linux/init.h>
    8.15 +#include <linux/kernel.h>
    8.16 +#include <linux/spinlock.h>
    8.17 +#include <linux/threads.h>
    8.18 +#include <linux/sched.h>
    8.19 +#include <linux/smp.h>
    8.20 +#include <linux/interrupt.h>
    8.21 +#include <linux/irq.h>
    8.22 +#include <linux/mmzone.h>
    8.23 +#include <linux/module.h>
    8.24 +#include <linux/bitops.h>
    8.25 +#include <linux/nodemask.h>
    8.26 +#include <linux/proc_fs.h>
    8.27 +#include <linux/seq_file.h>
    8.28 +
    8.29 +#include <asm/processor.h>
    8.30 +#include <asm/irq.h>
    8.31 +#include <asm/sal.h>
    8.32 +#include <asm/system.h>
    8.33 +#include <asm/delay.h>
    8.34 +#include <asm/io.h>
    8.35 +#include <asm/smp.h>
    8.36 +#include <asm/tlb.h>
    8.37 +#include <asm/numa.h>
    8.38 +#include <asm/hw_irq.h>
    8.39 +#include <asm/current.h>
    8.40 +#include <asm/sn/sn_cpuid.h>
    8.41 +#include <asm/sn/sn_sal.h>
    8.42 +#include <asm/sn/addrs.h>
    8.43 +#include <asm/sn/shub_mmr.h>
    8.44 +#include <asm/sn/nodepda.h>
    8.45 +#include <asm/sn/rw_mmr.h>
    8.46 +
    8.47 +DEFINE_PER_CPU(struct ptc_stats, ptcstats);
    8.48 +DECLARE_PER_CPU(struct ptc_stats, ptcstats);
    8.49 +
    8.50 +static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
    8.51 +
    8.52 +extern unsigned long
    8.53 +sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
    8.54 +			       volatile unsigned long *, unsigned long,
    8.55 +			       volatile unsigned long *, unsigned long);
    8.56 +void
    8.57 +sn2_ptc_deadlock_recovery(short *, short, short, int,
    8.58 +			  volatile unsigned long *, unsigned long,
    8.59 +			  volatile unsigned long *, unsigned long);
    8.60 +
    8.61 +/*
    8.62 + * Note: some is the following is captured here to make degugging easier
    8.63 + * (the macros make more sense if you see the debug patch - not posted)
    8.64 + */
    8.65 +#define sn2_ptctest	0
    8.66 +#define local_node_uses_ptc_ga(sh1)	((sh1) ? 1 : 0)
    8.67 +#define max_active_pio(sh1)		((sh1) ? 32 : 7)
    8.68 +#define reset_max_active_on_deadlock()	1
    8.69 +#define PTC_LOCK(sh1)			((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
    8.70 +
    8.71 +struct ptc_stats {
    8.72 +	unsigned long ptc_l;
    8.73 +	unsigned long change_rid;
    8.74 +	unsigned long shub_ptc_flushes;
    8.75 +	unsigned long nodes_flushed;
    8.76 +	unsigned long deadlocks;
    8.77 +	unsigned long deadlocks2;
    8.78 +	unsigned long lock_itc_clocks;
    8.79 +	unsigned long shub_itc_clocks;
    8.80 +	unsigned long shub_itc_clocks_max;
    8.81 +	unsigned long shub_ptc_flushes_not_my_mm;
    8.82 +};
    8.83 +
    8.84 +#define sn2_ptctest	0
    8.85 +
    8.86 +static inline unsigned long wait_piowc(void)
    8.87 +{
    8.88 +	volatile unsigned long *piows;
    8.89 +	unsigned long zeroval, ws;
    8.90 +
    8.91 +	piows = pda->pio_write_status_addr;
    8.92 +	zeroval = pda->pio_write_status_val;
    8.93 +	do {
    8.94 +		cpu_relax();
    8.95 +	} while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
    8.96 +	return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
    8.97 +}
    8.98 +
    8.99 +/**
   8.100 + * sn_migrate - SN-specific task migration actions
   8.101 + * @task: Task being migrated to new CPU
   8.102 + *
   8.103 + * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
   8.104 + * Context switching user threads which have memory-mapped MMIO may cause
   8.105 + * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
   8.106 + * from the previous CPU's Shub before execution resumes on the new CPU.
   8.107 + */
   8.108 +void sn_migrate(struct task_struct *task)
   8.109 +{
   8.110 +	pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
   8.111 +	volatile unsigned long *adr = last_pda->pio_write_status_addr;
   8.112 +	unsigned long val = last_pda->pio_write_status_val;
   8.113 +
   8.114 +	/* Drain PIO writes from old CPU's Shub */
   8.115 +	while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
   8.116 +			!= val))
   8.117 +		cpu_relax();
   8.118 +}
   8.119 +
   8.120 +void sn_tlb_migrate_finish(struct mm_struct *mm)
   8.121 +{
   8.122 +	/* flush_tlb_mm is inefficient if more than 1 users of mm */
   8.123 +	if (mm == current->mm && mm && atomic_read(&mm->mm_users) == 1)
   8.124 +		flush_tlb_mm(mm);
   8.125 +}
   8.126 +
   8.127 +/**
   8.128 + * sn2_global_tlb_purge - globally purge translation cache of virtual address range
   8.129 + * @mm: mm_struct containing virtual address range
   8.130 + * @start: start of virtual address range
   8.131 + * @end: end of virtual address range
   8.132 + * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
   8.133 + *
   8.134 + * Purges the translation caches of all processors of the given virtual address
   8.135 + * range.
   8.136 + *
   8.137 + * Note:
   8.138 + * 	- cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
   8.139 + * 	- cpu_vm_mask is converted into a nodemask of the nodes containing the
   8.140 + * 	  cpus in cpu_vm_mask.
   8.141 + *	- if only one bit is set in cpu_vm_mask & it is the current cpu & the
   8.142 + *	  process is purging its own virtual address range, then only the
   8.143 + *	  local TLB needs to be flushed. This flushing can be done using
   8.144 + *	  ptc.l. This is the common case & avoids the global spinlock.
   8.145 + *	- if multiple cpus have loaded the context, then flushing has to be
   8.146 + *	  done with ptc.g/MMRs under protection of the global ptc_lock.
   8.147 + */
   8.148 +
   8.149 +void
   8.150 +sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
   8.151 +		     unsigned long end, unsigned long nbits)
   8.152 +{
   8.153 +	int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
   8.154 +	int mymm = (mm == current->active_mm && mm == current->mm);
   8.155 +	int use_cpu_ptcga;
   8.156 +	volatile unsigned long *ptc0, *ptc1;
   8.157 +	unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
   8.158 +	short nasids[MAX_NUMNODES], nix;
   8.159 +	nodemask_t nodes_flushed;
   8.160 +	int active, max_active, deadlock;
   8.161 +
   8.162 +	nodes_clear(nodes_flushed);
   8.163 +	i = 0;
   8.164 +
   8.165 +	for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
   8.166 +		cnode = cpu_to_node(cpu);
   8.167 +		node_set(cnode, nodes_flushed);
   8.168 +		lcpu = cpu;
   8.169 +		i++;
   8.170 +	}
   8.171 +
   8.172 +	if (i == 0)
   8.173 +		return;
   8.174 +
   8.175 +	preempt_disable();
   8.176 +
   8.177 +	if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
   8.178 +		do {
   8.179 +			ia64_ptcl(start, nbits << 2);
   8.180 +			start += (1UL << nbits);
   8.181 +		} while (start < end);
   8.182 +		ia64_srlz_i();
   8.183 +		__get_cpu_var(ptcstats).ptc_l++;
   8.184 +		preempt_enable();
   8.185 +		return;
   8.186 +	}
   8.187 +
   8.188 +	if (atomic_read(&mm->mm_users) == 1 && mymm) {
   8.189 +		flush_tlb_mm(mm);
   8.190 +		__get_cpu_var(ptcstats).change_rid++;
   8.191 +		preempt_enable();
   8.192 +		return;
   8.193 +	}
   8.194 +
   8.195 +	itc = ia64_get_itc();
   8.196 +	nix = 0;
   8.197 +	for_each_node_mask(cnode, nodes_flushed)
   8.198 +		nasids[nix++] = cnodeid_to_nasid(cnode);
   8.199 +
   8.200 +	rr_value = (mm->context << 3) | REGION_NUMBER(start);
   8.201 +
   8.202 +	shub1 = is_shub1();
   8.203 +	if (shub1) {
   8.204 +		data0 = (1UL << SH1_PTC_0_A_SHFT) |
   8.205 +		    	(nbits << SH1_PTC_0_PS_SHFT) |
   8.206 +			(rr_value << SH1_PTC_0_RID_SHFT) |
   8.207 +		    	(1UL << SH1_PTC_0_START_SHFT);
   8.208 +		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
   8.209 +		ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
   8.210 +	} else {
   8.211 +		data0 = (1UL << SH2_PTC_A_SHFT) |
   8.212 +			(nbits << SH2_PTC_PS_SHFT) |
   8.213 +		    	(1UL << SH2_PTC_START_SHFT);
   8.214 +		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC + 
   8.215 +			(rr_value << SH2_PTC_RID_SHFT));
   8.216 +		ptc1 = NULL;
   8.217 +	}
   8.218 +	
   8.219 +
   8.220 +	mynasid = get_nasid();
   8.221 +	use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
   8.222 +	max_active = max_active_pio(shub1);
   8.223 +
   8.224 +	itc = ia64_get_itc();
   8.225 +	spin_lock_irqsave(PTC_LOCK(shub1), flags);
   8.226 +	itc2 = ia64_get_itc();
   8.227 +
   8.228 +	__get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
   8.229 +	__get_cpu_var(ptcstats).shub_ptc_flushes++;
   8.230 +	__get_cpu_var(ptcstats).nodes_flushed += nix;
   8.231 +	if (!mymm)
   8.232 +		 __get_cpu_var(ptcstats).shub_ptc_flushes_not_my_mm++;
   8.233 +
   8.234 +	if (use_cpu_ptcga && !mymm) {
   8.235 +		old_rr = ia64_get_rr(start);
   8.236 +		ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
   8.237 +		ia64_srlz_d();
   8.238 +	}
   8.239 +
   8.240 +	wait_piowc();
   8.241 +	do {
   8.242 +		if (shub1)
   8.243 +			data1 = start | (1UL << SH1_PTC_1_START_SHFT);
   8.244 +		else
   8.245 +			data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
   8.246 +		deadlock = 0;
   8.247 +		active = 0;
   8.248 +		for (ibegin = 0, i = 0; i < nix; i++) {
   8.249 +			nasid = nasids[i];
   8.250 +			if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
   8.251 +				ia64_ptcga(start, nbits << 2);
   8.252 +				ia64_srlz_i();
   8.253 +			} else {
   8.254 +				ptc0 = CHANGE_NASID(nasid, ptc0);
   8.255 +				if (ptc1)
   8.256 +					ptc1 = CHANGE_NASID(nasid, ptc1);
   8.257 +				pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
   8.258 +				active++;
   8.259 +			}
   8.260 +			if (active >= max_active || i == (nix - 1)) {
   8.261 +				if ((deadlock = wait_piowc())) {
   8.262 +					sn2_ptc_deadlock_recovery(nasids, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
   8.263 +					if (reset_max_active_on_deadlock())
   8.264 +						max_active = 1;
   8.265 +				}
   8.266 +				active = 0;
   8.267 +				ibegin = i + 1;
   8.268 +			}
   8.269 +		}
   8.270 +		start += (1UL << nbits);
   8.271 +	} while (start < end);
   8.272 +
   8.273 +	itc2 = ia64_get_itc() - itc2;
   8.274 +	__get_cpu_var(ptcstats).shub_itc_clocks += itc2;
   8.275 +	if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
   8.276 +		__get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
   8.277 +
   8.278 +	if (old_rr) {
   8.279 +		ia64_set_rr(start, old_rr);
   8.280 +		ia64_srlz_d();
   8.281 +	}
   8.282 +
   8.283 +	spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
   8.284 +
   8.285 +	preempt_enable();
   8.286 +}
   8.287 +
   8.288 +/*
   8.289 + * sn2_ptc_deadlock_recovery
   8.290 + *
   8.291 + * Recover from PTC deadlocks conditions. Recovery requires stepping thru each 
   8.292 + * TLB flush transaction.  The recovery sequence is somewhat tricky & is
   8.293 + * coded in assembly language.
   8.294 + */
   8.295 +
   8.296 +void
   8.297 +sn2_ptc_deadlock_recovery(short *nasids, short ib, short ie, int mynasid,
   8.298 +			  volatile unsigned long *ptc0, unsigned long data0,
   8.299 +			  volatile unsigned long *ptc1, unsigned long data1)
   8.300 +{
   8.301 +	short nasid, i;
   8.302 +	unsigned long *piows, zeroval, n;
   8.303 +
   8.304 +	__get_cpu_var(ptcstats).deadlocks++;
   8.305 +
   8.306 +	piows = (unsigned long *) pda->pio_write_status_addr;
   8.307 +	zeroval = pda->pio_write_status_val;
   8.308 +
   8.309 +
   8.310 +	for (i=ib; i <= ie; i++) {
   8.311 +		nasid = nasids[i];
   8.312 +		if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
   8.313 +			continue;
   8.314 +		ptc0 = CHANGE_NASID(nasid, ptc0);
   8.315 +		if (ptc1)
   8.316 +			ptc1 = CHANGE_NASID(nasid, ptc1);
   8.317 +
   8.318 +		n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
   8.319 +		__get_cpu_var(ptcstats).deadlocks2 += n;
   8.320 +	}
   8.321 +
   8.322 +}
   8.323 +
   8.324 +/**
   8.325 + * sn_send_IPI_phys - send an IPI to a Nasid and slice
   8.326 + * @nasid: nasid to receive the interrupt (may be outside partition)
   8.327 + * @physid: physical cpuid to receive the interrupt.
   8.328 + * @vector: command to send
   8.329 + * @delivery_mode: delivery mechanism
   8.330 + *
   8.331 + * Sends an IPI (interprocessor interrupt) to the processor specified by
   8.332 + * @physid
   8.333 + *
   8.334 + * @delivery_mode can be one of the following
   8.335 + *
   8.336 + * %IA64_IPI_DM_INT - pend an interrupt
   8.337 + * %IA64_IPI_DM_PMI - pend a PMI
   8.338 + * %IA64_IPI_DM_NMI - pend an NMI
   8.339 + * %IA64_IPI_DM_INIT - pend an INIT interrupt
   8.340 + */
   8.341 +void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
   8.342 +{
   8.343 +	long val;
   8.344 +	unsigned long flags = 0;
   8.345 +	volatile long *p;
   8.346 +
   8.347 +	p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
   8.348 +	val = (1UL << SH_IPI_INT_SEND_SHFT) |
   8.349 +	    (physid << SH_IPI_INT_PID_SHFT) |
   8.350 +	    ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
   8.351 +	    ((long)vector << SH_IPI_INT_IDX_SHFT) |
   8.352 +	    (0x000feeUL << SH_IPI_INT_BASE_SHFT);
   8.353 +
   8.354 +	mb();
   8.355 +	if (enable_shub_wars_1_1()) {
   8.356 +		spin_lock_irqsave(&sn2_global_ptc_lock, flags);
   8.357 +	}
   8.358 +	pio_phys_write_mmr(p, val);
   8.359 +	if (enable_shub_wars_1_1()) {
   8.360 +		wait_piowc();
   8.361 +		spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
   8.362 +	}
   8.363 +
   8.364 +}
   8.365 +
   8.366 +EXPORT_SYMBOL(sn_send_IPI_phys);
   8.367 +
   8.368 +/**
   8.369 + * sn2_send_IPI - send an IPI to a processor
   8.370 + * @cpuid: target of the IPI
   8.371 + * @vector: command to send
   8.372 + * @delivery_mode: delivery mechanism
   8.373 + * @redirect: redirect the IPI?
   8.374 + *
   8.375 + * Sends an IPI (InterProcessor Interrupt) to the processor specified by
   8.376 + * @cpuid.  @vector specifies the command to send, while @delivery_mode can 
   8.377 + * be one of the following
   8.378 + *
   8.379 + * %IA64_IPI_DM_INT - pend an interrupt
   8.380 + * %IA64_IPI_DM_PMI - pend a PMI
   8.381 + * %IA64_IPI_DM_NMI - pend an NMI
   8.382 + * %IA64_IPI_DM_INIT - pend an INIT interrupt
   8.383 + */
   8.384 +void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
   8.385 +{
   8.386 +	long physid;
   8.387 +	int nasid;
   8.388 +
   8.389 +	physid = cpu_physical_id(cpuid);
   8.390 +	nasid = cpuid_to_nasid(cpuid);
   8.391 +
   8.392 +	/* the following is used only when starting cpus at boot time */
   8.393 +	if (unlikely(nasid == -1))
   8.394 +		ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
   8.395 +
   8.396 +	sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
   8.397 +}
   8.398 +
   8.399 +#ifdef CONFIG_PROC_FS
   8.400 +
   8.401 +#define PTC_BASENAME	"sgi_sn/ptc_statistics"
   8.402 +
   8.403 +static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
   8.404 +{
   8.405 +	if (*offset < NR_CPUS)
   8.406 +		return offset;
   8.407 +	return NULL;
   8.408 +}
   8.409 +
   8.410 +static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
   8.411 +{
   8.412 +	(*offset)++;
   8.413 +	if (*offset < NR_CPUS)
   8.414 +		return offset;
   8.415 +	return NULL;
   8.416 +}
   8.417 +
   8.418 +static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
   8.419 +{
   8.420 +}
   8.421 +
   8.422 +static int sn2_ptc_seq_show(struct seq_file *file, void *data)
   8.423 +{
   8.424 +	struct ptc_stats *stat;
   8.425 +	int cpu;
   8.426 +
   8.427 +	cpu = *(loff_t *) data;
   8.428 +
   8.429 +	if (!cpu) {
   8.430 +		seq_printf(file,
   8.431 +			   "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2\n");
   8.432 +		seq_printf(file, "# ptctest %d\n", sn2_ptctest);
   8.433 +	}
   8.434 +
   8.435 +	if (cpu < NR_CPUS && cpu_online(cpu)) {
   8.436 +		stat = &per_cpu(ptcstats, cpu);
   8.437 +		seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
   8.438 +				stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
   8.439 +				stat->deadlocks,
   8.440 +				1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.441 +				1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.442 +				1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.443 +				stat->shub_ptc_flushes_not_my_mm,
   8.444 +				stat->deadlocks2);
   8.445 +	}
   8.446 +	return 0;
   8.447 +}
   8.448 +
   8.449 +static struct seq_operations sn2_ptc_seq_ops = {
   8.450 +	.start = sn2_ptc_seq_start,
   8.451 +	.next = sn2_ptc_seq_next,
   8.452 +	.stop = sn2_ptc_seq_stop,
   8.453 +	.show = sn2_ptc_seq_show
   8.454 +};
   8.455 +
   8.456 +static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
   8.457 +{
   8.458 +	return seq_open(file, &sn2_ptc_seq_ops);
   8.459 +}
   8.460 +
   8.461 +static struct file_operations proc_sn2_ptc_operations = {
   8.462 +	.open = sn2_ptc_proc_open,
   8.463 +	.read = seq_read,
   8.464 +	.llseek = seq_lseek,
   8.465 +	.release = seq_release,
   8.466 +};
   8.467 +
   8.468 +static struct proc_dir_entry *proc_sn2_ptc;
   8.469 +
   8.470 +static int __init sn2_ptc_init(void)
   8.471 +{
   8.472 +	if (!ia64_platform_is("sn2"))
   8.473 +		return 0;
   8.474 +
   8.475 +	if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
   8.476 +		printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
   8.477 +		return -EINVAL;
   8.478 +	}
   8.479 +	proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
   8.480 +	spin_lock_init(&sn2_global_ptc_lock);
   8.481 +	return 0;
   8.482 +}
   8.483 +
   8.484 +static void __exit sn2_ptc_exit(void)
   8.485 +{
   8.486 +	remove_proc_entry(PTC_BASENAME, NULL);
   8.487 +}
   8.488 +
   8.489 +module_init(sn2_ptc_init);
   8.490 +module_exit(sn2_ptc_exit);
   8.491 +#endif /* CONFIG_PROC_FS */
   8.492 +
     9.1 --- a/xen/arch/ia64/linux/Makefile	Tue Dec 12 15:25:02 2006 -0700
     9.2 +++ b/xen/arch/ia64/linux/Makefile	Wed Dec 13 11:08:40 2006 -0700
     9.3 @@ -23,6 +23,7 @@ obj-y += __udivdi3.o
     9.4  obj-y += __moddi3.o
     9.5  obj-y += __umoddi3.o
     9.6  obj-y += carta_random.o
     9.7 +obj-y += io.o
     9.8  
     9.9  ## variants of divide/modulo
    9.10  ## see files in xen/arch/ia64/linux/lib (linux/arch/ia64/lib)
    10.1 --- a/xen/arch/ia64/linux/README.origin	Tue Dec 12 15:25:02 2006 -0700
    10.2 +++ b/xen/arch/ia64/linux/README.origin	Wed Dec 13 11:08:40 2006 -0700
    10.3 @@ -27,3 +27,6 @@ strlen.S		-> linux/arch/ia64/lib/strlen.
    10.4  
    10.5  # The files below are from Linux-2.6.16.33
    10.6  carta_random.S		-> linux/arch/ia64/lib/carta_random.S
    10.7 +
    10.8 +# The files below are from Linux-2.6.19
    10.9 +io.c			-> linux/arch/ia64/lib/io.c
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/ia64/linux/dig/Makefile	Wed Dec 13 11:08:40 2006 -0700
    11.3 @@ -0,0 +1,1 @@
    11.4 +obj-y += machvec.o
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen/arch/ia64/linux/dig/README.origin	Wed Dec 13 11:08:40 2006 -0700
    12.3 @@ -0,0 +1,7 @@
    12.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    12.5 +
    12.6 +NOTE: DO NOT commit changes to these files!   If a file
    12.7 +needs to be changed, move it to ../linux-xen and follow
    12.8 +the instructions in the README there.
    12.9 +
   12.10 +machvec.c		-> linux/arch/ia64/dig/machvec.c
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/xen/arch/ia64/linux/dig/machvec.c	Wed Dec 13 11:08:40 2006 -0700
    13.3 @@ -0,0 +1,3 @@
    13.4 +#define MACHVEC_PLATFORM_NAME		dig
    13.5 +#define MACHVEC_PLATFORM_HEADER		<asm/machvec_dig.h>
    13.6 +#include <asm/machvec_init.h>
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/xen/arch/ia64/linux/hp/Makefile	Wed Dec 13 11:08:40 2006 -0700
    14.3 @@ -0,0 +1,1 @@
    14.4 +subdir-y += zx1
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/xen/arch/ia64/linux/hp/zx1/Makefile	Wed Dec 13 11:08:40 2006 -0700
    15.3 @@ -0,0 +1,1 @@
    15.4 +obj-y += hpzx1_machvec.o
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/xen/arch/ia64/linux/hp/zx1/README.origin	Wed Dec 13 11:08:40 2006 -0700
    16.3 @@ -0,0 +1,7 @@
    16.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    16.5 +
    16.6 +NOTE: DO NOT commit changes to these files!   If a file
    16.7 +needs to be changed, move it to ../linux-xen and follow
    16.8 +the instructions in the README there.
    16.9 +
   16.10 +hpzx1_machvec.c		-> linux/arch/ia64/hp/zx1/hpzx1_machvec.c
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/xen/arch/ia64/linux/hp/zx1/hpzx1_machvec.c	Wed Dec 13 11:08:40 2006 -0700
    17.3 @@ -0,0 +1,3 @@
    17.4 +#define MACHVEC_PLATFORM_NAME		hpzx1
    17.5 +#define MACHVEC_PLATFORM_HEADER		<asm/machvec_hpzx1.h>
    17.6 +#include <asm/machvec_init.h>
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/xen/arch/ia64/linux/io.c	Wed Dec 13 11:08:40 2006 -0700
    18.3 @@ -0,0 +1,164 @@
    18.4 +#include <linux/module.h>
    18.5 +#include <linux/types.h>
    18.6 +
    18.7 +#include <asm/io.h>
    18.8 +
    18.9 +/*
   18.10 + * Copy data from IO memory space to "real" memory space.
   18.11 + * This needs to be optimized.
   18.12 + */
   18.13 +void memcpy_fromio(void *to, const volatile void __iomem *from, long count)
   18.14 +{
   18.15 +	char *dst = to;
   18.16 +
   18.17 +	while (count) {
   18.18 +		count--;
   18.19 +		*dst++ = readb(from++);
   18.20 +	}
   18.21 +}
   18.22 +EXPORT_SYMBOL(memcpy_fromio);
   18.23 +
   18.24 +/*
   18.25 + * Copy data from "real" memory space to IO memory space.
   18.26 + * This needs to be optimized.
   18.27 + */
   18.28 +void memcpy_toio(volatile void __iomem *to, const void *from, long count)
   18.29 +{
   18.30 +	const char *src = from;
   18.31 +
   18.32 +	while (count) {
   18.33 +		count--;
   18.34 +		writeb(*src++, to++);
   18.35 +	}
   18.36 +}
   18.37 +EXPORT_SYMBOL(memcpy_toio);
   18.38 +
   18.39 +/*
   18.40 + * "memset" on IO memory space.
   18.41 + * This needs to be optimized.
   18.42 + */
   18.43 +void memset_io(volatile void __iomem *dst, int c, long count)
   18.44 +{
   18.45 +	unsigned char ch = (char)(c & 0xff);
   18.46 +
   18.47 +	while (count) {
   18.48 +		count--;
   18.49 +		writeb(ch, dst);
   18.50 +		dst++;
   18.51 +	}
   18.52 +}
   18.53 +EXPORT_SYMBOL(memset_io);
   18.54 +
   18.55 +#ifdef CONFIG_IA64_GENERIC
   18.56 +
   18.57 +#undef __ia64_inb
   18.58 +#undef __ia64_inw
   18.59 +#undef __ia64_inl
   18.60 +#undef __ia64_outb
   18.61 +#undef __ia64_outw
   18.62 +#undef __ia64_outl
   18.63 +#undef __ia64_readb
   18.64 +#undef __ia64_readw
   18.65 +#undef __ia64_readl
   18.66 +#undef __ia64_readq
   18.67 +#undef __ia64_readb_relaxed
   18.68 +#undef __ia64_readw_relaxed
   18.69 +#undef __ia64_readl_relaxed
   18.70 +#undef __ia64_readq_relaxed
   18.71 +#undef __ia64_writeb
   18.72 +#undef __ia64_writew
   18.73 +#undef __ia64_writel
   18.74 +#undef __ia64_writeq
   18.75 +#undef __ia64_mmiowb
   18.76 +
   18.77 +unsigned int
   18.78 +__ia64_inb (unsigned long port)
   18.79 +{
   18.80 +	return ___ia64_inb(port);
   18.81 +}
   18.82 +
   18.83 +unsigned int
   18.84 +__ia64_inw (unsigned long port)
   18.85 +{
   18.86 +	return ___ia64_inw(port);
   18.87 +}
   18.88 +
   18.89 +unsigned int
   18.90 +__ia64_inl (unsigned long port)
   18.91 +{
   18.92 +	return ___ia64_inl(port);
   18.93 +}
   18.94 +
   18.95 +void
   18.96 +__ia64_outb (unsigned char val, unsigned long port)
   18.97 +{
   18.98 +	___ia64_outb(val, port);
   18.99 +}
  18.100 +
  18.101 +void
  18.102 +__ia64_outw (unsigned short val, unsigned long port)
  18.103 +{
  18.104 +	___ia64_outw(val, port);
  18.105 +}
  18.106 +
  18.107 +void
  18.108 +__ia64_outl (unsigned int val, unsigned long port)
  18.109 +{
  18.110 +	___ia64_outl(val, port);
  18.111 +}
  18.112 +
  18.113 +unsigned char
  18.114 +__ia64_readb (void __iomem *addr)
  18.115 +{
  18.116 +	return ___ia64_readb (addr);
  18.117 +}
  18.118 +
  18.119 +unsigned short
  18.120 +__ia64_readw (void __iomem *addr)
  18.121 +{
  18.122 +	return ___ia64_readw (addr);
  18.123 +}
  18.124 +
  18.125 +unsigned int
  18.126 +__ia64_readl (void __iomem *addr)
  18.127 +{
  18.128 +	return ___ia64_readl (addr);
  18.129 +}
  18.130 +
  18.131 +unsigned long
  18.132 +__ia64_readq (void __iomem *addr)
  18.133 +{
  18.134 +	return ___ia64_readq (addr);
  18.135 +}
  18.136 +
  18.137 +unsigned char
  18.138 +__ia64_readb_relaxed (void __iomem *addr)
  18.139 +{
  18.140 +	return ___ia64_readb (addr);
  18.141 +}
  18.142 +
  18.143 +unsigned short
  18.144 +__ia64_readw_relaxed (void __iomem *addr)
  18.145 +{
  18.146 +	return ___ia64_readw (addr);
  18.147 +}
  18.148 +
  18.149 +unsigned int
  18.150 +__ia64_readl_relaxed (void __iomem *addr)
  18.151 +{
  18.152 +	return ___ia64_readl (addr);
  18.153 +}
  18.154 +
  18.155 +unsigned long
  18.156 +__ia64_readq_relaxed (void __iomem *addr)
  18.157 +{
  18.158 +	return ___ia64_readq (addr);
  18.159 +}
  18.160 +
  18.161 +void
  18.162 +__ia64_mmiowb(void)
  18.163 +{
  18.164 +	___ia64_mmiowb();
  18.165 +}
  18.166 +
  18.167 +#endif /* CONFIG_IA64_GENERIC */
    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/xen/arch/ia64/linux/sn/Makefile	Wed Dec 13 11:08:40 2006 -0700
    19.3 @@ -0,0 +1,2 @@
    19.4 +subdir-y += kernel
    19.5 +subdir-y += pci
    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/xen/arch/ia64/linux/sn/kernel/Makefile	Wed Dec 13 11:08:40 2006 -0700
    20.3 @@ -0,0 +1,3 @@
    20.4 +obj-y += machvec.o
    20.5 +obj-y += pio_phys.o
    20.6 +obj-y += ptc_deadlock.o
    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/xen/arch/ia64/linux/sn/kernel/README.origin	Wed Dec 13 11:08:40 2006 -0700
    21.3 @@ -0,0 +1,9 @@
    21.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    21.5 +
    21.6 +NOTE: DO NOT commit changes to these files!   If a file
    21.7 +needs to be changed, move it to ../linux-xen and follow
    21.8 +the instructions in the README there.
    21.9 +
   21.10 +machvec.c		-> linux/arch/ia64/sn/kernel/machvec.c
   21.11 +pio_phys.S		-> linux/arch/ia64/sn/kernel/pio_phys.S
   21.12 +ptc_deadlock.S		-> linux/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/xen/arch/ia64/linux/sn/kernel/machvec.c	Wed Dec 13 11:08:40 2006 -0700
    22.3 @@ -0,0 +1,11 @@
    22.4 +/*
    22.5 + * This file is subject to the terms and conditions of the GNU General Public
    22.6 + * License.  See the file "COPYING" in the main directory of this archive
    22.7 + * for more details.
    22.8 + *
    22.9 + * Copyright (c) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
   22.10 + */
   22.11 +
   22.12 +#define MACHVEC_PLATFORM_NAME	sn2
   22.13 +#define MACHVEC_PLATFORM_HEADER	<asm/machvec_sn2.h>
   22.14 +#include <asm/machvec_init.h>
    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/xen/arch/ia64/linux/sn/kernel/pio_phys.S	Wed Dec 13 11:08:40 2006 -0700
    23.3 @@ -0,0 +1,71 @@
    23.4 +/*
    23.5 + * This file is subject to the terms and conditions of the GNU General Public
    23.6 + * License.  See the file "COPYING" in the main directory of this archive
    23.7 + * for more details.
    23.8 + *
    23.9 + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
   23.10 + *
   23.11 + * This file contains macros used to access MMR registers via
   23.12 + * uncached physical addresses.
   23.13 + *      pio_phys_read_mmr  - read an MMR
   23.14 + *      pio_phys_write_mmr - write an MMR
   23.15 + *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
   23.16 + *              Second MMR will be skipped if address is NULL
   23.17 + *
   23.18 + * Addresses passed to these routines should be uncached physical addresses
   23.19 + * 	ie., 0x80000....
   23.20 + */
   23.21 +
   23.22 +
   23.23 +
   23.24 +#include <asm/asmmacro.h>
   23.25 +#include <asm/page.h>
   23.26 +
   23.27 +GLOBAL_ENTRY(pio_phys_read_mmr)
   23.28 +	.prologue
   23.29 +	.regstk 1,0,0,0
   23.30 +	.body
   23.31 +	mov r2=psr
   23.32 +	rsm psr.i | psr.dt
   23.33 +	;;
   23.34 +	srlz.d
   23.35 +	ld8.acq r8=[r32]
   23.36 +	;;
   23.37 +	mov psr.l=r2;;
   23.38 +	srlz.d
   23.39 +	br.ret.sptk.many rp
   23.40 +END(pio_phys_read_mmr)
   23.41 +
   23.42 +GLOBAL_ENTRY(pio_phys_write_mmr)
   23.43 +	.prologue
   23.44 +	.regstk 2,0,0,0
   23.45 +	.body
   23.46 +	mov r2=psr
   23.47 +	rsm psr.i | psr.dt
   23.48 +	;;
   23.49 +	srlz.d
   23.50 +	st8.rel [r32]=r33
   23.51 +	;;
   23.52 +	mov psr.l=r2;;
   23.53 +	srlz.d
   23.54 +	br.ret.sptk.many rp
   23.55 +END(pio_phys_write_mmr)
   23.56 +
   23.57 +GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)
   23.58 +	.prologue
   23.59 +	.regstk 4,0,0,0
   23.60 +	.body
   23.61 +	mov r2=psr
   23.62 +	cmp.ne p9,p0=r34,r0;
   23.63 +	rsm psr.i | psr.dt | psr.ic
   23.64 +	;;
   23.65 +	srlz.d
   23.66 +	st8.rel [r32]=r33
   23.67 +(p9)	st8.rel [r34]=r35
   23.68 +	;;
   23.69 +	mov psr.l=r2;;
   23.70 +	srlz.d
   23.71 +	br.ret.sptk.many rp
   23.72 +END(pio_atomic_phys_write_mmrs)
   23.73 +
   23.74 +
    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/xen/arch/ia64/linux/sn/kernel/ptc_deadlock.S	Wed Dec 13 11:08:40 2006 -0700
    24.3 @@ -0,0 +1,92 @@
    24.4 +/* 
    24.5 + * This file is subject to the terms and conditions of the GNU General Public
    24.6 + * License.  See the file "COPYING" in the main directory of this archive
    24.7 + * for more details.
    24.8 + *
    24.9 + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
   24.10 + */
   24.11 +
   24.12 +#include <asm/types.h>
   24.13 +#include <asm/sn/shub_mmr.h>
   24.14 +
   24.15 +#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
   24.16 +#define WRITECOUNTMASK	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
   24.17 +#define ALIAS_OFFSET	8
   24.18 +
   24.19 +
   24.20 +	.global	sn2_ptc_deadlock_recovery_core
   24.21 +	.proc  	sn2_ptc_deadlock_recovery_core
   24.22 +
   24.23 +sn2_ptc_deadlock_recovery_core:
   24.24 +	.regstk 6,0,0,0
   24.25 +
   24.26 +	ptc0  	 = in0
   24.27 +	data0 	 = in1
   24.28 +	ptc1  	 = in2
   24.29 +	data1 	 = in3
   24.30 +	piowc 	 = in4
   24.31 +	zeroval  = in5
   24.32 +	piowcphy = r30
   24.33 +	psrsave  = r2
   24.34 +	scr1	 = r16
   24.35 +	scr2	 = r17
   24.36 +	mask	 = r18
   24.37 +
   24.38 +
   24.39 +	extr.u	piowcphy=piowc,0,61;;	// Convert piowc to uncached physical address
   24.40 +	dep	piowcphy=-1,piowcphy,63,1
   24.41 +	movl	mask=WRITECOUNTMASK
   24.42 +	mov	r8=r0
   24.43 +
   24.44 +1:
   24.45 +	cmp.ne  p8,p9=r0,ptc1		// Test for shub type (ptc1 non-null on shub1)
   24.46 +					// p8 = 1 if shub1, p9 = 1 if shub2
   24.47 +
   24.48 +	add	scr2=ALIAS_OFFSET,piowc	// Address of WRITE_STATUS alias register 
   24.49 +	mov	scr1=7;;		// Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR
   24.50 +(p8)	st8.rel	[scr2]=scr1;;
   24.51 +(p9)	ld8.acq	scr1=[scr2];;
   24.52 +
   24.53 +5:	ld8.acq	scr1=[piowc];;		// Wait for PIOs to complete.
   24.54 +	hint	@pause
   24.55 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.56 +	cmp.ne	p6,p0=zeroval,scr2
   24.57 +(p6)	br.cond.sptk 5b
   24.58 +	
   24.59 +
   24.60 +
   24.61 +	////////////// BEGIN PHYSICAL MODE ////////////////////
   24.62 +	mov psrsave=psr			// Disable IC (no PMIs)
   24.63 +	rsm psr.i | psr.dt | psr.ic;;
   24.64 +	srlz.i;;
   24.65 +
   24.66 +	st8.rel [ptc0]=data0		// Write PTC0 & wait for completion.
   24.67 +
   24.68 +5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
   24.69 +	hint	@pause
   24.70 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.71 +	cmp.ne	p6,p0=zeroval,scr2
   24.72 +(p6)	br.cond.sptk 5b;;
   24.73 +
   24.74 +	tbit.nz	p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
   24.75 +(p7)	cmp.ne p7,p0=r0,ptc1;;		// Test for non-null ptc1
   24.76 +	
   24.77 +(p7)	st8.rel [ptc1]=data1;;		// Now write PTC1.
   24.78 +
   24.79 +5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
   24.80 +	hint	@pause
   24.81 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.82 +	cmp.ne	p6,p0=zeroval,scr2
   24.83 +(p6)	br.cond.sptk 5b
   24.84 +	
   24.85 +	tbit.nz	p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
   24.86 +
   24.87 +	mov psr.l=psrsave;;		// Reenable IC
   24.88 +	srlz.i;;
   24.89 +	////////////// END   PHYSICAL MODE ////////////////////
   24.90 +
   24.91 +(p8)	add	r8=1,r8
   24.92 +(p8)	br.cond.spnt 1b;;		// Repeat if DEADLOCK occurred.
   24.93 +
   24.94 +	br.ret.sptk	rp
   24.95 +	.endp sn2_ptc_deadlock_recovery_core
    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/xen/arch/ia64/linux/sn/pci/Makefile	Wed Dec 13 11:08:40 2006 -0700
    25.3 @@ -0,0 +1,1 @@
    25.4 +subdir-y += pcibr
    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/Makefile	Wed Dec 13 11:08:40 2006 -0700
    26.3 @@ -0,0 +1,1 @@
    26.4 +obj-y += pcibr_reg.o
    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/README.origin	Wed Dec 13 11:08:40 2006 -0700
    27.3 @@ -0,0 +1,7 @@
    27.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    27.5 +
    27.6 +NOTE: DO NOT commit changes to these files!   If a file
    27.7 +needs to be changed, move it to ../linux-xen and follow
    27.8 +the instructions in the README there.
    27.9 +
   27.10 +pcibr_reg.c		-> linux/arch/ia64/sn/pci/pcibr/pcibr_reg.c
    28.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/pcibr_reg.c	Wed Dec 13 11:08:40 2006 -0700
    28.3 @@ -0,0 +1,285 @@
    28.4 +/*
    28.5 + * This file is subject to the terms and conditions of the GNU General Public
    28.6 + * License.  See the file "COPYING" in the main directory of this archive
    28.7 + * for more details.
    28.8 + *
    28.9 + * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
   28.10 + */
   28.11 +
   28.12 +#include <linux/interrupt.h>
   28.13 +#include <linux/types.h>
   28.14 +#include <asm/sn/io.h>
   28.15 +#include <asm/sn/pcibr_provider.h>
   28.16 +#include <asm/sn/pcibus_provider_defs.h>
   28.17 +#include <asm/sn/pcidev.h>
   28.18 +#include <asm/sn/pic.h>
   28.19 +#include <asm/sn/tiocp.h>
   28.20 +
   28.21 +union br_ptr {
   28.22 +	struct tiocp tio;
   28.23 +	struct pic pic;
   28.24 +};
   28.25 +
   28.26 +/*
   28.27 + * Control Register Access -- Read/Write                            0000_0020
   28.28 + */
   28.29 +void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
   28.30 +{
   28.31 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.32 +
   28.33 +	if (pcibus_info) {
   28.34 +		switch (pcibus_info->pbi_bridge_type) {
   28.35 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.36 +			__sn_clrq_relaxed(&ptr->tio.cp_control, bits);
   28.37 +			break;
   28.38 +		case PCIBR_BRIDGETYPE_PIC:
   28.39 +			__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);
   28.40 +			break;
   28.41 +		default:
   28.42 +			panic
   28.43 +			    ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
   28.44 +			     ptr);
   28.45 +		}
   28.46 +	}
   28.47 +}
   28.48 +
   28.49 +void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
   28.50 +{
   28.51 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.52 +
   28.53 +	if (pcibus_info) {
   28.54 +		switch (pcibus_info->pbi_bridge_type) {
   28.55 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.56 +			__sn_setq_relaxed(&ptr->tio.cp_control, bits);
   28.57 +			break;
   28.58 +		case PCIBR_BRIDGETYPE_PIC:
   28.59 +			__sn_setq_relaxed(&ptr->pic.p_wid_control, bits);
   28.60 +			break;
   28.61 +		default:
   28.62 +			panic
   28.63 +			    ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
   28.64 +			     ptr);
   28.65 +		}
   28.66 +	}
   28.67 +}
   28.68 +
   28.69 +/*
   28.70 + * PCI/PCIX Target Flush Register Access -- Read Only		    0000_0050
   28.71 + */
   28.72 +u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
   28.73 +{
   28.74 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.75 +	u64 ret = 0;
   28.76 +
   28.77 +	if (pcibus_info) {
   28.78 +		switch (pcibus_info->pbi_bridge_type) {
   28.79 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.80 +			ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);
   28.81 +			break;
   28.82 +		case PCIBR_BRIDGETYPE_PIC:
   28.83 +			ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);
   28.84 +			break;
   28.85 +		default:
   28.86 +			panic
   28.87 +			    ("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
   28.88 +			     ptr);
   28.89 +		}
   28.90 +	}
   28.91 +
   28.92 +	/* Read of the Target Flush should always return zero */
   28.93 +	if (ret != 0)
   28.94 +		panic("pcireg_tflush_get:Target Flush failed\n");
   28.95 +
   28.96 +	return ret;
   28.97 +}
   28.98 +
   28.99 +/*
  28.100 + * Interrupt Status Register Access -- Read Only		    0000_0100
  28.101 + */
  28.102 +u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
  28.103 +{
  28.104 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.105 +	u64 ret = 0;
  28.106 +
  28.107 +	if (pcibus_info) {
  28.108 +		switch (pcibus_info->pbi_bridge_type) {
  28.109 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.110 +			ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);
  28.111 +			break;
  28.112 +		case PCIBR_BRIDGETYPE_PIC:
  28.113 +			ret = __sn_readq_relaxed(&ptr->pic.p_int_status);
  28.114 +			break;
  28.115 +		default:
  28.116 +			panic
  28.117 +			    ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
  28.118 +			     ptr);
  28.119 +		}
  28.120 +	}
  28.121 +	return ret;
  28.122 +}
  28.123 +
  28.124 +/*
  28.125 + * Interrupt Enable Register Access -- Read/Write                   0000_0108
  28.126 + */
  28.127 +void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
  28.128 +{
  28.129 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.130 +
  28.131 +	if (pcibus_info) {
  28.132 +		switch (pcibus_info->pbi_bridge_type) {
  28.133 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.134 +			__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
  28.135 +			break;
  28.136 +		case PCIBR_BRIDGETYPE_PIC:
  28.137 +			__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
  28.138 +			break;
  28.139 +		default:
  28.140 +			panic
  28.141 +			    ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
  28.142 +			     ptr);
  28.143 +		}
  28.144 +	}
  28.145 +}
  28.146 +
  28.147 +void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
  28.148 +{
  28.149 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.150 +
  28.151 +	if (pcibus_info) {
  28.152 +		switch (pcibus_info->pbi_bridge_type) {
  28.153 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.154 +			__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);
  28.155 +			break;
  28.156 +		case PCIBR_BRIDGETYPE_PIC:
  28.157 +			__sn_setq_relaxed(&ptr->pic.p_int_enable, bits);
  28.158 +			break;
  28.159 +		default:
  28.160 +			panic
  28.161 +			    ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
  28.162 +			     ptr);
  28.163 +		}
  28.164 +	}
  28.165 +}
  28.166 +
  28.167 +/*
  28.168 + * Intr Host Address Register (int_addr) -- Read/Write  0000_0130 - 0000_0168
  28.169 + */
  28.170 +void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
  28.171 +			       u64 addr)
  28.172 +{
  28.173 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.174 +
  28.175 +	if (pcibus_info) {
  28.176 +		switch (pcibus_info->pbi_bridge_type) {
  28.177 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.178 +			__sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
  28.179 +			    TIOCP_HOST_INTR_ADDR);
  28.180 +			__sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
  28.181 +			    (addr & TIOCP_HOST_INTR_ADDR));
  28.182 +			break;
  28.183 +		case PCIBR_BRIDGETYPE_PIC:
  28.184 +			__sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
  28.185 +			    PIC_HOST_INTR_ADDR);
  28.186 +			__sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
  28.187 +			    (addr & PIC_HOST_INTR_ADDR));
  28.188 +			break;
  28.189 +		default:
  28.190 +			panic
  28.191 +			    ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
  28.192 +			     ptr);
  28.193 +		}
  28.194 +	}
  28.195 +}
  28.196 +
  28.197 +/*
  28.198 + * Force Interrupt Register Access -- Write Only	0000_01C0 - 0000_01F8
  28.199 + */
  28.200 +void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
  28.201 +{
  28.202 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.203 +
  28.204 +	if (pcibus_info) {
  28.205 +		switch (pcibus_info->pbi_bridge_type) {
  28.206 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.207 +			writeq(1, &ptr->tio.cp_force_pin[int_n]);
  28.208 +			break;
  28.209 +		case PCIBR_BRIDGETYPE_PIC:
  28.210 +			writeq(1, &ptr->pic.p_force_pin[int_n]);
  28.211 +			break;
  28.212 +		default:
  28.213 +			panic
  28.214 +			    ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
  28.215 +			     ptr);
  28.216 +		}
  28.217 +	}
  28.218 +}
  28.219 +
  28.220 +/*
  28.221 + * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
  28.222 + */
  28.223 +u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
  28.224 +{
  28.225 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.226 +	u64 ret = 0;
  28.227 +
  28.228 +	if (pcibus_info) {
  28.229 +		switch (pcibus_info->pbi_bridge_type) {
  28.230 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.231 +			ret =
  28.232 +			    __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
  28.233 +			break;
  28.234 +		case PCIBR_BRIDGETYPE_PIC:
  28.235 +			ret =
  28.236 +			    __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
  28.237 +			break;
  28.238 +		default:
  28.239 +		      panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
  28.240 +		}
  28.241 +
  28.242 +	}
  28.243 +	/* Read of the Write Buffer Flush should always return zero */
  28.244 +	return ret;
  28.245 +}
  28.246 +
  28.247 +void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
  28.248 +			u64 val)
  28.249 +{
  28.250 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.251 +
  28.252 +	if (pcibus_info) {
  28.253 +		switch (pcibus_info->pbi_bridge_type) {
  28.254 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.255 +			writeq(val, &ptr->tio.cp_int_ate_ram[ate_index]);
  28.256 +			break;
  28.257 +		case PCIBR_BRIDGETYPE_PIC:
  28.258 +			writeq(val, &ptr->pic.p_int_ate_ram[ate_index]);
  28.259 +			break;
  28.260 +		default:
  28.261 +			panic
  28.262 +			    ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
  28.263 +			     ptr);
  28.264 +		}
  28.265 +	}
  28.266 +}
  28.267 +
  28.268 +u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
  28.269 +{
  28.270 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.271 +	u64 __iomem *ret = NULL;
  28.272 +
  28.273 +	if (pcibus_info) {
  28.274 +		switch (pcibus_info->pbi_bridge_type) {
  28.275 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.276 +			ret = &ptr->tio.cp_int_ate_ram[ate_index];
  28.277 +			break;
  28.278 +		case PCIBR_BRIDGETYPE_PIC:
  28.279 +			ret = &ptr->pic.p_int_ate_ram[ate_index];
  28.280 +			break;
  28.281 +		default:
  28.282 +			panic
  28.283 +			    ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
  28.284 +			     ptr);
  28.285 +		}
  28.286 +	}
  28.287 +	return ret;
  28.288 +}
    29.1 --- a/xen/include/asm-ia64/linux-null/linux/ioport.h	Tue Dec 12 15:25:02 2006 -0700
    29.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.3 @@ -1,1 +0,0 @@
    29.4 -/* This file is intentionally left empty. */
    30.1 --- a/xen/include/asm-ia64/linux-xen/asm/README.origin	Tue Dec 12 15:25:02 2006 -0700
    30.2 +++ b/xen/include/asm-ia64/linux-xen/asm/README.origin	Wed Dec 13 11:08:40 2006 -0700
    30.3 @@ -34,3 +34,9 @@ iosapic.h		-> linux/include/asm-ia64/ios
    30.4  # The files below are from Linux-2.6.16.33
    30.5  perfmon.h		-> linux/include/asm-ia64/perfmon.h
    30.6  perfmon_default_smpl.h	-> linux/include/asm-ia64/perfmon_default_smpl.h
    30.7 +
    30.8 +# The files below are from Linux-2.6.19
    30.9 +machvec_dig.h		-> linux/include/asm-ia64/machvec_dig.h
   30.10 +machvec_sn2.h		-> linux/include/asm-ia64/machvec_sn2.h
   30.11 +machvec_hpzx1.h		-> linux/include/asm-ia64/machvec_hpzx1.h
   30.12 +machvec_pci.h		-> linux/include/asm-ia64/pci.h
    31.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_dig.h	Wed Dec 13 11:08:40 2006 -0700
    31.3 @@ -0,0 +1,16 @@
    31.4 +#ifndef _ASM_IA64_MACHVEC_DIG_h
    31.5 +#define _ASM_IA64_MACHVEC_DIG_h
    31.6 +
    31.7 +extern ia64_mv_setup_t dig_setup;
    31.8 +
    31.9 +/*
   31.10 + * This stuff has dual use!
   31.11 + *
   31.12 + * For a generic kernel, the macros are used to initialize the
   31.13 + * platform's machvec structure.  When compiling a non-generic kernel,
   31.14 + * the macros are used directly.
   31.15 + */
   31.16 +#define platform_name		"dig"
   31.17 +#define platform_setup		dig_setup
   31.18 +
   31.19 +#endif /* _ASM_IA64_MACHVEC_DIG_h */
    32.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    32.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_hpzx1.h	Wed Dec 13 11:08:40 2006 -0700
    32.3 @@ -0,0 +1,37 @@
    32.4 +#ifndef _ASM_IA64_MACHVEC_HPZX1_h
    32.5 +#define _ASM_IA64_MACHVEC_HPZX1_h
    32.6 +
    32.7 +extern ia64_mv_setup_t			dig_setup;
    32.8 +extern ia64_mv_dma_alloc_coherent	sba_alloc_coherent;
    32.9 +extern ia64_mv_dma_free_coherent	sba_free_coherent;
   32.10 +extern ia64_mv_dma_map_single		sba_map_single;
   32.11 +extern ia64_mv_dma_unmap_single		sba_unmap_single;
   32.12 +extern ia64_mv_dma_map_sg		sba_map_sg;
   32.13 +extern ia64_mv_dma_unmap_sg		sba_unmap_sg;
   32.14 +extern ia64_mv_dma_supported		sba_dma_supported;
   32.15 +extern ia64_mv_dma_mapping_error	sba_dma_mapping_error;
   32.16 +
   32.17 +/*
   32.18 + * This stuff has dual use!
   32.19 + *
   32.20 + * For a generic kernel, the macros are used to initialize the
   32.21 + * platform's machvec structure.  When compiling a non-generic kernel,
   32.22 + * the macros are used directly.
   32.23 + */
   32.24 +#define platform_name				"hpzx1"
   32.25 +#define platform_setup				dig_setup
   32.26 +#define platform_dma_init			machvec_noop
   32.27 +#define platform_dma_alloc_coherent		sba_alloc_coherent
   32.28 +#define platform_dma_free_coherent		sba_free_coherent
   32.29 +#define platform_dma_map_single			sba_map_single
   32.30 +#define platform_dma_unmap_single		sba_unmap_single
   32.31 +#define platform_dma_map_sg			sba_map_sg
   32.32 +#define platform_dma_unmap_sg			sba_unmap_sg
   32.33 +#define platform_dma_sync_single_for_cpu	machvec_dma_sync_single
   32.34 +#define platform_dma_sync_sg_for_cpu		machvec_dma_sync_sg
   32.35 +#define platform_dma_sync_single_for_device	machvec_dma_sync_single
   32.36 +#define platform_dma_sync_sg_for_device		machvec_dma_sync_sg
   32.37 +#define platform_dma_supported			sba_dma_supported
   32.38 +#define platform_dma_mapping_error		sba_dma_mapping_error
   32.39 +
   32.40 +#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
    33.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    33.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_sn2.h	Wed Dec 13 11:08:40 2006 -0700
    33.3 @@ -0,0 +1,133 @@
    33.4 +/*
    33.5 + * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc.  All Rights Reserved.
    33.6 + * 
    33.7 + * This program is free software; you can redistribute it and/or modify it 
    33.8 + * under the terms of version 2 of the GNU General Public License 
    33.9 + * as published by the Free Software Foundation.
   33.10 + * 
   33.11 + * This program is distributed in the hope that it would be useful, but 
   33.12 + * WITHOUT ANY WARRANTY; without even the implied warranty of 
   33.13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
   33.14 + * 
   33.15 + * Further, this software is distributed without any warranty that it is 
   33.16 + * free of the rightful claim of any third person regarding infringement 
   33.17 + * or the like.  Any license provided herein, whether implied or 
   33.18 + * otherwise, applies only to this software file.  Patent licenses, if 
   33.19 + * any, provided herein do not apply to combinations of this program with 
   33.20 + * other software, or any other product whatsoever.
   33.21 + * 
   33.22 + * You should have received a copy of the GNU General Public 
   33.23 + * License along with this program; if not, write the Free Software 
   33.24 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
   33.25 + * 
   33.26 + * For further information regarding this notice, see: 
   33.27 + * 
   33.28 + * http://oss.sgi.com/projects/GenInfo/NoticeExplan
   33.29 + */
   33.30 +
   33.31 +#ifndef _ASM_IA64_MACHVEC_SN2_H
   33.32 +#define _ASM_IA64_MACHVEC_SN2_H
   33.33 +
   33.34 +extern ia64_mv_setup_t sn_setup;
   33.35 +extern ia64_mv_cpu_init_t sn_cpu_init;
   33.36 +extern ia64_mv_irq_init_t sn_irq_init;
   33.37 +extern ia64_mv_send_ipi_t sn2_send_IPI;
   33.38 +extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
   33.39 +extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
   33.40 +extern ia64_mv_tlb_migrate_finish_t	sn_tlb_migrate_finish;
   33.41 +extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
   33.42 +extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
   33.43 +extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
   33.44 +extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
   33.45 +extern ia64_mv_inb_t __sn_inb;
   33.46 +extern ia64_mv_inw_t __sn_inw;
   33.47 +extern ia64_mv_inl_t __sn_inl;
   33.48 +extern ia64_mv_outb_t __sn_outb;
   33.49 +extern ia64_mv_outw_t __sn_outw;
   33.50 +extern ia64_mv_outl_t __sn_outl;
   33.51 +extern ia64_mv_mmiowb_t __sn_mmiowb;
   33.52 +extern ia64_mv_readb_t __sn_readb;
   33.53 +extern ia64_mv_readw_t __sn_readw;
   33.54 +extern ia64_mv_readl_t __sn_readl;
   33.55 +extern ia64_mv_readq_t __sn_readq;
   33.56 +extern ia64_mv_readb_t __sn_readb_relaxed;
   33.57 +extern ia64_mv_readw_t __sn_readw_relaxed;
   33.58 +extern ia64_mv_readl_t __sn_readl_relaxed;
   33.59 +extern ia64_mv_readq_t __sn_readq_relaxed;
   33.60 +extern ia64_mv_dma_alloc_coherent	sn_dma_alloc_coherent;
   33.61 +extern ia64_mv_dma_free_coherent	sn_dma_free_coherent;
   33.62 +extern ia64_mv_dma_map_single		sn_dma_map_single;
   33.63 +extern ia64_mv_dma_unmap_single		sn_dma_unmap_single;
   33.64 +extern ia64_mv_dma_map_sg		sn_dma_map_sg;
   33.65 +extern ia64_mv_dma_unmap_sg		sn_dma_unmap_sg;
   33.66 +extern ia64_mv_dma_sync_single_for_cpu	sn_dma_sync_single_for_cpu;
   33.67 +extern ia64_mv_dma_sync_sg_for_cpu	sn_dma_sync_sg_for_cpu;
   33.68 +extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
   33.69 +extern ia64_mv_dma_sync_sg_for_device	sn_dma_sync_sg_for_device;
   33.70 +extern ia64_mv_dma_mapping_error	sn_dma_mapping_error;
   33.71 +extern ia64_mv_dma_supported		sn_dma_supported;
   33.72 +extern ia64_mv_migrate_t		sn_migrate;
   33.73 +extern ia64_mv_setup_msi_irq_t		sn_setup_msi_irq;
   33.74 +extern ia64_mv_teardown_msi_irq_t	sn_teardown_msi_irq;
   33.75 +
   33.76 +
   33.77 +/*
   33.78 + * This stuff has dual use!
   33.79 + *
   33.80 + * For a generic kernel, the macros are used to initialize the
   33.81 + * platform's machvec structure.  When compiling a non-generic kernel,
   33.82 + * the macros are used directly.
   33.83 + */
   33.84 +#define platform_name			"sn2"
   33.85 +#define platform_setup			sn_setup
   33.86 +#define platform_cpu_init		sn_cpu_init
   33.87 +#define platform_irq_init		sn_irq_init
   33.88 +#define platform_send_ipi		sn2_send_IPI
   33.89 +#define platform_timer_interrupt	sn_timer_interrupt
   33.90 +#define platform_global_tlb_purge       sn2_global_tlb_purge
   33.91 +#define platform_tlb_migrate_finish	sn_tlb_migrate_finish
   33.92 +#define platform_pci_fixup		sn_pci_fixup
   33.93 +#define platform_inb			__sn_inb
   33.94 +#define platform_inw			__sn_inw
   33.95 +#define platform_inl			__sn_inl
   33.96 +#define platform_outb			__sn_outb
   33.97 +#define platform_outw			__sn_outw
   33.98 +#define platform_outl			__sn_outl
   33.99 +#define platform_mmiowb			__sn_mmiowb
  33.100 +#define platform_readb			__sn_readb
  33.101 +#define platform_readw			__sn_readw
  33.102 +#define platform_readl			__sn_readl
  33.103 +#define platform_readq			__sn_readq
  33.104 +#define platform_readb_relaxed		__sn_readb_relaxed
  33.105 +#define platform_readw_relaxed		__sn_readw_relaxed
  33.106 +#define platform_readl_relaxed		__sn_readl_relaxed
  33.107 +#define platform_readq_relaxed		__sn_readq_relaxed
  33.108 +#define platform_local_vector_to_irq	sn_local_vector_to_irq
  33.109 +#define platform_pci_get_legacy_mem	sn_pci_get_legacy_mem
  33.110 +#define platform_pci_legacy_read	sn_pci_legacy_read
  33.111 +#define platform_pci_legacy_write	sn_pci_legacy_write
  33.112 +#define platform_dma_init		machvec_noop
  33.113 +#define platform_dma_alloc_coherent	sn_dma_alloc_coherent
  33.114 +#define platform_dma_free_coherent	sn_dma_free_coherent
  33.115 +#define platform_dma_map_single		sn_dma_map_single
  33.116 +#define platform_dma_unmap_single	sn_dma_unmap_single
  33.117 +#define platform_dma_map_sg		sn_dma_map_sg
  33.118 +#define platform_dma_unmap_sg		sn_dma_unmap_sg
  33.119 +#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
  33.120 +#define platform_dma_sync_sg_for_cpu	sn_dma_sync_sg_for_cpu
  33.121 +#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
  33.122 +#define platform_dma_sync_sg_for_device	sn_dma_sync_sg_for_device
  33.123 +#define platform_dma_mapping_error		sn_dma_mapping_error
  33.124 +#define platform_dma_supported		sn_dma_supported
  33.125 +#define platform_migrate		sn_migrate
  33.126 +#ifdef CONFIG_PCI_MSI
  33.127 +#define platform_setup_msi_irq		sn_setup_msi_irq
  33.128 +#define platform_teardown_msi_irq	sn_teardown_msi_irq
  33.129 +#else
  33.130 +#define platform_setup_msi_irq		((ia64_mv_setup_msi_irq_t*)NULL)
  33.131 +#define platform_teardown_msi_irq	((ia64_mv_teardown_msi_irq_t*)NULL)
  33.132 +#endif
  33.133 +
  33.134 +#include <asm/sn/io.h>
  33.135 +
  33.136 +#endif /* _ASM_IA64_MACHVEC_SN2_H */
    34.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    34.2 +++ b/xen/include/asm-ia64/linux-xen/asm/pci.h	Wed Dec 13 11:08:40 2006 -0700
    34.3 @@ -0,0 +1,174 @@
    34.4 +#ifndef _ASM_IA64_PCI_H
    34.5 +#define _ASM_IA64_PCI_H
    34.6 +
    34.7 +#include <linux/mm.h>
    34.8 +#include <linux/slab.h>
    34.9 +#include <linux/spinlock.h>
   34.10 +#include <linux/string.h>
   34.11 +#include <linux/types.h>
   34.12 +
   34.13 +#include <asm/io.h>
   34.14 +#include <asm/scatterlist.h>
   34.15 +
   34.16 +/*
   34.17 + * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
   34.18 + * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
   34.19 + * loader.
   34.20 + */
   34.21 +#define pcibios_assign_all_busses()     0
   34.22 +#define pcibios_scan_all_fns(a, b)	0
   34.23 +
   34.24 +#define PCIBIOS_MIN_IO		0x1000
   34.25 +#define PCIBIOS_MIN_MEM		0x10000000
   34.26 +
   34.27 +void pcibios_config_init(void);
   34.28 +
   34.29 +struct pci_dev;
   34.30 +
   34.31 +/*
   34.32 + * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence
   34.33 + * between device bus addresses and CPU physical addresses.  Platforms with a hardware I/O
   34.34 + * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and
   34.35 + * network device layers.  Platforms with separate bus address spaces _must_ turn this off
   34.36 + * and provide a device DMA mapping implementation that takes care of the necessary
   34.37 + * address translation.
   34.38 + *
   34.39 + * For now, the ia64 platforms which may have separate/multiple bus address spaces all
   34.40 + * have I/O MMUs which support the merging of physically discontiguous buffers, so we can
   34.41 + * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS.
   34.42 + */
   34.43 +extern unsigned long ia64_max_iommu_merge_mask;
   34.44 +#define PCI_DMA_BUS_IS_PHYS	(ia64_max_iommu_merge_mask == ~0UL)
   34.45 +
   34.46 +static inline void
   34.47 +pcibios_set_master (struct pci_dev *dev)
   34.48 +{
   34.49 +	/* No special bus mastering setup handling */
   34.50 +}
   34.51 +
   34.52 +static inline void
   34.53 +pcibios_penalize_isa_irq (int irq, int active)
   34.54 +{
   34.55 +	/* We don't do dynamic PCI IRQ allocation */
   34.56 +}
   34.57 +
   34.58 +#define HAVE_ARCH_PCI_MWI 1
   34.59 +extern int pcibios_prep_mwi (struct pci_dev *);
   34.60 +
   34.61 +#include <asm-generic/pci-dma-compat.h>
   34.62 +
   34.63 +/* pci_unmap_{single,page} is not a nop, thus... */
   34.64 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
   34.65 +	dma_addr_t ADDR_NAME;
   34.66 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
   34.67 +	__u32 LEN_NAME;
   34.68 +#define pci_unmap_addr(PTR, ADDR_NAME)			\
   34.69 +	((PTR)->ADDR_NAME)
   34.70 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
   34.71 +	(((PTR)->ADDR_NAME) = (VAL))
   34.72 +#define pci_unmap_len(PTR, LEN_NAME)			\
   34.73 +	((PTR)->LEN_NAME)
   34.74 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
   34.75 +	(((PTR)->LEN_NAME) = (VAL))
   34.76 +
   34.77 +/* The ia64 platform always supports 64-bit addressing. */
   34.78 +#define pci_dac_dma_supported(pci_dev, mask)		(1)
   34.79 +#define pci_dac_page_to_dma(dev,pg,off,dir)		((dma_addr_t) page_to_bus(pg) + (off))
   34.80 +#define pci_dac_dma_to_page(dev,dma_addr)		(virt_to_page(bus_to_virt(dma_addr)))
   34.81 +#define pci_dac_dma_to_offset(dev,dma_addr)		offset_in_page(dma_addr)
   34.82 +#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir)	do { } while (0)
   34.83 +#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir)	do { mb(); } while (0)
   34.84 +
   34.85 +#define sg_dma_len(sg)		((sg)->dma_length)
   34.86 +#define sg_dma_address(sg)	((sg)->dma_address)
   34.87 +
   34.88 +#ifdef CONFIG_PCI
   34.89 +static inline void pci_dma_burst_advice(struct pci_dev *pdev,
   34.90 +					enum pci_dma_burst_strategy *strat,
   34.91 +					unsigned long *strategy_parameter)
   34.92 +{
   34.93 +	unsigned long cacheline_size;
   34.94 +	u8 byte;
   34.95 +
   34.96 +	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
   34.97 +	if (byte == 0)
   34.98 +		cacheline_size = 1024;
   34.99 +	else
  34.100 +		cacheline_size = (int) byte * 4;
  34.101 +
  34.102 +	*strat = PCI_DMA_BURST_MULTIPLE;
  34.103 +	*strategy_parameter = cacheline_size;
  34.104 +}
  34.105 +#endif
  34.106 +
  34.107 +#define HAVE_PCI_MMAP
  34.108 +extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  34.109 +				enum pci_mmap_state mmap_state, int write_combine);
  34.110 +#define HAVE_PCI_LEGACY
  34.111 +extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  34.112 +				      struct vm_area_struct *vma);
  34.113 +extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off,
  34.114 +				  size_t count);
  34.115 +extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off,
  34.116 +				   size_t count);
  34.117 +extern int pci_mmap_legacy_mem(struct kobject *kobj,
  34.118 +			       struct bin_attribute *attr,
  34.119 +			       struct vm_area_struct *vma);
  34.120 +
  34.121 +#define pci_get_legacy_mem platform_pci_get_legacy_mem
  34.122 +#define pci_legacy_read platform_pci_legacy_read
  34.123 +#define pci_legacy_write platform_pci_legacy_write
  34.124 +
  34.125 +struct pci_window {
  34.126 +	struct resource resource;
  34.127 +	u64 offset;
  34.128 +};
  34.129 +
  34.130 +struct pci_controller {
  34.131 +	void *acpi_handle;
  34.132 +	void *iommu;
  34.133 +	int segment;
  34.134 +	int node;		/* nearest node with memory or -1 for global allocation */
  34.135 +
  34.136 +	unsigned int windows;
  34.137 +	struct pci_window *window;
  34.138 +
  34.139 +	void *platform_data;
  34.140 +};
  34.141 +
  34.142 +#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
  34.143 +#define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
  34.144 +
  34.145 +extern struct pci_ops pci_root_ops;
  34.146 +
  34.147 +static inline int pci_proc_domain(struct pci_bus *bus)
  34.148 +{
  34.149 +	return (pci_domain_nr(bus) != 0);
  34.150 +}
  34.151 +
  34.152 +static inline void pcibios_add_platform_entries(struct pci_dev *dev)
  34.153 +{
  34.154 +}
  34.155 +
  34.156 +extern void pcibios_resource_to_bus(struct pci_dev *dev,
  34.157 +		struct pci_bus_region *region, struct resource *res);
  34.158 +
  34.159 +extern void pcibios_bus_to_resource(struct pci_dev *dev,
  34.160 +		struct resource *res, struct pci_bus_region *region);
  34.161 +
  34.162 +static inline struct resource *
  34.163 +pcibios_select_root(struct pci_dev *pdev, struct resource *res)
  34.164 +{
  34.165 +	struct resource *root = NULL;
  34.166 +
  34.167 +	if (res->flags & IORESOURCE_IO)
  34.168 +		root = &ioport_resource;
  34.169 +	if (res->flags & IORESOURCE_MEM)
  34.170 +		root = &iomem_resource;
  34.171 +
  34.172 +	return root;
  34.173 +}
  34.174 +
  34.175 +#define pcibios_scan_all_fns(a, b)	0
  34.176 +
  34.177 +#endif /* _ASM_IA64_PCI_H */
    35.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    35.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/README.origin	Wed Dec 13 11:08:40 2006 -0700
    35.3 @@ -0,0 +1,16 @@
    35.4 +# Source files in this directory are near-identical copies of linux-2.6.19
    35.5 +# files:
    35.6 +
    35.7 +# NOTE: ALL changes to these files should be clearly marked
    35.8 +# (e.g. with #ifdef XEN or XEN in a comment) so that they can be
    35.9 +# easily updated to future versions of the corresponding Linux files.
   35.10 +
   35.11 +addrs.h			-> linux/include/asm-ia64/sn/addrs.h
   35.12 +arch.h			-> linux/include/asm-ia64/sn/arch.h
   35.13 +hubdev.h		-> linux/arch/ia64/sn/include/xtalk/hubdev.h
   35.14 +intr.h			-> linux/include/asm-ia64/sn/intr.h
   35.15 +io.h			-> linux/include/asm-ia64/sn/io.h
   35.16 +nodepda.h		-> linux/include/asm-ia64/sn/nodepda.h
   35.17 +pcibr_provider.h	-> linux/include/asm-ia64/sn/pcibr_provider.h
   35.18 +rw_mmr.h		-> linux/include/asm-ia64/sn/rw_mmr.h
   35.19 +types.h			-> linux/include/asm-ia64/sn/types.h
    36.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    36.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/addrs.h	Wed Dec 13 11:08:40 2006 -0700
    36.3 @@ -0,0 +1,299 @@
    36.4 +/*
    36.5 + * This file is subject to the terms and conditions of the GNU General Public
    36.6 + * License.  See the file "COPYING" in the main directory of this archive
    36.7 + * for more details.
    36.8 + *
    36.9 + * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
   36.10 + */
   36.11 +
   36.12 +#ifndef _ASM_IA64_SN_ADDRS_H
   36.13 +#define _ASM_IA64_SN_ADDRS_H
   36.14 +
   36.15 +#include <asm/percpu.h>
   36.16 +#include <asm/sn/types.h>
   36.17 +#include <asm/sn/arch.h>
   36.18 +#include <asm/sn/pda.h>
   36.19 +
   36.20 +/*
   36.21 + *  Memory/SHUB Address Format:
   36.22 + *  +-+---------+--+--------------+
   36.23 + *  |0|  NASID  |AS| NodeOffset   |
   36.24 + *  +-+---------+--+--------------+
   36.25 + *
   36.26 + *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
   36.27 + *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
   36.28 + *     00: Local Resources and MMR space
   36.29 + *           Top bit of NodeOffset
   36.30 + *               0: Local resources space
   36.31 + *                  node id:
   36.32 + *                        0: IA64/NT compatibility space
   36.33 + *                        2: Local MMR Space
   36.34 + *                        4: Local memory, regardless of local node id
   36.35 + *               1: Global MMR space
   36.36 + *     01: GET space.
   36.37 + *     10: AMO space.
   36.38 + *     11: Cacheable memory space.
   36.39 + *
   36.40 + *   NodeOffset: byte offset
   36.41 + *
   36.42 + *
   36.43 + *  TIO address format:
   36.44 + *  +-+----------+--+--------------+
   36.45 + *  |0|  NASID   |AS| Nodeoffset   |
   36.46 + *  +-+----------+--+--------------+
   36.47 + *
   36.48 + *  NASID: (low NASID bit is 1) TIO
   36.49 + *   AS: 2-bit Chiplet Identifier
   36.50 + *     00: TIO LB (Indicates TIO MMR access.)
   36.51 + *     01: TIO ICE (indicates coretalk space access.)
   36.52 + * 
   36.53 + *   NodeOffset: top bit must be set.
   36.54 + *
   36.55 + *
   36.56 + * Note that in both of the above address formats, the low
   36.57 + * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
   36.58 + */
   36.59 +
   36.60 +
   36.61 +/*
   36.62 + * Define basic shift & mask constants for manipulating NASIDs and AS values.
   36.63 + */
   36.64 +#define NASID_BITMASK		(sn_hub_info->nasid_bitmask)
   36.65 +#define NASID_SHIFT		(sn_hub_info->nasid_shift)
   36.66 +#define AS_SHIFT		(sn_hub_info->as_shift)
   36.67 +#define AS_BITMASK		0x3UL
   36.68 +
   36.69 +#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
   36.70 +#define AS_MASK			((u64)AS_BITMASK << AS_SHIFT)
   36.71 +
   36.72 +
   36.73 +/*
   36.74 + * AS values. These are the same on both SHUB1 & SHUB2.
   36.75 + */
   36.76 +#define AS_GET_VAL		1UL
   36.77 +#define AS_AMO_VAL		2UL
   36.78 +#define AS_CAC_VAL		3UL
   36.79 +#define AS_GET_SPACE		(AS_GET_VAL << AS_SHIFT)
   36.80 +#define AS_AMO_SPACE		(AS_AMO_VAL << AS_SHIFT)
   36.81 +#define AS_CAC_SPACE		(AS_CAC_VAL << AS_SHIFT)
   36.82 +
   36.83 +
   36.84 +/* 
   36.85 + * Virtual Mode Local & Global MMR space.  
   36.86 + */
   36.87 +#define SH1_LOCAL_MMR_OFFSET	0x8000000000UL
   36.88 +#define SH2_LOCAL_MMR_OFFSET	0x0200000000UL
   36.89 +#define LOCAL_MMR_OFFSET	(is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
   36.90 +#define LOCAL_MMR_SPACE		(__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
   36.91 +#define LOCAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
   36.92 +
   36.93 +#define SH1_GLOBAL_MMR_OFFSET	0x0800000000UL
   36.94 +#define SH2_GLOBAL_MMR_OFFSET	0x0300000000UL
   36.95 +#define GLOBAL_MMR_OFFSET	(is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
   36.96 +#define GLOBAL_MMR_SPACE	(__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
   36.97 +
   36.98 +/*
   36.99 + * Physical mode addresses
  36.100 + */
  36.101 +#define GLOBAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
  36.102 +
  36.103 +
  36.104 +/*
  36.105 + * Clear region & AS bits.
  36.106 + */
  36.107 +#define TO_PHYS_MASK		(~(RGN_BITS | AS_MASK))
  36.108 +
  36.109 +
  36.110 +/*
  36.111 + * Misc NASID manipulation.
  36.112 + */
  36.113 +#define NASID_SPACE(n)		((u64)(n) << NASID_SHIFT)
  36.114 +#define REMOTE_ADDR(n,a)	(NASID_SPACE(n) | (a))
  36.115 +#define NODE_OFFSET(x)		((x) & (NODE_ADDRSPACE_SIZE - 1))
  36.116 +#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
  36.117 +#define NASID_GET(x)		(int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
  36.118 +#define LOCAL_MMR_ADDR(a)	(LOCAL_MMR_SPACE | (a))
  36.119 +#define GLOBAL_MMR_ADDR(n,a)	(GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
  36.120 +#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
  36.121 +#define GLOBAL_CAC_ADDR(n,a)	(CAC_BASE | REMOTE_ADDR(n,a))
  36.122 +#define CHANGE_NASID(n,x)	((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
  36.123 +#define IS_TIO_NASID(n)		((n) & 1)
  36.124 +
  36.125 +
  36.126 +/* non-II mmr's start at top of big window space (4G) */
  36.127 +#define BWIN_TOP		0x0000000100000000UL
  36.128 +
  36.129 +/*
  36.130 + * general address defines
  36.131 + */
  36.132 +#define CAC_BASE		(PAGE_OFFSET | AS_CAC_SPACE)
  36.133 +#define AMO_BASE		(__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
  36.134 +#define AMO_PHYS_BASE		(RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
  36.135 +#define GET_BASE		(PAGE_OFFSET | AS_GET_SPACE)
  36.136 +
  36.137 +/*
  36.138 + * Convert Memory addresses between various addressing modes.
  36.139 + */
  36.140 +#define TO_PHYS(x)		(TO_PHYS_MASK & (x))
  36.141 +#define TO_CAC(x)		(CAC_BASE     | TO_PHYS(x))
  36.142 +#ifdef CONFIG_SGI_SN
  36.143 +#define TO_AMO(x)		(AMO_BASE     | TO_PHYS(x))
  36.144 +#define TO_GET(x)		(GET_BASE     | TO_PHYS(x))
  36.145 +#else
  36.146 +#define TO_AMO(x)		({ BUG(); x; })
  36.147 +#define TO_GET(x)		({ BUG(); x; })
  36.148 +#endif
  36.149 +
  36.150 +/*
  36.151 + * Covert from processor physical address to II/TIO physical address:
  36.152 + *	II - squeeze out the AS bits
  36.153 + *	TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
  36.154 + *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
  36.155 + *           to insert a chiplet id into this macro.  However, it is our belief
  36.156 + *           right now that this chiplet id will be ICE, which is also zero.
  36.157 + */
  36.158 +#define SH1_TIO_PHYS_TO_DMA(x) 						\
  36.159 +	((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
  36.160 +
  36.161 +#define SH2_NETWORK_BANK_OFFSET(x) 					\
  36.162 +        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
  36.163 +
  36.164 +#define SH2_NETWORK_BANK_SELECT(x) 					\
  36.165 +        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))	\
  36.166 +        	>> (sn_hub_info->nasid_shift - 4)) << 36)
  36.167 +
  36.168 +#define SH2_NETWORK_ADDRESS(x) 						\
  36.169 +	(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
  36.170 +
  36.171 +#define SH2_TIO_PHYS_TO_DMA(x) 						\
  36.172 +        (((u64)(NASID_GET(x)) << 40) | 	SH2_NETWORK_ADDRESS(x))
  36.173 +
  36.174 +#define PHYS_TO_TIODMA(x)						\
  36.175 +	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
  36.176 +
  36.177 +#define PHYS_TO_DMA(x)							\
  36.178 +	((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
  36.179 +
  36.180 +
  36.181 +/*
  36.182 + * Macros to test for address type.
  36.183 + */
  36.184 +#define IS_AMO_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
  36.185 +#define IS_AMO_PHYS_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
  36.186 +
  36.187 +
  36.188 +/*
  36.189 + * The following definitions pertain to the IO special address
  36.190 + * space.  They define the location of the big and little windows
  36.191 + * of any given node.
  36.192 + */
  36.193 +#define BWIN_SIZE_BITS			29	/* big window size: 512M */
  36.194 +#define TIO_BWIN_SIZE_BITS		30	/* big window size: 1G */
  36.195 +#define NODE_SWIN_BASE(n, w)		((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
  36.196 +		: RAW_NODE_SWIN_BASE(n, w))
  36.197 +#define TIO_SWIN_BASE(n, w) 		(TIO_IO_BASE(n) + \
  36.198 +					    ((u64) (w) << TIO_SWIN_SIZE_BITS))
  36.199 +#define NODE_IO_BASE(n)			(GLOBAL_MMR_SPACE | NASID_SPACE(n))
  36.200 +#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
  36.201 +#define BWIN_SIZE			(1UL << BWIN_SIZE_BITS)
  36.202 +#define NODE_BWIN_BASE0(n)		(NODE_IO_BASE(n) + BWIN_SIZE)
  36.203 +#define NODE_BWIN_BASE(n, w)		(NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
  36.204 +#define RAW_NODE_SWIN_BASE(n, w)	(NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
  36.205 +#define BWIN_WIDGET_MASK		0x7
  36.206 +#define BWIN_WINDOWNUM(x)		(((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
  36.207 +#define SH1_IS_BIG_WINDOW_ADDR(x)	((x) & BWIN_TOP)
  36.208 +
  36.209 +#define TIO_BWIN_WINDOW_SELECT_MASK	0x7
  36.210 +#define TIO_BWIN_WINDOWNUM(x)		(((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
  36.211 +
  36.212 +#define TIO_HWIN_SHIFT_BITS		33
  36.213 +#define TIO_HWIN(x)			(NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
  36.214 +
  36.215 +/*
  36.216 + * The following definitions pertain to the IO special address
  36.217 + * space.  They define the location of the big and little windows
  36.218 + * of any given node.
  36.219 + */
  36.220 +
  36.221 +#define SWIN_SIZE_BITS			24
  36.222 +#define	SWIN_WIDGET_MASK		0xF
  36.223 +
  36.224 +#define TIO_SWIN_SIZE_BITS		28
  36.225 +#define TIO_SWIN_SIZE			(1UL << TIO_SWIN_SIZE_BITS)
  36.226 +#define TIO_SWIN_WIDGET_MASK		0x3
  36.227 +
  36.228 +/*
  36.229 + * Convert smallwindow address to xtalk address.
  36.230 + *
  36.231 + * 'addr' can be physical or virtual address, but will be converted
  36.232 + * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
  36.233 + */
  36.234 +#define	SWIN_WIDGETNUM(x)		(((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
  36.235 +#define TIO_SWIN_WIDGETNUM(x)		(((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
  36.236 +
  36.237 +
  36.238 +/*
  36.239 + * The following macros produce the correct base virtual address for
  36.240 + * the hub registers. The REMOTE_HUB_* macro produce
  36.241 + * the address for the specified hub's registers.  The intent is
  36.242 + * that the appropriate PI, MD, NI, or II register would be substituted
  36.243 + * for x.
  36.244 + *
  36.245 + *   WARNING:
  36.246 + *	When certain Hub chip workaround are defined, it's not sufficient
  36.247 + *	to dereference the *_HUB_ADDR() macros.  You should instead use
  36.248 + *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
  36.249 + *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  36.250 + *	They're always safe.
  36.251 + */
  36.252 +/* Shub1 TIO & MMR addressing macros */
  36.253 +#define SH1_TIO_IOSPACE_ADDR(n,x)					\
  36.254 +	GLOBAL_MMR_ADDR(n,x)
  36.255 +
  36.256 +#define SH1_REMOTE_BWIN_MMR(n,x)					\
  36.257 +	GLOBAL_MMR_ADDR(n,x)
  36.258 +
  36.259 +#define SH1_REMOTE_SWIN_MMR(n,x)					\
  36.260 +	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
  36.261 +
  36.262 +#define SH1_REMOTE_MMR(n,x)						\
  36.263 +	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :		\
  36.264 +	 	SH1_REMOTE_SWIN_MMR(n,x))
  36.265 +
  36.266 +/* Shub1 TIO & MMR addressing macros */
  36.267 +#define SH2_TIO_IOSPACE_ADDR(n,x)					\
  36.268 +	((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
  36.269 +
  36.270 +#define SH2_REMOTE_MMR(n,x)						\
  36.271 +	GLOBAL_MMR_ADDR(n,x)
  36.272 +
  36.273 +
  36.274 +/* TIO & MMR addressing macros that work on both shub1 & shub2 */
  36.275 +#define TIO_IOSPACE_ADDR(n,x)						\
  36.276 +	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :		\
  36.277 +		 SH2_TIO_IOSPACE_ADDR(n,x)))
  36.278 +
  36.279 +#define SH_REMOTE_MMR(n,x)						\
  36.280 +	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
  36.281 +
  36.282 +#define REMOTE_HUB_ADDR(n,x)						\
  36.283 +	(IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :	\
  36.284 +	 ((volatile u64*)SH_REMOTE_MMR(n,x)))
  36.285 +
  36.286 +
  36.287 +#define HUB_L(x)			(*((volatile typeof(*x) *)x))
  36.288 +#define	HUB_S(x,d)			(*((volatile typeof(*x) *)x) = (d))
  36.289 +
  36.290 +#define REMOTE_HUB_L(n, a)		HUB_L(REMOTE_HUB_ADDR((n), (a)))
  36.291 +#define REMOTE_HUB_S(n, a, d)		HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
  36.292 +
  36.293 +/*
  36.294 + * Coretalk address breakdown
  36.295 + */
  36.296 +#define CTALK_NASID_SHFT		40
  36.297 +#define CTALK_NASID_MASK		(0x3FFFULL << CTALK_NASID_SHFT)
  36.298 +#define CTALK_CID_SHFT			38
  36.299 +#define CTALK_CID_MASK			(0x3ULL << CTALK_CID_SHFT)
  36.300 +#define CTALK_NODE_OFFSET		0x3FFFFFFFFF
  36.301 +
  36.302 +#endif /* _ASM_IA64_SN_ADDRS_H */
    37.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    37.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/arch.h	Wed Dec 13 11:08:40 2006 -0700
    37.3 @@ -0,0 +1,85 @@
    37.4 +/*
    37.5 + * This file is subject to the terms and conditions of the GNU General Public
    37.6 + * License.  See the file "COPYING" in the main directory of this archive
    37.7 + * for more details.
    37.8 + *
    37.9 + * SGI specific setup.
   37.10 + *
   37.11 + * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
   37.12 + * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
   37.13 + */
   37.14 +#ifndef _ASM_IA64_SN_ARCH_H
   37.15 +#define _ASM_IA64_SN_ARCH_H
   37.16 +
   37.17 +#include <linux/numa.h>
   37.18 +#include <asm/types.h>
   37.19 +#include <asm/percpu.h>
   37.20 +#include <asm/sn/types.h>
   37.21 +#include <asm/sn/sn_cpuid.h>
   37.22 +
   37.23 +/*
   37.24 + * This is the maximum number of NUMALINK nodes that can be part of a single
   37.25 + * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
   37.26 + * remote partitions are NOT included in this number.
   37.27 + * The number of compact nodes cannot exceed size of a coherency domain.
   37.28 + * The purpose of this define is to specify a node count that includes
   37.29 + * all C/M/TIO nodes in an SSI system.
   37.30 + *
   37.31 + * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
   37.32 + *
   37.33 + * 	Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
   37.34 + * 	to ACPI3.0, this limit will be removed. The notion of "compact nodes"
   37.35 + * 	should be deleted and TIOs should be included in MAX_NUMNODES.
   37.36 + */
   37.37 +#define MAX_TIO_NODES		MAX_NUMNODES
   37.38 +#define MAX_COMPACT_NODES	(MAX_NUMNODES + MAX_TIO_NODES)
   37.39 +
   37.40 +/*
   37.41 + * Maximum number of nodes in all partitions and in all coherency domains.
   37.42 + * This is the total number of nodes accessible in the numalink fabric. It
   37.43 + * includes all C & M bricks, plus all TIOs.
   37.44 + *
   37.45 + * This value is also the value of the maximum number of NASIDs in the numalink
   37.46 + * fabric.
   37.47 + */
   37.48 +#define MAX_NUMALINK_NODES	16384
   37.49 +
   37.50 +/*
   37.51 + * The following defines attributes of the HUB chip. These attributes are
   37.52 + * frequently referenced. They are kept in the per-cpu data areas of each cpu.
   37.53 + * They are kept together in a struct to minimize cache misses.
   37.54 + */
   37.55 +struct sn_hub_info_s {
   37.56 +	u8 shub2;
   37.57 +	u8 nasid_shift;
   37.58 +	u8 as_shift;
   37.59 +	u8 shub_1_1_found;
   37.60 +	u16 nasid_bitmask;
   37.61 +};
   37.62 +DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
   37.63 +#define sn_hub_info 	(&__get_cpu_var(__sn_hub_info))
   37.64 +#define is_shub2()	(sn_hub_info->shub2)
   37.65 +#define is_shub1()	(sn_hub_info->shub2 == 0)
   37.66 +
   37.67 +/*
   37.68 + * Use this macro to test if shub 1.1 wars should be enabled
   37.69 + */
   37.70 +#define enable_shub_wars_1_1()	(sn_hub_info->shub_1_1_found)
   37.71 +
   37.72 +
   37.73 +/*
   37.74 + * Compact node ID to nasid mappings kept in the per-cpu data areas of each
   37.75 + * cpu.
   37.76 + */
   37.77 +DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
   37.78 +#define sn_cnodeid_to_nasid	(&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
   37.79 +
   37.80 +
   37.81 +extern u8 sn_partition_id;
   37.82 +extern u8 sn_system_size;
   37.83 +extern u8 sn_sharing_domain_size;
   37.84 +extern u8 sn_region_size;
   37.85 +
   37.86 +extern void sn_flush_all_caches(long addr, long bytes);
   37.87 +
   37.88 +#endif /* _ASM_IA64_SN_ARCH_H */
    38.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    38.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/hubdev.h	Wed Dec 13 11:08:40 2006 -0700
    38.3 @@ -0,0 +1,91 @@
    38.4 +/*
    38.5 + * This file is subject to the terms and conditions of the GNU General Public
    38.6 + * License.  See the file "COPYING" in the main directory of this archive
    38.7 + * for more details.
    38.8 + *
    38.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   38.10 + */
   38.11 +#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
   38.12 +#define _ASM_IA64_SN_XTALK_HUBDEV_H
   38.13 +
   38.14 +#include "xtalk/xwidgetdev.h"
   38.15 +
   38.16 +#define HUB_WIDGET_ID_MAX 0xf
   38.17 +#define DEV_PER_WIDGET (2*2*8)
   38.18 +#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
   38.19 +#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
   38.20 +#define IIO_ITTE_WIDGET_SHIFT   8
   38.21 +
   38.22 +#define IIO_ITTE_WIDGET(itte)	\
   38.23 +	(((itte) >> IIO_ITTE_WIDGET_SHIFT) & IIO_ITTE_WIDGET_MASK)
   38.24 +
   38.25 +/*
   38.26 + * Use the top big window as a surrogate for the first small window
   38.27 + */
   38.28 +#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
   38.29 +#define IIO_NUM_ITTES   7
   38.30 +#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
   38.31 +
   38.32 +/* This struct is shared between the PROM and the kernel.
   38.33 + * Changes to this struct will require corresponding changes to the kernel.
   38.34 + */
   38.35 +struct sn_flush_device_common {
   38.36 +	int sfdl_bus;
   38.37 +	int sfdl_slot;
   38.38 +	int sfdl_pin;
   38.39 +	struct common_bar_list {
   38.40 +		unsigned long start;
   38.41 +		unsigned long end;
   38.42 +	} sfdl_bar_list[6];
   38.43 +	unsigned long sfdl_force_int_addr;
   38.44 +	unsigned long sfdl_flush_value;
   38.45 +	volatile unsigned long *sfdl_flush_addr;
   38.46 +	u32 sfdl_persistent_busnum;
   38.47 +	u32 sfdl_persistent_segment;
   38.48 +	struct pcibus_info *sfdl_pcibus_info;
   38.49 +};
   38.50 +
   38.51 +/* This struct is kernel only and is not used by the PROM */
   38.52 +struct sn_flush_device_kernel {
   38.53 +	spinlock_t sfdl_flush_lock;
   38.54 +	struct sn_flush_device_common *common;
   38.55 +};
   38.56 +
   38.57 +/* 01/16/06 This struct is the old PROM/kernel struct and needs to be included
   38.58 + * for older official PROMs to function on the new kernel base.  This struct
   38.59 + * will be removed when the next official PROM release occurs. */
   38.60 +
   38.61 +struct sn_flush_device_war {
   38.62 +	struct sn_flush_device_common common;
   38.63 +	u32 filler; /* older PROMs expect the default size of a spinlock_t */
   38.64 +};
   38.65 +
   38.66 +/*
   38.67 + * **widget_p - Used as an array[wid_num][device] of sn_flush_device_kernel.
   38.68 + */
   38.69 +struct sn_flush_nasid_entry  {
   38.70 +	struct sn_flush_device_kernel **widget_p; // Used as an array of wid_num
   38.71 +	u64 iio_itte[8];
   38.72 +};
   38.73 +
   38.74 +struct hubdev_info {
   38.75 +	geoid_t				hdi_geoid;
   38.76 +	short				hdi_nasid;
   38.77 +	short				hdi_peer_nasid;   /* Dual Porting Peer */
   38.78 +
   38.79 +	struct sn_flush_nasid_entry	hdi_flush_nasid_list;
   38.80 +	struct xwidget_info		hdi_xwidget_info[HUB_WIDGET_ID_MAX + 1];
   38.81 +
   38.82 +
   38.83 +	void				*hdi_nodepda;
   38.84 +	void				*hdi_node_vertex;
   38.85 +	u32				max_segment_number;
   38.86 +	u32				max_pcibus_number;
   38.87 +};
   38.88 +
   38.89 +extern void hubdev_init_node(nodepda_t *, cnodeid_t);
   38.90 +extern void hub_error_init(struct hubdev_info *);
   38.91 +extern void ice_error_init(struct hubdev_info *);
   38.92 +
   38.93 +
   38.94 +#endif /* _ASM_IA64_SN_XTALK_HUBDEV_H */
    39.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    39.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/intr.h	Wed Dec 13 11:08:40 2006 -0700
    39.3 @@ -0,0 +1,67 @@
    39.4 +/*
    39.5 + * This file is subject to the terms and conditions of the GNU General Public
    39.6 + * License.  See the file "COPYING" in the main directory of this archive
    39.7 + * for more details.
    39.8 + *
    39.9 + * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
   39.10 + */
   39.11 +
   39.12 +#ifndef _ASM_IA64_SN_INTR_H
   39.13 +#define _ASM_IA64_SN_INTR_H
   39.14 +
   39.15 +#include <linux/rcupdate.h>
   39.16 +#include <asm/sn/types.h>
   39.17 +
   39.18 +#define SGI_UART_VECTOR		0xe9
   39.19 +
   39.20 +/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
   39.21 +#define SGI_XPC_ACTIVATE	0x30
   39.22 +#define SGI_II_ERROR		0x31
   39.23 +#define SGI_XBOW_ERROR		0x32
   39.24 +#define SGI_PCIASIC_ERROR	0x33
   39.25 +#define SGI_ACPI_SCI_INT	0x34
   39.26 +#define SGI_TIOCA_ERROR		0x35
   39.27 +#define SGI_TIO_ERROR		0x36
   39.28 +#define SGI_TIOCX_ERROR		0x37
   39.29 +#define SGI_MMTIMER_VECTOR	0x38
   39.30 +#define SGI_XPC_NOTIFY		0xe7
   39.31 +
   39.32 +#define IA64_SN2_FIRST_DEVICE_VECTOR	0x3c
   39.33 +#define IA64_SN2_LAST_DEVICE_VECTOR	0xe6
   39.34 +
   39.35 +#define SN2_IRQ_RESERVED	0x1
   39.36 +#define SN2_IRQ_CONNECTED	0x2
   39.37 +#define SN2_IRQ_SHARED		0x4
   39.38 +
   39.39 +// The SN PROM irq struct
   39.40 +struct sn_irq_info {
   39.41 +	struct sn_irq_info *irq_next;	/* deprecated DO NOT USE     */
   39.42 +	short		irq_nasid;	/* Nasid IRQ is assigned to  */
   39.43 +	int		irq_slice;	/* slice IRQ is assigned to  */
   39.44 +	int		irq_cpuid;	/* kernel logical cpuid	     */
   39.45 +	int		irq_irq;	/* the IRQ number */
   39.46 +	int		irq_int_bit;	/* Bridge interrupt pin */
   39.47 +					/* <0 means MSI */
   39.48 +	u64	irq_xtalkaddr;	/* xtalkaddr IRQ is sent to  */
   39.49 +	int		irq_bridge_type;/* pciio asic type (pciio.h) */
   39.50 +	void	       *irq_bridge;	/* bridge generating irq     */
   39.51 +	void	       *irq_pciioinfo;	/* associated pciio_info_t   */
   39.52 +	int		irq_last_intr;	/* For Shub lb lost intr WAR */
   39.53 +	int		irq_cookie;	/* unique cookie 	     */
   39.54 +	int		irq_flags;	/* flags */
   39.55 +	int		irq_share_cnt;	/* num devices sharing IRQ   */
   39.56 +	struct list_head	list;	/* list of sn_irq_info structs */
   39.57 +	struct rcu_head		rcu;	/* rcu callback list */
   39.58 +};
   39.59 +
   39.60 +extern void sn_send_IPI_phys(int, long, int, int);
   39.61 +extern u64 sn_intr_alloc(nasid_t, int,
   39.62 +			      struct sn_irq_info *,
   39.63 +			      int, nasid_t, int);
   39.64 +extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
   39.65 +extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
   39.66 +extern struct list_head **sn_irq_lh;
   39.67 +
   39.68 +#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
   39.69 +
   39.70 +#endif /* _ASM_IA64_SN_INTR_H */
    40.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    40.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/io.h	Wed Dec 13 11:08:40 2006 -0700
    40.3 @@ -0,0 +1,274 @@
    40.4 +/* 
    40.5 + * This file is subject to the terms and conditions of the GNU General Public
    40.6 + * License.  See the file "COPYING" in the main directory of this archive
    40.7 + * for more details.
    40.8 + *
    40.9 + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
   40.10 + */
   40.11 +
   40.12 +#ifndef _ASM_SN_IO_H
   40.13 +#define _ASM_SN_IO_H
   40.14 +#include <linux/compiler.h>
   40.15 +#include <asm/intrinsics.h>
   40.16 +
   40.17 +extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
   40.18 +extern void __sn_mmiowb(void); /* Forward definition */
   40.19 +
   40.20 +extern int num_cnodes;
   40.21 +
   40.22 +#define __sn_mf_a()   ia64_mfa()
   40.23 +
   40.24 +extern void sn_dma_flush(unsigned long);
   40.25 +
   40.26 +#define __sn_inb ___sn_inb
   40.27 +#define __sn_inw ___sn_inw
   40.28 +#define __sn_inl ___sn_inl
   40.29 +#define __sn_outb ___sn_outb
   40.30 +#define __sn_outw ___sn_outw
   40.31 +#define __sn_outl ___sn_outl
   40.32 +#define __sn_readb ___sn_readb
   40.33 +#define __sn_readw ___sn_readw
   40.34 +#define __sn_readl ___sn_readl
   40.35 +#define __sn_readq ___sn_readq
   40.36 +#define __sn_readb_relaxed ___sn_readb_relaxed
   40.37 +#define __sn_readw_relaxed ___sn_readw_relaxed
   40.38 +#define __sn_readl_relaxed ___sn_readl_relaxed
   40.39 +#define __sn_readq_relaxed ___sn_readq_relaxed
   40.40 +
   40.41 +/*
   40.42 + * Convenience macros for setting/clearing bits using the above accessors
   40.43 + */
   40.44 +
   40.45 +#define __sn_setq_relaxed(addr, val) \
   40.46 +	writeq((__sn_readq_relaxed(addr) | (val)), (addr))
   40.47 +#define __sn_clrq_relaxed(addr, val) \
   40.48 +	writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
   40.49 +
   40.50 +/*
   40.51 + * The following routines are SN Platform specific, called when
   40.52 + * a reference is made to inX/outX set macros.  SN Platform
   40.53 + * inX set of macros ensures that Posted DMA writes on the
   40.54 + * Bridge is flushed.
   40.55 + *
   40.56 + * The routines should be self explainatory.
   40.57 + */
   40.58 +
   40.59 +static inline unsigned int
   40.60 +___sn_inb (unsigned long port)
   40.61 +{
   40.62 +	volatile unsigned char *addr;
   40.63 +	unsigned char ret = -1;
   40.64 +
   40.65 +	if ((addr = sn_io_addr(port))) {
   40.66 +		ret = *addr;
   40.67 +		__sn_mf_a();
   40.68 +		sn_dma_flush((unsigned long)addr);
   40.69 +	}
   40.70 +	return ret;
   40.71 +}
   40.72 +
   40.73 +static inline unsigned int
   40.74 +___sn_inw (unsigned long port)
   40.75 +{
   40.76 +	volatile unsigned short *addr;
   40.77 +	unsigned short ret = -1;
   40.78 +
   40.79 +	if ((addr = sn_io_addr(port))) {
   40.80 +		ret = *addr;
   40.81 +		__sn_mf_a();
   40.82 +		sn_dma_flush((unsigned long)addr);
   40.83 +	}
   40.84 +	return ret;
   40.85 +}
   40.86 +
   40.87 +static inline unsigned int
   40.88 +___sn_inl (unsigned long port)
   40.89 +{
   40.90 +	volatile unsigned int *addr;
   40.91 +	unsigned int ret = -1;
   40.92 +
   40.93 +	if ((addr = sn_io_addr(port))) {
   40.94 +		ret = *addr;
   40.95 +		__sn_mf_a();
   40.96 +		sn_dma_flush((unsigned long)addr);
   40.97 +	}
   40.98 +	return ret;
   40.99 +}
  40.100 +
  40.101 +static inline void
  40.102 +___sn_outb (unsigned char val, unsigned long port)
  40.103 +{
  40.104 +	volatile unsigned char *addr;
  40.105 +
  40.106 +	if ((addr = sn_io_addr(port))) {
  40.107 +		*addr = val;
  40.108 +		__sn_mmiowb();
  40.109 +	}
  40.110 +}
  40.111 +
  40.112 +static inline void
  40.113 +___sn_outw (unsigned short val, unsigned long port)
  40.114 +{
  40.115 +	volatile unsigned short *addr;
  40.116 +
  40.117 +	if ((addr = sn_io_addr(port))) {
  40.118 +		*addr = val;
  40.119 +		__sn_mmiowb();
  40.120 +	}
  40.121 +}
  40.122 +
  40.123 +static inline void
  40.124 +___sn_outl (unsigned int val, unsigned long port)
  40.125 +{
  40.126 +	volatile unsigned int *addr;
  40.127 +
  40.128 +	if ((addr = sn_io_addr(port))) {
  40.129 +		*addr = val;
  40.130 +		__sn_mmiowb();
  40.131 +	}
  40.132 +}
  40.133 +
  40.134 +/*
  40.135 + * The following routines are SN Platform specific, called when 
  40.136 + * a reference is made to readX/writeX set macros.  SN Platform 
  40.137 + * readX set of macros ensures that Posted DMA writes on the 
  40.138 + * Bridge is flushed.
  40.139 + * 
  40.140 + * The routines should be self explainatory.
  40.141 + */
  40.142 +
  40.143 +static inline unsigned char
  40.144 +___sn_readb (const volatile void __iomem *addr)
  40.145 +{
  40.146 +	unsigned char val;
  40.147 +
  40.148 +	val = *(volatile unsigned char __force *)addr;
  40.149 +	__sn_mf_a();
  40.150 +	sn_dma_flush((unsigned long)addr);
  40.151 +        return val;
  40.152 +}
  40.153 +
  40.154 +static inline unsigned short
  40.155 +___sn_readw (const volatile void __iomem *addr)
  40.156 +{
  40.157 +	unsigned short val;
  40.158 +
  40.159 +	val = *(volatile unsigned short __force *)addr;
  40.160 +	__sn_mf_a();
  40.161 +	sn_dma_flush((unsigned long)addr);
  40.162 +        return val;
  40.163 +}
  40.164 +
  40.165 +static inline unsigned int
  40.166 +___sn_readl (const volatile void __iomem *addr)
  40.167 +{
  40.168 +	unsigned int val;
  40.169 +
  40.170 +	val = *(volatile unsigned int __force *)addr;
  40.171 +	__sn_mf_a();
  40.172 +	sn_dma_flush((unsigned long)addr);
  40.173 +        return val;
  40.174 +}
  40.175 +
  40.176 +static inline unsigned long
  40.177 +___sn_readq (const volatile void __iomem *addr)
  40.178 +{
  40.179 +	unsigned long val;
  40.180 +
  40.181 +	val = *(volatile unsigned long __force *)addr;
  40.182 +	__sn_mf_a();
  40.183 +	sn_dma_flush((unsigned long)addr);
  40.184 +        return val;
  40.185 +}
  40.186 +
  40.187 +/*
  40.188 + * For generic and SN2 kernels, we have a set of fast access
  40.189 + * PIO macros.	These macros are provided on SN Platform
  40.190 + * because the normal inX and readX macros perform an
  40.191 + * additional task of flushing Post DMA request on the Bridge.
  40.192 + *
  40.193 + * These routines should be self explainatory.
  40.194 + */
  40.195 +
  40.196 +static inline unsigned int
  40.197 +sn_inb_fast (unsigned long port)
  40.198 +{
  40.199 +	volatile unsigned char *addr = (unsigned char *)port;
  40.200 +	unsigned char ret;
  40.201 +
  40.202 +	ret = *addr;
  40.203 +	__sn_mf_a();
  40.204 +	return ret;
  40.205 +}
  40.206 +
  40.207 +static inline unsigned int
  40.208 +sn_inw_fast (unsigned long port)
  40.209 +{
  40.210 +	volatile unsigned short *addr = (unsigned short *)port;
  40.211 +	unsigned short ret;
  40.212 +
  40.213 +	ret = *addr;
  40.214 +	__sn_mf_a();
  40.215 +	return ret;
  40.216 +}
  40.217 +
  40.218 +static inline unsigned int
  40.219 +sn_inl_fast (unsigned long port)
  40.220 +{
  40.221 +	volatile unsigned int *addr = (unsigned int *)port;
  40.222 +	unsigned int ret;
  40.223 +
  40.224 +	ret = *addr;
  40.225 +	__sn_mf_a();
  40.226 +	return ret;
  40.227 +}
  40.228 +
  40.229 +static inline unsigned char
  40.230 +___sn_readb_relaxed (const volatile void __iomem *addr)
  40.231 +{
  40.232 +	return *(volatile unsigned char __force *)addr;
  40.233 +}
  40.234 +
  40.235 +static inline unsigned short
  40.236 +___sn_readw_relaxed (const volatile void __iomem *addr)
  40.237 +{
  40.238 +	return *(volatile unsigned short __force *)addr;
  40.239 +}
  40.240 +
  40.241 +static inline unsigned int
  40.242 +___sn_readl_relaxed (const volatile void __iomem *addr)
  40.243 +{
  40.244 +	return *(volatile unsigned int __force *) addr;
  40.245 +}
  40.246 +
  40.247 +static inline unsigned long
  40.248 +___sn_readq_relaxed (const volatile void __iomem *addr)
  40.249 +{
  40.250 +	return *(volatile unsigned long __force *) addr;
  40.251 +}
  40.252 +
  40.253 +struct pci_dev;
  40.254 +
  40.255 +static inline int
  40.256 +sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
  40.257 +{
  40.258 +
  40.259 +	if (vchan > 1) {
  40.260 +		return -1;
  40.261 +	}
  40.262 +
  40.263 +	if (!(*addr >> 32))	/* Using a mask here would be cleaner */
  40.264 +		return 0;	/* but this generates better code */
  40.265 +
  40.266 +	if (vchan == 1) {
  40.267 +		/* Set Bit 57 */
  40.268 +		*addr |= (1UL << 57);
  40.269 +	} else {
  40.270 +		/* Clear Bit 57 */
  40.271 +		*addr &= ~(1UL << 57);
  40.272 +	}
  40.273 +
  40.274 +	return 0;
  40.275 +}
  40.276 +
  40.277 +#endif	/* _ASM_SN_IO_H */
    41.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    41.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/nodepda.h	Wed Dec 13 11:08:40 2006 -0700
    41.3 @@ -0,0 +1,83 @@
    41.4 +/*
    41.5 + * This file is subject to the terms and conditions of the GNU General Public
    41.6 + * License.  See the file "COPYING" in the main directory of this archive
    41.7 + * for more details.
    41.8 + *
    41.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   41.10 + */
   41.11 +#ifndef _ASM_IA64_SN_NODEPDA_H
   41.12 +#define _ASM_IA64_SN_NODEPDA_H
   41.13 +
   41.14 +
   41.15 +#include <asm/semaphore.h>
   41.16 +#include <asm/irq.h>
   41.17 +#include <asm/sn/arch.h>
   41.18 +#include <asm/sn/intr.h>
   41.19 +#include <asm/sn/bte.h>
   41.20 +
   41.21 +/*
   41.22 + * NUMA Node-Specific Data structures are defined in this file.
   41.23 + * In particular, this is the location of the node PDA.
   41.24 + * A pointer to the right node PDA is saved in each CPU PDA.
   41.25 + */
   41.26 +
   41.27 +/*
   41.28 + * Node-specific data structure.
   41.29 + *
   41.30 + * One of these structures is allocated on each node of a NUMA system.
   41.31 + *
   41.32 + * This structure provides a convenient way of keeping together 
   41.33 + * all per-node data structures. 
   41.34 + */
   41.35 +struct phys_cpuid {
   41.36 +	short			nasid;
   41.37 +	char			subnode;
   41.38 +	char			slice;
   41.39 +};
   41.40 +
   41.41 +struct nodepda_s {
   41.42 +	void 		*pdinfo;	/* Platform-dependent per-node info */
   41.43 +
   41.44 +	/*
   41.45 +	 * The BTEs on this node are shared by the local cpus
   41.46 +	 */
   41.47 +	struct bteinfo_s	bte_if[MAX_BTES_PER_NODE];	/* Virtual Interface */
   41.48 +	struct timer_list	bte_recovery_timer;
   41.49 +	spinlock_t		bte_recovery_lock;
   41.50 +
   41.51 +	/* 
   41.52 +	 * Array of pointers to the nodepdas for each node.
   41.53 +	 */
   41.54 +	struct nodepda_s	*pernode_pdaindr[MAX_COMPACT_NODES]; 
   41.55 +
   41.56 +	/*
   41.57 +	 * Array of physical cpu identifiers. Indexed by cpuid.
   41.58 +	 */
   41.59 +	struct phys_cpuid	phys_cpuid[NR_CPUS];
   41.60 +	spinlock_t		ptc_lock ____cacheline_aligned_in_smp;
   41.61 +};
   41.62 +
   41.63 +typedef struct nodepda_s nodepda_t;
   41.64 +
   41.65 +/*
   41.66 + * Access Functions for node PDA.
   41.67 + * Since there is one nodepda for each node, we need a convenient mechanism
   41.68 + * to access these nodepdas without cluttering code with #ifdefs.
   41.69 + * The next set of definitions provides this.
   41.70 + * Routines are expected to use 
   41.71 + *
   41.72 + *	sn_nodepda   - to access node PDA for the node on which code is running
   41.73 + *	NODEPDA(cnodeid)   - to access node PDA for cnodeid
   41.74 + */
   41.75 +
   41.76 +DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
   41.77 +#define sn_nodepda		(__get_cpu_var(__sn_nodepda))
   41.78 +#define	NODEPDA(cnodeid)	(sn_nodepda->pernode_pdaindr[cnodeid])
   41.79 +
   41.80 +/*
   41.81 + * Check if given a compact node id the corresponding node has all the
   41.82 + * cpus disabled. 
   41.83 + */
   41.84 +#define is_headless_node(cnodeid)	(nr_cpus_node(cnodeid) == 0)
   41.85 +
   41.86 +#endif /* _ASM_IA64_SN_NODEPDA_H */
    42.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    42.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/pcibr_provider.h	Wed Dec 13 11:08:40 2006 -0700
    42.3 @@ -0,0 +1,149 @@
    42.4 +/*
    42.5 + * This file is subject to the terms and conditions of the GNU General Public
    42.6 + * License.  See the file "COPYING" in the main directory of this archive
    42.7 + * for more details.
    42.8 + *
    42.9 + * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
   42.10 + */
   42.11 +#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
   42.12 +#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
   42.13 +
   42.14 +#include <asm/sn/intr.h>
   42.15 +#include <asm/sn/pcibus_provider_defs.h>
   42.16 +
   42.17 +/* Workarounds */
   42.18 +#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
   42.19 +
   42.20 +#define BUSTYPE_MASK                    0x1
   42.21 +
   42.22 +/* Macros given a pcibus structure */
   42.23 +#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
   42.24 +#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
   42.25 +                asic == PCIIO_ASIC_TYPE_TIOCP)
   42.26 +#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
   42.27 +
   42.28 +
   42.29 +/*
   42.30 + * The different PCI Bridge types supported on the SGI Altix platforms
   42.31 + */
   42.32 +#define PCIBR_BRIDGETYPE_UNKNOWN       -1
   42.33 +#define PCIBR_BRIDGETYPE_PIC            2
   42.34 +#define PCIBR_BRIDGETYPE_TIOCP          3
   42.35 +
   42.36 +/*
   42.37 + * Bridge 64bit Direct Map Attributes
   42.38 + */
   42.39 +#define PCI64_ATTR_PREF                 (1ull << 59)
   42.40 +#define PCI64_ATTR_PREC                 (1ull << 58)
   42.41 +#define PCI64_ATTR_VIRTUAL              (1ull << 57)
   42.42 +#define PCI64_ATTR_BAR                  (1ull << 56)
   42.43 +#define PCI64_ATTR_SWAP                 (1ull << 55)
   42.44 +#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
   42.45 +
   42.46 +#define PCI32_LOCAL_BASE                0
   42.47 +#define PCI32_MAPPED_BASE               0x40000000
   42.48 +#define PCI32_DIRECT_BASE               0x80000000
   42.49 +
   42.50 +#define IS_PCI32_MAPPED(x)              ((u64)(x) < PCI32_DIRECT_BASE && \
   42.51 +                                         (u64)(x) >= PCI32_MAPPED_BASE)
   42.52 +#define IS_PCI32_DIRECT(x)              ((u64)(x) >= PCI32_MAPPED_BASE)
   42.53 +
   42.54 +
   42.55 +/*
   42.56 + * Bridge PMU Address Transaltion Entry Attibutes
   42.57 + */
   42.58 +#define PCI32_ATE_V                     (0x1 << 0)
   42.59 +#define PCI32_ATE_CO                    (0x1 << 1)
   42.60 +#define PCI32_ATE_PREC                  (0x1 << 2)
   42.61 +#define PCI32_ATE_MSI                   (0x1 << 2)
   42.62 +#define PCI32_ATE_PREF                  (0x1 << 3)
   42.63 +#define PCI32_ATE_BAR                   (0x1 << 4)
   42.64 +#define PCI32_ATE_ADDR_SHFT             12
   42.65 +
   42.66 +#define MINIMAL_ATES_REQUIRED(addr, size) \
   42.67 +	(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
   42.68 +
   42.69 +#define MINIMAL_ATE_FLAG(addr, size) \
   42.70 +	(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
   42.71 +
   42.72 +/* bit 29 of the pci address is the SWAP bit */
   42.73 +#define ATE_SWAPSHIFT                   29
   42.74 +#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
   42.75 +#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
   42.76 +
   42.77 +/*
   42.78 + * I/O page size
   42.79 + */
   42.80 +#if PAGE_SIZE < 16384
   42.81 +#define IOPFNSHIFT                      12      /* 4K per mapped page */
   42.82 +#else
   42.83 +#define IOPFNSHIFT                      14      /* 16K per mapped page */
   42.84 +#endif
   42.85 +
   42.86 +#define IOPGSIZE                        (1 << IOPFNSHIFT)
   42.87 +#define IOPG(x)                         ((x) >> IOPFNSHIFT)
   42.88 +#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
   42.89 +
   42.90 +#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
   42.91 +#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
   42.92 +
   42.93 +/*
   42.94 + * PMU resources.
   42.95 + */
   42.96 +struct ate_resource{
   42.97 +	u64 *ate;
   42.98 +	u64 num_ate;
   42.99 +	u64 lowest_free_index;
  42.100 +};
  42.101 +
  42.102 +struct pcibus_info {
  42.103 +	struct pcibus_bussoft	pbi_buscommon;   /* common header */
  42.104 +	u32                pbi_moduleid;
  42.105 +	short                   pbi_bridge_type;
  42.106 +	short                   pbi_bridge_mode;
  42.107 +
  42.108 +	struct ate_resource     pbi_int_ate_resource;
  42.109 +	u64                pbi_int_ate_size;
  42.110 +
  42.111 +	u64                pbi_dir_xbase;
  42.112 +	char                    pbi_hub_xid;
  42.113 +
  42.114 +	u64                pbi_devreg[8];
  42.115 +
  42.116 +	u32		pbi_valid_devices;
  42.117 +	u32		pbi_enabled_devices;
  42.118 +
  42.119 +	spinlock_t              pbi_lock;
  42.120 +};
  42.121 +
  42.122 +extern int  pcibr_init_provider(void);
  42.123 +extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
  42.124 +extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
  42.125 +extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
  42.126 +extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
  42.127 +
  42.128 +/*
  42.129 + * prototypes for the bridge asic register access routines in pcibr_reg.c
  42.130 + */
  42.131 +extern void             pcireg_control_bit_clr(struct pcibus_info *, u64);
  42.132 +extern void             pcireg_control_bit_set(struct pcibus_info *, u64);
  42.133 +extern u64         pcireg_tflush_get(struct pcibus_info *);
  42.134 +extern u64         pcireg_intr_status_get(struct pcibus_info *);
  42.135 +extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
  42.136 +extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
  42.137 +extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
  42.138 +extern void             pcireg_force_intr_set(struct pcibus_info *, int);
  42.139 +extern u64         pcireg_wrb_flush_get(struct pcibus_info *, int);
  42.140 +extern void             pcireg_int_ate_set(struct pcibus_info *, int, u64);
  42.141 +extern u64 __iomem *	pcireg_int_ate_addr(struct pcibus_info *, int);
  42.142 +extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
  42.143 +extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
  42.144 +extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
  42.145 +extern void 		pcibr_ate_free(struct pcibus_info *, int);
  42.146 +extern void 		ate_write(struct pcibus_info *, int, int, u64);
  42.147 +extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
  42.148 +				 void *resp);
  42.149 +extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
  42.150 +				  int action, void *resp);
  42.151 +extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
  42.152 +#endif
    43.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    43.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/rw_mmr.h	Wed Dec 13 11:08:40 2006 -0700
    43.3 @@ -0,0 +1,28 @@
    43.4 +/*
    43.5 + * This file is subject to the terms and conditions of the GNU General Public
    43.6 + * License.  See the file "COPYING" in the main directory of this archive
    43.7 + * for more details.
    43.8 + *
    43.9 + * Copyright (C) 2002-2006 Silicon Graphics, Inc.  All Rights Reserved.
   43.10 + */
   43.11 +#ifndef _ASM_IA64_SN_RW_MMR_H
   43.12 +#define _ASM_IA64_SN_RW_MMR_H
   43.13 +
   43.14 +
   43.15 +/*
   43.16 + * This file that access MMRs via uncached physical addresses.
   43.17 + * 	pio_phys_read_mmr  - read an MMR
   43.18 + * 	pio_phys_write_mmr - write an MMR
   43.19 + * 	pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
   43.20 + *		Second MMR will be skipped if address is NULL
   43.21 + *
   43.22 + * Addresses passed to these routines should be uncached physical addresses
   43.23 + * ie., 0x80000....
   43.24 + */
   43.25 +
   43.26 +
   43.27 +extern long pio_phys_read_mmr(volatile long *mmr); 
   43.28 +extern void pio_phys_write_mmr(volatile long *mmr, long val);
   43.29 +extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2); 
   43.30 +
   43.31 +#endif /* _ASM_IA64_SN_RW_MMR_H */
    44.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    44.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/types.h	Wed Dec 13 11:08:40 2006 -0700
    44.3 @@ -0,0 +1,26 @@
    44.4 +/*
    44.5 + * This file is subject to the terms and conditions of the GNU General Public
    44.6 + * License.  See the file "COPYING" in the main directory of this archive
    44.7 + * for more details.
    44.8 + *
    44.9 + * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc.  All Rights Reserved.
   44.10 + * Copyright (C) 1999 by Ralf Baechle
   44.11 + */
   44.12 +#ifndef _ASM_IA64_SN_TYPES_H
   44.13 +#define _ASM_IA64_SN_TYPES_H
   44.14 +
   44.15 +#include <linux/types.h>
   44.16 +
   44.17 +typedef unsigned long 	cpuid_t;
   44.18 +typedef signed short	nasid_t;	/* node id in numa-as-id space */
   44.19 +typedef signed char	partid_t;	/* partition ID type */
   44.20 +typedef unsigned int    moduleid_t;     /* user-visible module number type */
   44.21 +typedef unsigned int    cmoduleid_t;    /* kernel compact module id type */
   44.22 +typedef unsigned char	slotid_t;	/* slot (blade) within module */
   44.23 +typedef unsigned char	slabid_t;	/* slab (asic) within slot */
   44.24 +typedef u64 nic_t;
   44.25 +typedef unsigned long iopaddr_t;
   44.26 +typedef unsigned long paddr_t;
   44.27 +typedef short cnodeid_t;
   44.28 +
   44.29 +#endif /* _ASM_IA64_SN_TYPES_H */
    45.1 --- a/xen/include/asm-ia64/linux-xen/linux/README.origin	Tue Dec 12 15:25:02 2006 -0700
    45.2 +++ b/xen/include/asm-ia64/linux-xen/linux/README.origin	Wed Dec 13 11:08:40 2006 -0700
    45.3 @@ -12,3 +12,8 @@ interrupt.h 		-> linux/include/linux/int
    45.4  
    45.5  # The files below are from Linux-2.6.16.33
    45.6  oprofile.h		-> linux/include/linux/oprofile.h
    45.7 +
    45.8 +# The files below are from Linux-2.6.19
    45.9 +pci.h			-> linux/include/linux/pci.h
   45.10 +kobject.h		-> linux/include/linux/kobject.h
   45.11 +device.h		-> linux/include/linux/device.h
    46.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    46.2 +++ b/xen/include/asm-ia64/linux-xen/linux/device.h	Wed Dec 13 11:08:40 2006 -0700
    46.3 @@ -0,0 +1,473 @@
    46.4 +/*
    46.5 + * device.h - generic, centralized driver model
    46.6 + *
    46.7 + * Copyright (c) 2001-2003 Patrick Mochel <mochel@osdl.org>
    46.8 + *
    46.9 + * This file is released under the GPLv2
   46.10 + *
   46.11 + * See Documentation/driver-model/ for more information.
   46.12 + */
   46.13 +
   46.14 +#ifndef _DEVICE_H_
   46.15 +#define _DEVICE_H_
   46.16 +
   46.17 +#include <linux/ioport.h>
   46.18 +#include <linux/kobject.h>
   46.19 +#include <linux/klist.h>
   46.20 +#include <linux/list.h>
   46.21 +#include <linux/compiler.h>
   46.22 +#include <linux/types.h>
   46.23 +#include <linux/module.h>
   46.24 +#include <linux/pm.h>
   46.25 +#include <asm/semaphore.h>
   46.26 +#include <asm/atomic.h>
   46.27 +
   46.28 +#define DEVICE_NAME_SIZE	50
   46.29 +#define DEVICE_NAME_HALF	__stringify(20)	/* Less than half to accommodate slop */
   46.30 +#define DEVICE_ID_SIZE		32
   46.31 +#define BUS_ID_SIZE		KOBJ_NAME_LEN
   46.32 +
   46.33 +
   46.34 +struct device;
   46.35 +struct device_driver;
   46.36 +struct class;
   46.37 +struct class_device;
   46.38 +
   46.39 +struct bus_type {
   46.40 +	const char		* name;
   46.41 +
   46.42 +	struct subsystem	subsys;
   46.43 +	struct kset		drivers;
   46.44 +	struct kset		devices;
   46.45 +	struct klist		klist_devices;
   46.46 +	struct klist		klist_drivers;
   46.47 +
   46.48 +	struct bus_attribute	* bus_attrs;
   46.49 +	struct device_attribute	* dev_attrs;
   46.50 +	struct driver_attribute	* drv_attrs;
   46.51 +
   46.52 +	int		(*match)(struct device * dev, struct device_driver * drv);
   46.53 +	int		(*uevent)(struct device *dev, char **envp,
   46.54 +				  int num_envp, char *buffer, int buffer_size);
   46.55 +	int		(*probe)(struct device * dev);
   46.56 +	int		(*remove)(struct device * dev);
   46.57 +	void		(*shutdown)(struct device * dev);
   46.58 +
   46.59 +	int (*suspend)(struct device * dev, pm_message_t state);
   46.60 +	int (*suspend_late)(struct device * dev, pm_message_t state);
   46.61 +	int (*resume_early)(struct device * dev);
   46.62 +	int (*resume)(struct device * dev);
   46.63 +};
   46.64 +
   46.65 +extern int __must_check bus_register(struct bus_type * bus);
   46.66 +extern void bus_unregister(struct bus_type * bus);
   46.67 +
   46.68 +extern int __must_check bus_rescan_devices(struct bus_type * bus);
   46.69 +
   46.70 +/* iterator helpers for buses */
   46.71 +
   46.72 +int bus_for_each_dev(struct bus_type * bus, struct device * start, void * data,
   46.73 +		     int (*fn)(struct device *, void *));
   46.74 +struct device * bus_find_device(struct bus_type *bus, struct device *start,
   46.75 +				void *data, int (*match)(struct device *, void *));
   46.76 +
   46.77 +int __must_check bus_for_each_drv(struct bus_type *bus,
   46.78 +		struct device_driver *start, void *data,
   46.79 +		int (*fn)(struct device_driver *, void *));
   46.80 +
   46.81 +/* driverfs interface for exporting bus attributes */
   46.82 +
   46.83 +struct bus_attribute {
   46.84 +	struct attribute	attr;
   46.85 +	ssize_t (*show)(struct bus_type *, char * buf);
   46.86 +	ssize_t (*store)(struct bus_type *, const char * buf, size_t count);
   46.87 +};
   46.88 +
   46.89 +#define BUS_ATTR(_name,_mode,_show,_store)	\
   46.90 +struct bus_attribute bus_attr_##_name = __ATTR(_name,_mode,_show,_store)
   46.91 +
   46.92 +extern int __must_check bus_create_file(struct bus_type *,
   46.93 +					struct bus_attribute *);
   46.94 +extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
   46.95 +
   46.96 +struct device_driver {
   46.97 +	const char		* name;
   46.98 +	struct bus_type		* bus;
   46.99 +
  46.100 +	struct completion	unloaded;
  46.101 +	struct kobject		kobj;
  46.102 +	struct klist		klist_devices;
  46.103 +	struct klist_node	knode_bus;
  46.104 +
  46.105 +	struct module		* owner;
  46.106 +
  46.107 +	int	(*probe)	(struct device * dev);
  46.108 +	int	(*remove)	(struct device * dev);
  46.109 +	void	(*shutdown)	(struct device * dev);
  46.110 +	int	(*suspend)	(struct device * dev, pm_message_t state);
  46.111 +	int	(*resume)	(struct device * dev);
  46.112 +
  46.113 +	unsigned int multithread_probe:1;
  46.114 +};
  46.115 +
  46.116 +
  46.117 +extern int __must_check driver_register(struct device_driver * drv);
  46.118 +extern void driver_unregister(struct device_driver * drv);
  46.119 +
  46.120 +extern struct device_driver * get_driver(struct device_driver * drv);
  46.121 +extern void put_driver(struct device_driver * drv);
  46.122 +extern struct device_driver *driver_find(const char *name, struct bus_type *bus);
  46.123 +extern int driver_probe_done(void);
  46.124 +
  46.125 +/* driverfs interface for exporting driver attributes */
  46.126 +
  46.127 +struct driver_attribute {
  46.128 +	struct attribute	attr;
  46.129 +	ssize_t (*show)(struct device_driver *, char * buf);
  46.130 +	ssize_t (*store)(struct device_driver *, const char * buf, size_t count);
  46.131 +};
  46.132 +
  46.133 +#define DRIVER_ATTR(_name,_mode,_show,_store)	\
  46.134 +struct driver_attribute driver_attr_##_name = __ATTR(_name,_mode,_show,_store)
  46.135 +
  46.136 +extern int __must_check driver_create_file(struct device_driver *,
  46.137 +					struct driver_attribute *);
  46.138 +extern void driver_remove_file(struct device_driver *, struct driver_attribute *);
  46.139 +
  46.140 +extern int __must_check driver_for_each_device(struct device_driver * drv,
  46.141 +		struct device *start, void *data,
  46.142 +		int (*fn)(struct device *, void *));
  46.143 +struct device * driver_find_device(struct device_driver *drv,
  46.144 +				   struct device *start, void *data,
  46.145 +				   int (*match)(struct device *, void *));
  46.146 +
  46.147 +/*
  46.148 + * device classes
  46.149 + */
  46.150 +struct class {
  46.151 +	const char		* name;
  46.152 +	struct module		* owner;
  46.153 +
  46.154 +	struct subsystem	subsys;
  46.155 +	struct list_head	children;
  46.156 +	struct list_head	devices;
  46.157 +	struct list_head	interfaces;
  46.158 +	struct semaphore	sem;	/* locks both the children and interfaces lists */
  46.159 +
  46.160 +	struct kobject		*virtual_dir;
  46.161 +
  46.162 +	struct class_attribute		* class_attrs;
  46.163 +	struct class_device_attribute	* class_dev_attrs;
  46.164 +	struct device_attribute		* dev_attrs;
  46.165 +
  46.166 +	int	(*uevent)(struct class_device *dev, char **envp,
  46.167 +			   int num_envp, char *buffer, int buffer_size);
  46.168 +	int	(*dev_uevent)(struct device *dev, char **envp, int num_envp,
  46.169 +				char *buffer, int buffer_size);
  46.170 +
  46.171 +	void	(*release)(struct class_device *dev);
  46.172 +	void	(*class_release)(struct class *class);
  46.173 +	void	(*dev_release)(struct device *dev);
  46.174 +
  46.175 +	int	(*suspend)(struct device *, pm_message_t state);
  46.176 +	int	(*resume)(struct device *);
  46.177 +};
  46.178 +
  46.179 +extern int __must_check class_register(struct class *);
  46.180 +extern void class_unregister(struct class *);
  46.181 +
  46.182 +
  46.183 +struct class_attribute {
  46.184 +	struct attribute	attr;
  46.185 +	ssize_t (*show)(struct class *, char * buf);
  46.186 +	ssize_t (*store)(struct class *, const char * buf, size_t count);
  46.187 +};
  46.188 +
  46.189 +#define CLASS_ATTR(_name,_mode,_show,_store)			\
  46.190 +struct class_attribute class_attr_##_name = __ATTR(_name,_mode,_show,_store) 
  46.191 +
  46.192 +extern int __must_check class_create_file(struct class *,
  46.193 +					const struct class_attribute *);
  46.194 +extern void class_remove_file(struct class *, const struct class_attribute *);
  46.195 +
  46.196 +struct class_device_attribute {
  46.197 +	struct attribute	attr;
  46.198 +	ssize_t (*show)(struct class_device *, char * buf);
  46.199 +	ssize_t (*store)(struct class_device *, const char * buf, size_t count);
  46.200 +};
  46.201 +
  46.202 +#define CLASS_DEVICE_ATTR(_name,_mode,_show,_store)		\
  46.203 +struct class_device_attribute class_device_attr_##_name = 	\
  46.204 +	__ATTR(_name,_mode,_show,_store)
  46.205 +
  46.206 +extern int __must_check class_device_create_file(struct class_device *,
  46.207 +				    const struct class_device_attribute *);
  46.208 +
  46.209 +/**
  46.210 + * struct class_device - class devices
  46.211 + * @class: pointer to the parent class for this class device.  This is required.
  46.212 + * @devt: for internal use by the driver core only.
  46.213 + * @node: for internal use by the driver core only.
  46.214 + * @kobj: for internal use by the driver core only.
  46.215 + * @devt_attr: for internal use by the driver core only.
  46.216 + * @groups: optional additional groups to be created
  46.217 + * @dev: if set, a symlink to the struct device is created in the sysfs
  46.218 + * directory for this struct class device.
  46.219 + * @class_data: pointer to whatever you want to store here for this struct
  46.220 + * class_device.  Use class_get_devdata() and class_set_devdata() to get and
  46.221 + * set this pointer.
  46.222 + * @parent: pointer to a struct class_device that is the parent of this struct
  46.223 + * class_device.  If NULL, this class_device will show up at the root of the
  46.224 + * struct class in sysfs (which is probably what you want to have happen.)
  46.225 + * @release: pointer to a release function for this struct class_device.  If
  46.226 + * set, this will be called instead of the class specific release function.
  46.227 + * Only use this if you want to override the default release function, like
  46.228 + * when you are nesting class_device structures.
  46.229 + * @uevent: pointer to a uevent function for this struct class_device.  If
  46.230 + * set, this will be called instead of the class specific uevent function.
  46.231 + * Only use this if you want to override the default uevent function, like
  46.232 + * when you are nesting class_device structures.
  46.233 + */
  46.234 +struct class_device {
  46.235 +	struct list_head	node;
  46.236 +
  46.237 +	struct kobject		kobj;
  46.238 +	struct class		* class;	/* required */
  46.239 +	dev_t			devt;		/* dev_t, creates the sysfs "dev" */
  46.240 +	struct class_device_attribute *devt_attr;
  46.241 +	struct class_device_attribute uevent_attr;
  46.242 +	struct device		* dev;		/* not necessary, but nice to have */
  46.243 +	void			* class_data;	/* class-specific data */
  46.244 +	struct class_device	*parent;	/* parent of this child device, if there is one */
  46.245 +	struct attribute_group  ** groups;	/* optional groups */
  46.246 +
  46.247 +	void	(*release)(struct class_device *dev);
  46.248 +	int	(*uevent)(struct class_device *dev, char **envp,
  46.249 +			   int num_envp, char *buffer, int buffer_size);
  46.250 +	char	class_id[BUS_ID_SIZE];	/* unique to this class */
  46.251 +};
  46.252 +
  46.253 +static inline void *
  46.254 +class_get_devdata (struct class_device *dev)
  46.255 +{
  46.256 +	return dev->class_data;
  46.257 +}
  46.258 +
  46.259 +static inline void
  46.260 +class_set_devdata (struct class_device *dev, void *data)
  46.261 +{
  46.262 +	dev->class_data = data;
  46.263 +}
  46.264 +
  46.265 +
  46.266 +extern int __must_check class_device_register(struct class_device *);
  46.267 +extern void class_device_unregister(struct class_device *);
  46.268 +extern void class_device_initialize(struct class_device *);
  46.269 +extern int __must_check class_device_add(struct class_device *);
  46.270 +extern void class_device_del(struct class_device *);
  46.271 +
  46.272 +extern int class_device_rename(struct class_device *, char *);
  46.273 +
  46.274 +extern struct class_device * class_device_get(struct class_device *);
  46.275 +extern void class_device_put(struct class_device *);
  46.276 +
  46.277 +extern void class_device_remove_file(struct class_device *, 
  46.278 +				     const struct class_device_attribute *);
  46.279 +extern int __must_check class_device_create_bin_file(struct class_device *,
  46.280 +					struct bin_attribute *);
  46.281 +extern void class_device_remove_bin_file(struct class_device *,
  46.282 +					 struct bin_attribute *);
  46.283 +
  46.284 +struct class_interface {
  46.285 +	struct list_head	node;
  46.286 +	struct class		*class;
  46.287 +
  46.288 +	int (*add)	(struct class_device *, struct class_interface *);
  46.289 +	void (*remove)	(struct class_device *, struct class_interface *);
  46.290 +	int (*add_dev)		(struct device *, struct class_interface *);
  46.291 +	void (*remove_dev)	(struct device *, struct class_interface *);
  46.292 +};
  46.293 +
  46.294 +extern int __must_check class_interface_register(struct class_interface *);
  46.295 +extern void class_interface_unregister(struct class_interface *);
  46.296 +
  46.297 +extern struct class *class_create(struct module *owner, const char *name);
  46.298 +extern void class_destroy(struct class *cls);
  46.299 +extern struct class_device *class_device_create(struct class *cls,
  46.300 +						struct class_device *parent,
  46.301 +						dev_t devt,
  46.302 +						struct device *device,
  46.303 +						const char *fmt, ...)
  46.304 +					__attribute__((format(printf,5,6)));
  46.305 +extern void class_device_destroy(struct class *cls, dev_t devt);
  46.306 +
  46.307 +/* interface for exporting device attributes */
  46.308 +struct device_attribute {
  46.309 +	struct attribute	attr;
  46.310 +	ssize_t (*show)(struct device *dev, struct device_attribute *attr,
  46.311 +			char *buf);
  46.312 +	ssize_t (*store)(struct device *dev, struct device_attribute *attr,
  46.313 +			 const char *buf, size_t count);
  46.314 +};
  46.315 +
  46.316 +#define DEVICE_ATTR(_name,_mode,_show,_store) \
  46.317 +struct device_attribute dev_attr_##_name = __ATTR(_name,_mode,_show,_store)
  46.318 +
  46.319 +extern int __must_check device_create_file(struct device *device,
  46.320 +					struct device_attribute * entry);
  46.321 +extern void device_remove_file(struct device * dev, struct device_attribute * attr);
  46.322 +extern int __must_check device_create_bin_file(struct device *dev,
  46.323 +					       struct bin_attribute *attr);
  46.324 +extern void device_remove_bin_file(struct device *dev,
  46.325 +				   struct bin_attribute *attr);
  46.326 +struct device {
  46.327 +	struct klist		klist_children;
  46.328 +	struct klist_node	knode_parent;		/* node in sibling list */
  46.329 +	struct klist_node	knode_driver;
  46.330 +	struct klist_node	knode_bus;
  46.331 +	struct device 	* parent;
  46.332 +
  46.333 +	struct kobject kobj;
  46.334 +	char	bus_id[BUS_ID_SIZE];	/* position on parent bus */
  46.335 +	unsigned		is_registered:1;
  46.336 +	struct device_attribute uevent_attr;
  46.337 +	struct device_attribute *devt_attr;
  46.338 +
  46.339 +	struct semaphore	sem;	/* semaphore to synchronize calls to
  46.340 +					 * its driver.
  46.341 +					 */
  46.342 +
  46.343 +	struct bus_type	* bus;		/* type of bus device is on */
  46.344 +	struct device_driver *driver;	/* which driver has allocated this
  46.345 +					   device */
  46.346 +	void		*driver_data;	/* data private to the driver */
  46.347 +	void		*platform_data;	/* Platform specific data, device
  46.348 +					   core doesn't touch it */
  46.349 +	void		*firmware_data; /* Firmware specific data (e.g. ACPI,
  46.350 +					   BIOS data),reserved for device core*/
  46.351 +	struct dev_pm_info	power;
  46.352 +
  46.353 +	u64		*dma_mask;	/* dma mask (if dma'able device) */
  46.354 +	u64		coherent_dma_mask;/* Like dma_mask, but for
  46.355 +					     alloc_coherent mappings as
  46.356 +					     not all hardware supports
  46.357 +					     64 bit addresses for consistent
  46.358 +					     allocations such descriptors. */
  46.359 +
  46.360 +	struct list_head	dma_pools;	/* dma pools (if dma'ble) */
  46.361 +
  46.362 +	struct dma_coherent_mem	*dma_mem; /* internal for coherent mem
  46.363 +					     override */
  46.364 +
  46.365 +	/* class_device migration path */
  46.366 +	struct list_head	node;
  46.367 +	struct class		*class;		/* optional*/
  46.368 +	dev_t			devt;		/* dev_t, creates the sysfs "dev" */
  46.369 +	struct attribute_group	**groups;	/* optional groups */
  46.370 +
  46.371 +	void	(*release)(struct device * dev);
  46.372 +};
  46.373 +
  46.374 +static inline void *
  46.375 +dev_get_drvdata (struct device *dev)
  46.376 +{
  46.377 +	return dev->driver_data;
  46.378 +}
  46.379 +
  46.380 +static inline void
  46.381 +dev_set_drvdata (struct device *dev, void *data)
  46.382 +{
  46.383 +	dev->driver_data = data;
  46.384 +}
  46.385 +
  46.386 +static inline int device_is_registered(struct device *dev)
  46.387 +{
  46.388 +	return dev->is_registered;
  46.389 +}
  46.390 +
  46.391 +/*
  46.392 + * High level routines for use by the bus drivers
  46.393 + */
  46.394 +extern int __must_check device_register(struct device * dev);
  46.395 +extern void device_unregister(struct device * dev);
  46.396 +extern void device_initialize(struct device * dev);
  46.397 +extern int __must_check device_add(struct device * dev);
  46.398 +extern void device_del(struct device * dev);
  46.399 +extern int device_for_each_child(struct device *, void *,
  46.400 +		     int (*fn)(struct device *, void *));
  46.401 +extern int device_rename(struct device *dev, char *new_name);
  46.402 +
  46.403 +/*
  46.404 + * Manual binding of a device to driver. See drivers/base/bus.c
  46.405 + * for information on use.
  46.406 + */
  46.407 +extern int __must_check device_bind_driver(struct device *dev);
  46.408 +extern void device_release_driver(struct device * dev);
  46.409 +extern int  __must_check device_attach(struct device * dev);
  46.410 +extern int __must_check driver_attach(struct device_driver *drv);
  46.411 +extern int __must_check device_reprobe(struct device *dev);
  46.412 +
  46.413 +/*
  46.414 + * Easy functions for dynamically creating devices on the fly
  46.415 + */
  46.416 +extern struct device *device_create(struct class *cls, struct device *parent,
  46.417 +				    dev_t devt, const char *fmt, ...)
  46.418 +				    __attribute__((format(printf,4,5)));
  46.419 +extern void device_destroy(struct class *cls, dev_t devt);
  46.420 +
  46.421 +extern int virtual_device_parent(struct device *dev);
  46.422 +
  46.423 +/*
  46.424 + * Platform "fixup" functions - allow the platform to have their say
  46.425 + * about devices and actions that the general device layer doesn't
  46.426 + * know about.
  46.427 + */
  46.428 +/* Notify platform of device discovery */
  46.429 +extern int (*platform_notify)(struct device * dev);
  46.430 +
  46.431 +extern int (*platform_notify_remove)(struct device * dev);
  46.432 +
  46.433 +
  46.434 +/**
  46.435 + * get_device - atomically increment the reference count for the device.
  46.436 + *
  46.437 + */
  46.438 +extern struct device * get_device(struct device * dev);
  46.439 +extern void put_device(struct device * dev);
  46.440 +
  46.441 +
  46.442 +/* drivers/base/power/shutdown.c */
  46.443 +extern void device_shutdown(void);
  46.444 +
  46.445 +
  46.446 +/* drivers/base/firmware.c */
  46.447 +extern int __must_check firmware_register(struct subsystem *);
  46.448 +extern void firmware_unregister(struct subsystem *);
  46.449 +
  46.450 +/* debugging and troubleshooting/diagnostic helpers. */
  46.451 +extern const char *dev_driver_string(struct device *dev);
  46.452 +#define dev_printk(level, dev, format, arg...)	\
  46.453 +	printk(level "%s %s: " format , dev_driver_string(dev) , (dev)->bus_id , ## arg)
  46.454 +
  46.455 +#ifdef DEBUG
  46.456 +#define dev_dbg(dev, format, arg...)		\
  46.457 +	dev_printk(KERN_DEBUG , dev , format , ## arg)
  46.458 +#else
  46.459 +#define dev_dbg(dev, format, arg...) do { (void)(dev); } while (0)
  46.460 +#endif
  46.461 +
  46.462 +#define dev_err(dev, format, arg...)		\
  46.463 +	dev_printk(KERN_ERR , dev , format , ## arg)
  46.464 +#define dev_info(dev, format, arg...)		\
  46.465 +	dev_printk(KERN_INFO , dev , format , ## arg)
  46.466 +#define dev_warn(dev, format, arg...)		\
  46.467 +	dev_printk(KERN_WARNING , dev , format , ## arg)
  46.468 +#define dev_notice(dev, format, arg...)		\
  46.469 +	dev_printk(KERN_NOTICE , dev , format , ## arg)
  46.470 +
  46.471 +/* Create alias, so I can be autoloaded. */
  46.472 +#define MODULE_ALIAS_CHARDEV(major,minor) \
  46.473 +	MODULE_ALIAS("char-major-" __stringify(major) "-" __stringify(minor))
  46.474 +#define MODULE_ALIAS_CHARDEV_MAJOR(major) \
  46.475 +	MODULE_ALIAS("char-major-" __stringify(major) "-*")
  46.476 +#endif /* _DEVICE_H_ */
    47.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    47.2 +++ b/xen/include/asm-ia64/linux-xen/linux/kobject.h	Wed Dec 13 11:08:40 2006 -0700
    47.3 @@ -0,0 +1,282 @@
    47.4 +/*
    47.5 + * kobject.h - generic kernel object infrastructure.
    47.6 + *
    47.7 + * Copyright (c) 2002-2003	Patrick Mochel
    47.8 + * Copyright (c) 2002-2003	Open Source Development Labs
    47.9 + *
   47.10 + * This file is released under the GPLv2.
   47.11 + *
   47.12 + * 
   47.13 + * Please read Documentation/kobject.txt before using the kobject
   47.14 + * interface, ESPECIALLY the parts about reference counts and object
   47.15 + * destructors. 
   47.16 + */
   47.17 +
   47.18 +#ifndef _KOBJECT_H_
   47.19 +#define _KOBJECT_H_
   47.20 +
   47.21 +#ifdef __KERNEL__
   47.22 +
   47.23 +#include <linux/types.h>
   47.24 +#include <linux/list.h>
   47.25 +#include <linux/sysfs.h>
   47.26 +#include <linux/compiler.h>
   47.27 +#include <linux/spinlock.h>
   47.28 +#include <linux/rwsem.h>
   47.29 +#include <linux/kref.h>
   47.30 +#include <linux/kernel.h>
   47.31 +#include <linux/wait.h>
   47.32 +#include <asm/atomic.h>
   47.33 +
   47.34 +#define KOBJ_NAME_LEN			20
   47.35 +#define UEVENT_HELPER_PATH_LEN		256
   47.36 +
   47.37 +/* path to the userspace helper executed on an event */
   47.38 +extern char uevent_helper[];
   47.39 +
   47.40 +/* counter to tag the uevent, read only except for the kobject core */
   47.41 +extern u64 uevent_seqnum;
   47.42 +
   47.43 +/* the actions here must match the proper string in lib/kobject_uevent.c */
   47.44 +typedef int __bitwise kobject_action_t;
   47.45 +enum kobject_action {
   47.46 +	KOBJ_ADD	= (__force kobject_action_t) 0x01,	/* exclusive to core */
   47.47 +	KOBJ_REMOVE	= (__force kobject_action_t) 0x02,	/* exclusive to core */
   47.48 +	KOBJ_CHANGE	= (__force kobject_action_t) 0x03,	/* device state change */
   47.49 +	KOBJ_MOUNT	= (__force kobject_action_t) 0x04,	/* mount event for block devices (broken) */
   47.50 +	KOBJ_UMOUNT	= (__force kobject_action_t) 0x05,	/* umount event for block devices (broken) */
   47.51 +	KOBJ_OFFLINE	= (__force kobject_action_t) 0x06,	/* device offline */
   47.52 +	KOBJ_ONLINE	= (__force kobject_action_t) 0x07,	/* device online */
   47.53 +};
   47.54 +
   47.55 +struct kobject {
   47.56 +	const char		* k_name;
   47.57 +	char			name[KOBJ_NAME_LEN];
   47.58 +	struct kref		kref;
   47.59 +	struct list_head	entry;
   47.60 +	struct kobject		* parent;
   47.61 +	struct kset		* kset;
   47.62 +	struct kobj_type	* ktype;
   47.63 +	struct dentry		* dentry;
   47.64 +	wait_queue_head_t	poll;
   47.65 +};
   47.66 +
   47.67 +extern int kobject_set_name(struct kobject *, const char *, ...)
   47.68 +	__attribute__((format(printf,2,3)));
   47.69 +
   47.70 +static inline const char * kobject_name(const struct kobject * kobj)
   47.71 +{
   47.72 +	return kobj->k_name;
   47.73 +}
   47.74 +
   47.75 +extern void kobject_init(struct kobject *);
   47.76 +extern void kobject_cleanup(struct kobject *);
   47.77 +
   47.78 +extern int __must_check kobject_add(struct kobject *);
   47.79 +extern void kobject_del(struct kobject *);
   47.80 +
   47.81 +extern int __must_check kobject_rename(struct kobject *, const char *new_name);
   47.82 +
   47.83 +extern int __must_check kobject_register(struct kobject *);
   47.84 +extern void kobject_unregister(struct kobject *);
   47.85 +
   47.86 +extern struct kobject * kobject_get(struct kobject *);
   47.87 +extern void kobject_put(struct kobject *);
   47.88 +
   47.89 +extern struct kobject *kobject_add_dir(struct kobject *, const char *);
   47.90 +
   47.91 +extern char * kobject_get_path(struct kobject *, gfp_t);
   47.92 +
   47.93 +struct kobj_type {
   47.94 +	void (*release)(struct kobject *);
   47.95 +	struct sysfs_ops	* sysfs_ops;
   47.96 +	struct attribute	** default_attrs;
   47.97 +};
   47.98 +
   47.99 +
  47.100 +/**
  47.101 + *	kset - a set of kobjects of a specific type, belonging
  47.102 + *	to a specific subsystem.
  47.103 + *
  47.104 + *	All kobjects of a kset should be embedded in an identical 
  47.105 + *	type. This type may have a descriptor, which the kset points
  47.106 + *	to. This allows there to exist sets of objects of the same
  47.107 + *	type in different subsystems.
  47.108 + *
  47.109 + *	A subsystem does not have to be a list of only one type 
  47.110 + *	of object; multiple ksets can belong to one subsystem. All 
  47.111 + *	ksets of a subsystem share the subsystem's lock.
  47.112 + *
  47.113 + *	Each kset can support specific event variables; it can
  47.114 + *	supress the event generation or add subsystem specific
  47.115 + *	variables carried with the event.
  47.116 + */
  47.117 +struct kset_uevent_ops {
  47.118 +	int (*filter)(struct kset *kset, struct kobject *kobj);
  47.119 +	const char *(*name)(struct kset *kset, struct kobject *kobj);
  47.120 +	int (*uevent)(struct kset *kset, struct kobject *kobj, char **envp,
  47.121 +			int num_envp, char *buffer, int buffer_size);
  47.122 +};
  47.123 +
  47.124 +struct kset {
  47.125 +	struct subsystem	* subsys;
  47.126 +	struct kobj_type	* ktype;
  47.127 +	struct list_head	list;
  47.128 +	spinlock_t		list_lock;
  47.129 +	struct kobject		kobj;
  47.130 +	struct kset_uevent_ops	* uevent_ops;
  47.131 +};
  47.132 +
  47.133 +
  47.134 +extern void kset_init(struct kset * k);
  47.135 +extern int __must_check kset_add(struct kset * k);
  47.136 +extern int __must_check kset_register(struct kset * k);
  47.137 +extern void kset_unregister(struct kset * k);
  47.138 +
  47.139 +static inline struct kset * to_kset(struct kobject * kobj)
  47.140 +{
  47.141 +	return kobj ? container_of(kobj,struct kset,kobj) : NULL;
  47.142 +}
  47.143 +
  47.144 +static inline struct kset * kset_get(struct kset * k)
  47.145 +{
  47.146 +	return k ? to_kset(kobject_get(&k->kobj)) : NULL;
  47.147 +}
  47.148 +
  47.149 +static inline void kset_put(struct kset * k)
  47.150 +{
  47.151 +	kobject_put(&k->kobj);
  47.152 +}
  47.153 +
  47.154 +static inline struct kobj_type * get_ktype(struct kobject * k)
  47.155 +{
  47.156 +	if (k->kset && k->kset->ktype)
  47.157 +		return k->kset->ktype;
  47.158 +	else 
  47.159 +		return k->ktype;
  47.160 +}
  47.161 +
  47.162 +extern struct kobject * kset_find_obj(struct kset *, const char *);
  47.163 +
  47.164 +
  47.165 +/**
  47.166 + * Use this when initializing an embedded kset with no other 
  47.167 + * fields to initialize.
  47.168 + */
  47.169 +#define set_kset_name(str)	.kset = { .kobj = { .name = str } }
  47.170 +
  47.171 +
  47.172 +
  47.173 +struct subsystem {
  47.174 +	struct kset		kset;
  47.175 +	struct rw_semaphore	rwsem;
  47.176 +};
  47.177 +
  47.178 +#define decl_subsys(_name,_type,_uevent_ops) \
  47.179 +struct subsystem _name##_subsys = { \
  47.180 +	.kset = { \
  47.181 +		.kobj = { .name = __stringify(_name) }, \
  47.182 +		.ktype = _type, \
  47.183 +		.uevent_ops =_uevent_ops, \
  47.184 +	} \
  47.185 +}
  47.186 +#define decl_subsys_name(_varname,_name,_type,_uevent_ops) \
  47.187 +struct subsystem _varname##_subsys = { \
  47.188 +	.kset = { \
  47.189 +		.kobj = { .name = __stringify(_name) }, \
  47.190 +		.ktype = _type, \
  47.191 +		.uevent_ops =_uevent_ops, \
  47.192 +	} \
  47.193 +}
  47.194 +
  47.195 +/* The global /sys/kernel/ subsystem for people to chain off of */
  47.196 +extern struct subsystem kernel_subsys;
  47.197 +/* The global /sys/hypervisor/ subsystem  */
  47.198 +extern struct subsystem hypervisor_subsys;
  47.199 +
  47.200 +/**
  47.201 + * Helpers for setting the kset of registered objects.
  47.202 + * Often, a registered object belongs to a kset embedded in a 
  47.203 + * subsystem. These do no magic, just make the resulting code
  47.204 + * easier to follow. 
  47.205 + */
  47.206 +
  47.207 +/**
  47.208 + *	kobj_set_kset_s(obj,subsys) - set kset for embedded kobject.
  47.209 + *	@obj:		ptr to some object type.
  47.210 + *	@subsys:	a subsystem object (not a ptr).
  47.211 + *
  47.212 + *	Can be used for any object type with an embedded ->kobj.
  47.213 + */
  47.214 +
  47.215 +#define kobj_set_kset_s(obj,subsys) \
  47.216 +	(obj)->kobj.kset = &(subsys).kset
  47.217 +
  47.218 +/**
  47.219 + *	kset_set_kset_s(obj,subsys) - set kset for embedded kset.
  47.220 + *	@obj:		ptr to some object type.
  47.221 + *	@subsys:	a subsystem object (not a ptr).
  47.222 + *
  47.223 + *	Can be used for any object type with an embedded ->kset.
  47.224 + *	Sets the kset of @obj's  embedded kobject (via its embedded
  47.225 + *	kset) to @subsys.kset. This makes @obj a member of that 
  47.226 + *	kset.
  47.227 + */
  47.228 +
  47.229 +#define kset_set_kset_s(obj,subsys) \
  47.230 +	(obj)->kset.kobj.kset = &(subsys).kset
  47.231 +
  47.232 +/**
  47.233 + *	subsys_set_kset(obj,subsys) - set kset for subsystem
  47.234 + *	@obj:		ptr to some object type.
  47.235 + *	@subsys:	a subsystem object (not a ptr).
  47.236 + *
  47.237 + *	Can be used for any object type with an embedded ->subsys.
  47.238 + *	Sets the kset of @obj's kobject to @subsys.kset. This makes
  47.239 + *	the object a member of that kset.
  47.240 + */
  47.241 +
  47.242 +#define subsys_set_kset(obj,_subsys) \
  47.243 +	(obj)->subsys.kset.kobj.kset = &(_subsys).kset
  47.244 +
  47.245 +extern void subsystem_init(struct subsystem *);
  47.246 +extern int __must_check subsystem_register(struct subsystem *);
  47.247 +extern void subsystem_unregister(struct subsystem *);
  47.248 +
  47.249 +static inline struct subsystem * subsys_get(struct subsystem * s)
  47.250 +{
  47.251 +	return s ? container_of(kset_get(&s->kset),struct subsystem,kset) : NULL;
  47.252 +}
  47.253 +
  47.254 +static inline void subsys_put(struct subsystem * s)
  47.255 +{
  47.256 +	kset_put(&s->kset);
  47.257 +}
  47.258 +
  47.259 +struct subsys_attribute {
  47.260 +	struct attribute attr;
  47.261 +	ssize_t (*show)(struct subsystem *, char *);
  47.262 +	ssize_t (*store)(struct subsystem *, const char *, size_t); 
  47.263 +};
  47.264 +
  47.265 +extern int __must_check subsys_create_file(struct subsystem * ,
  47.266 +					struct subsys_attribute *);
  47.267 +
  47.268 +#if defined(CONFIG_HOTPLUG)
  47.269 +void kobject_uevent(struct kobject *kobj, enum kobject_action action);
  47.270 +
  47.271 +int add_uevent_var(char **envp, int num_envp, int *cur_index,
  47.272 +			char *buffer, int buffer_size, int *cur_len,
  47.273 +			const char *format, ...)
  47.274 +	__attribute__((format (printf, 7, 8)));
  47.275 +#else
  47.276 +static inline void kobject_uevent(struct kobject *kobj, enum kobject_action action) { }
  47.277 +
  47.278 +static inline int add_uevent_var(char **envp, int num_envp, int *cur_index,
  47.279 +				      char *buffer, int buffer_size, int *cur_len, 
  47.280 +				      const char *format, ...)
  47.281 +{ return 0; }
  47.282 +#endif
  47.283 +
  47.284 +#endif /* __KERNEL__ */
  47.285 +#endif /* _KOBJECT_H_ */
    48.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    48.2 +++ b/xen/include/asm-ia64/linux-xen/linux/pci.h	Wed Dec 13 11:08:40 2006 -0700
    48.3 @@ -0,0 +1,817 @@
    48.4 +/*
    48.5 + *	pci.h
    48.6 + *
    48.7 + *	PCI defines and function prototypes
    48.8 + *	Copyright 1994, Drew Eckhardt
    48.9 + *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
   48.10 + *
   48.11 + *	For more information, please consult the following manuals (look at
   48.12 + *	http://www.pcisig.com/ for how to get them):
   48.13 + *
   48.14 + *	PCI BIOS Specification
   48.15 + *	PCI Local Bus Specification
   48.16 + *	PCI to PCI Bridge Specification
   48.17 + *	PCI System Design Guide
   48.18 + */
   48.19 +
   48.20 +#ifndef LINUX_PCI_H
   48.21 +#define LINUX_PCI_H
   48.22 +
   48.23 +/* Include the pci register defines */
   48.24 +#include <linux/pci_regs.h>
   48.25 +
   48.26 +/* Include the ID list */
   48.27 +#include <linux/pci_ids.h>
   48.28 +
   48.29 +/*
   48.30 + * The PCI interface treats multi-function devices as independent
   48.31 + * devices.  The slot/function address of each device is encoded
   48.32 + * in a single byte as follows:
   48.33 + *
   48.34 + *	7:3 = slot
   48.35 + *	2:0 = function
   48.36 + */
   48.37 +#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
   48.38 +#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
   48.39 +#define PCI_FUNC(devfn)		((devfn) & 0x07)
   48.40 +
   48.41 +/* Ioctls for /proc/bus/pci/X/Y nodes. */
   48.42 +#define PCIIOC_BASE		('P' << 24 | 'C' << 16 | 'I' << 8)
   48.43 +#define PCIIOC_CONTROLLER	(PCIIOC_BASE | 0x00)	/* Get controller for PCI device. */
   48.44 +#define PCIIOC_MMAP_IS_IO	(PCIIOC_BASE | 0x01)	/* Set mmap state to I/O space. */
   48.45 +#define PCIIOC_MMAP_IS_MEM	(PCIIOC_BASE | 0x02)	/* Set mmap state to MEM space. */
   48.46 +#define PCIIOC_WRITE_COMBINE	(PCIIOC_BASE | 0x03)	/* Enable/disable write-combining. */
   48.47 +
   48.48 +#ifdef __KERNEL__
   48.49 +
   48.50 +#include <linux/mod_devicetable.h>
   48.51 +
   48.52 +#include <linux/types.h>
   48.53 +#include <linux/ioport.h>
   48.54 +#include <linux/list.h>
   48.55 +#include <linux/compiler.h>
   48.56 +#include <linux/errno.h>
   48.57 +#include <linux/device.h>
   48.58 +
   48.59 +/* File state for mmap()s on /proc/bus/pci/X/Y */
   48.60 +enum pci_mmap_state {
   48.61 +	pci_mmap_io,
   48.62 +	pci_mmap_mem
   48.63 +};
   48.64 +
   48.65 +/* This defines the direction arg to the DMA mapping routines. */
   48.66 +#define PCI_DMA_BIDIRECTIONAL	0
   48.67 +#define PCI_DMA_TODEVICE	1
   48.68 +#define PCI_DMA_FROMDEVICE	2
   48.69 +#define PCI_DMA_NONE		3
   48.70 +
   48.71 +#define DEVICE_COUNT_COMPATIBLE	4
   48.72 +#define DEVICE_COUNT_RESOURCE	12
   48.73 +
   48.74 +typedef int __bitwise pci_power_t;
   48.75 +
   48.76 +#define PCI_D0		((pci_power_t __force) 0)
   48.77 +#define PCI_D1		((pci_power_t __force) 1)
   48.78 +#define PCI_D2		((pci_power_t __force) 2)
   48.79 +#define PCI_D3hot	((pci_power_t __force) 3)
   48.80 +#define PCI_D3cold	((pci_power_t __force) 4)
   48.81 +#define PCI_UNKNOWN	((pci_power_t __force) 5)
   48.82 +#define PCI_POWER_ERROR	((pci_power_t __force) -1)
   48.83 +
   48.84 +/** The pci_channel state describes connectivity between the CPU and
   48.85 + *  the pci device.  If some PCI bus between here and the pci device
   48.86 + *  has crashed or locked up, this info is reflected here.
   48.87 + */
   48.88 +typedef unsigned int __bitwise pci_channel_state_t;
   48.89 +
   48.90 +enum pci_channel_state {
   48.91 +	/* I/O channel is in normal state */
   48.92 +	pci_channel_io_normal = (__force pci_channel_state_t) 1,
   48.93 +
   48.94 +	/* I/O to channel is blocked */
   48.95 +	pci_channel_io_frozen = (__force pci_channel_state_t) 2,
   48.96 +
   48.97 +	/* PCI card is dead */
   48.98 +	pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
   48.99 +};
  48.100 +
  48.101 +typedef unsigned short __bitwise pci_bus_flags_t;
  48.102 +enum pci_bus_flags {
  48.103 +	PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
  48.104 +};
  48.105 +
  48.106 +struct pci_cap_saved_state {
  48.107 +	struct hlist_node next;
  48.108 +	char cap_nr;
  48.109 +	u32 data[0];
  48.110 +};
  48.111 +
  48.112 +/*
  48.113 + * The pci_dev structure is used to describe PCI devices.
  48.114 + */
  48.115 +struct pci_dev {
  48.116 +	struct list_head global_list;	/* node in list of all PCI devices */
  48.117 +	struct list_head bus_list;	/* node in per-bus list */
  48.118 +	struct pci_bus	*bus;		/* bus this device is on */
  48.119 +	struct pci_bus	*subordinate;	/* bus this device bridges to */
  48.120 +
  48.121 +	void		*sysdata;	/* hook for sys-specific extension */
  48.122 +	struct proc_dir_entry *procent;	/* device entry in /proc/bus/pci */
  48.123 +
  48.124 +	unsigned int	devfn;		/* encoded device & function index */
  48.125 +	unsigned short	vendor;
  48.126 +	unsigned short	device;
  48.127 +	unsigned short	subsystem_vendor;
  48.128 +	unsigned short	subsystem_device;
  48.129 +	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
  48.130 +	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
  48.131 +	u8		rom_base_reg;	/* which config register controls the ROM */
  48.132 +	u8		pin;  		/* which interrupt pin this device uses */
  48.133 +
  48.134 +	struct pci_driver *driver;	/* which driver has allocated this device */
  48.135 +	u64		dma_mask;	/* Mask of the bits of bus address this
  48.136 +					   device implements.  Normally this is
  48.137 +					   0xffffffff.  You only need to change
  48.138 +					   this if your device has broken DMA
  48.139 +					   or supports 64-bit transfers.  */
  48.140 +
  48.141 +	pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
  48.142 +					   this is D0-D3, D0 being fully functional,
  48.143 +					   and D3 being off. */
  48.144 +
  48.145 +	pci_channel_state_t error_state;	/* current connectivity state */
  48.146 +	struct	device	dev;		/* Generic device interface */
  48.147 +
  48.148 +	/* device is compatible with these IDs */
  48.149 +	unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
  48.150 +	unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
  48.151 +
  48.152 +	int		cfg_size;	/* Size of configuration space */
  48.153 +
  48.154 +	/*
  48.155 +	 * Instead of touching interrupt line and base address registers
  48.156 +	 * directly, use the values stored here. They might be different!
  48.157 +	 */
  48.158 +	unsigned int	irq;
  48.159 +	struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
  48.160 +
  48.161 +	/* These fields are used by common fixups */
  48.162 +	unsigned int	transparent:1;	/* Transparent PCI bridge */
  48.163 +	unsigned int	multifunction:1;/* Part of multi-function device */
  48.164 +	/* keep track of device state */
  48.165 +	unsigned int	is_enabled:1;	/* pci_enable_device has been called */
  48.166 +	unsigned int	is_busmaster:1; /* device is busmaster */
  48.167 +	unsigned int	no_msi:1;	/* device may not use msi */
  48.168 +	unsigned int	no_d1d2:1;   /* only allow d0 or d3 */
  48.169 +	unsigned int	block_ucfg_access:1;	/* userspace config space access is blocked */
  48.170 +	unsigned int	broken_parity_status:1;	/* Device generates false positive parity */
  48.171 +	unsigned int 	msi_enabled:1;
  48.172 +	unsigned int	msix_enabled:1;
  48.173 +
  48.174 +	u32		saved_config_space[16]; /* config space saved at suspend time */
  48.175 +	struct hlist_head saved_cap_space;
  48.176 +	struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
  48.177 +	int rom_attr_enabled;		/* has display of the rom attribute been enabled? */
  48.178 +	struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
  48.179 +};
  48.180 +
  48.181 +#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
  48.182 +#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
  48.183 +#define	to_pci_dev(n) container_of(n, struct pci_dev, dev)
  48.184 +#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
  48.185 +
  48.186 +static inline struct pci_cap_saved_state *pci_find_saved_cap(
  48.187 +	struct pci_dev *pci_dev,char cap)
  48.188 +{
  48.189 +	struct pci_cap_saved_state *tmp;
  48.190 +	struct hlist_node *pos;
  48.191 +
  48.192 +	hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
  48.193 +		if (tmp->cap_nr == cap)
  48.194 +			return tmp;
  48.195 +	}
  48.196 +	return NULL;
  48.197 +}
  48.198 +
  48.199 +static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
  48.200 +	struct pci_cap_saved_state *new_cap)
  48.201 +{
  48.202 +	hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
  48.203 +}
  48.204 +
  48.205 +static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
  48.206 +{
  48.207 +	hlist_del(&cap->next);
  48.208 +}
  48.209 +
  48.210 +/*
  48.211 + *  For PCI devices, the region numbers are assigned this way:
  48.212 + *
  48.213 + *	0-5	standard PCI regions
  48.214 + *	6	expansion ROM
  48.215 + *	7-10	bridges: address space assigned to buses behind the bridge
  48.216 + */
  48.217 +
  48.218 +#define PCI_ROM_RESOURCE	6
  48.219 +#define PCI_BRIDGE_RESOURCES	7
  48.220 +#define PCI_NUM_RESOURCES	11
  48.221 +
  48.222 +#ifndef PCI_BUS_NUM_RESOURCES
  48.223 +#define PCI_BUS_NUM_RESOURCES	8
  48.224 +#endif
  48.225 +
  48.226 +#define PCI_REGION_FLAG_MASK	0x0fU	/* These bits of resource flags tell us the PCI region flags */
  48.227 +
  48.228 +struct pci_bus {
  48.229 +	struct list_head node;		/* node in list of buses */
  48.230 +	struct pci_bus	*parent;	/* parent bus this bridge is on */
  48.231 +	struct list_head children;	/* list of child buses */
  48.232 +	struct list_head devices;	/* list of devices on this bus */
  48.233 +	struct pci_dev	*self;		/* bridge device as seen by parent */
  48.234 +	struct resource	*resource[PCI_BUS_NUM_RESOURCES];
  48.235 +					/* address space routed to this bus */
  48.236 +
  48.237 +	struct pci_ops	*ops;		/* configuration access functions */
  48.238 +	void		*sysdata;	/* hook for sys-specific extension */
  48.239 +	struct proc_dir_entry *procdir;	/* directory entry in /proc/bus/pci */
  48.240 +
  48.241 +	unsigned char	number;		/* bus number */
  48.242 +	unsigned char	primary;	/* number of primary bridge */
  48.243 +	unsigned char	secondary;	/* number of secondary bridge */
  48.244 +	unsigned char	subordinate;	/* max number of subordinate buses */
  48.245 +
  48.246 +	char		name[48];
  48.247 +
  48.248 +	unsigned short  bridge_ctl;	/* manage NO_ISA/FBB/et al behaviors */
  48.249 +	pci_bus_flags_t bus_flags;	/* Inherited by child busses */
  48.250 +	struct device		*bridge;
  48.251 +	struct class_device	class_dev;
  48.252 +	struct bin_attribute	*legacy_io; /* legacy I/O for this bus */
  48.253 +	struct bin_attribute	*legacy_mem; /* legacy mem */
  48.254 +};
  48.255 +
  48.256 +#define pci_bus_b(n)	list_entry(n, struct pci_bus, node)
  48.257 +#define to_pci_bus(n)	container_of(n, struct pci_bus, class_dev)
  48.258 +
  48.259 +/*
  48.260 + * Error values that may be returned by PCI functions.
  48.261 + */
  48.262 +#define PCIBIOS_SUCCESSFUL		0x00
  48.263 +#define PCIBIOS_FUNC_NOT_SUPPORTED	0x81
  48.264 +#define PCIBIOS_BAD_VENDOR_ID		0x83
  48.265 +#define PCIBIOS_DEVICE_NOT_FOUND	0x86
  48.266 +#define PCIBIOS_BAD_REGISTER_NUMBER	0x87
  48.267 +#define PCIBIOS_SET_FAILED		0x88
  48.268 +#define PCIBIOS_BUFFER_TOO_SMALL	0x89
  48.269 +
  48.270 +/* Low-level architecture-dependent routines */
  48.271 +
  48.272 +struct pci_ops {
  48.273 +	int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  48.274 +	int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  48.275 +};
  48.276 +
  48.277 +struct pci_raw_ops {
  48.278 +	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  48.279 +		    int reg, int len, u32 *val);
  48.280 +	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  48.281 +		     int reg, int len, u32 val);
  48.282 +};
  48.283 +
  48.284 +extern struct pci_raw_ops *raw_pci_ops;
  48.285 +
  48.286 +struct pci_bus_region {
  48.287 +	unsigned long start;
  48.288 +	unsigned long end;
  48.289 +};
  48.290 +
  48.291 +struct pci_dynids {
  48.292 +	spinlock_t lock;            /* protects list, index */
  48.293 +	struct list_head list;      /* for IDs added at runtime */
  48.294 +	unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
  48.295 +};
  48.296 +
  48.297 +/* ---------------------------------------------------------------- */
  48.298 +/** PCI Error Recovery System (PCI-ERS).  If a PCI device driver provides
  48.299 + *  a set fof callbacks in struct pci_error_handlers, then that device driver
  48.300 + *  will be notified of PCI bus errors, and will be driven to recovery
  48.301 + *  when an error occurs.
  48.302 + */
  48.303 +
  48.304 +typedef unsigned int __bitwise pci_ers_result_t;
  48.305 +
  48.306 +enum pci_ers_result {
  48.307 +	/* no result/none/not supported in device driver */
  48.308 +	PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
  48.309 +
  48.310 +	/* Device driver can recover without slot reset */
  48.311 +	PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
  48.312 +
  48.313 +	/* Device driver wants slot to be reset. */
  48.314 +	PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
  48.315 +
  48.316 +	/* Device has completely failed, is unrecoverable */
  48.317 +	PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
  48.318 +
  48.319 +	/* Device driver is fully recovered and operational */
  48.320 +	PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
  48.321 +};
  48.322 +
  48.323 +/* PCI bus error event callbacks */
  48.324 +struct pci_error_handlers
  48.325 +{
  48.326 +	/* PCI bus error detected on this device */
  48.327 +	pci_ers_result_t (*error_detected)(struct pci_dev *dev,
  48.328 +	                      enum pci_channel_state error);
  48.329 +
  48.330 +	/* MMIO has been re-enabled, but not DMA */
  48.331 +	pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
  48.332 +
  48.333 +	/* PCI Express link has been reset */
  48.334 +	pci_ers_result_t (*link_reset)(struct pci_dev *dev);
  48.335 +
  48.336 +	/* PCI slot has been reset */
  48.337 +	pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
  48.338 +
  48.339 +	/* Device driver may resume normal operations */
  48.340 +	void (*resume)(struct pci_dev *dev);
  48.341 +};
  48.342 +
  48.343 +/* ---------------------------------------------------------------- */
  48.344 +
  48.345 +struct module;
  48.346 +struct pci_driver {
  48.347 +	struct list_head node;
  48.348 +	char *name;
  48.349 +	const struct pci_device_id *id_table;	/* must be non-NULL for probe to be called */
  48.350 +	int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);	/* New device inserted */
  48.351 +	void (*remove) (struct pci_dev *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
  48.352 +	int  (*suspend) (struct pci_dev *dev, pm_message_t state);	/* Device suspended */
  48.353 +	int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
  48.354 +	int  (*resume_early) (struct pci_dev *dev);
  48.355 +	int  (*resume) (struct pci_dev *dev);	                /* Device woken up */
  48.356 +	int  (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable);   /* Enable wake event */
  48.357 +	void (*shutdown) (struct pci_dev *dev);
  48.358 +
  48.359 +	struct pci_error_handlers *err_handler;
  48.360 +	struct device_driver	driver;
  48.361 +	struct pci_dynids dynids;
  48.362 +
  48.363 +	int multithread_probe;
  48.364 +};
  48.365 +
  48.366 +#define	to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
  48.367 +
  48.368 +/**
  48.369 + * PCI_DEVICE - macro used to describe a specific pci device
  48.370 + * @vend: the 16 bit PCI Vendor ID
  48.371 + * @dev: the 16 bit PCI Device ID
  48.372 + *
  48.373 + * This macro is used to create a struct pci_device_id that matches a
  48.374 + * specific device.  The subvendor and subdevice fields will be set to
  48.375 + * PCI_ANY_ID.
  48.376 + */
  48.377 +#define PCI_DEVICE(vend,dev) \
  48.378 +	.vendor = (vend), .device = (dev), \
  48.379 +	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  48.380 +
  48.381 +/**
  48.382 + * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
  48.383 + * @dev_class: the class, subclass, prog-if triple for this device
  48.384 + * @dev_class_mask: the class mask for this device
  48.385 + *
  48.386 + * This macro is used to create a struct pci_device_id that matches a
  48.387 + * specific PCI class.  The vendor, device, subvendor, and subdevice
  48.388 + * fields will be set to PCI_ANY_ID.
  48.389 + */
  48.390 +#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
  48.391 +	.class = (dev_class), .class_mask = (dev_class_mask), \
  48.392 +	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
  48.393 +	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  48.394 +
  48.395 +/*
  48.396 + * pci_module_init is obsolete, this stays here till we fix up all usages of it
  48.397 + * in the tree.
  48.398 + */
  48.399 +#define pci_module_init	pci_register_driver
  48.400 +
  48.401 +/* these external functions are only available when PCI support is enabled */
  48.402 +#ifdef CONFIG_PCI
  48.403 +
  48.404 +extern struct bus_type pci_bus_type;
  48.405 +
  48.406 +/* Do NOT directly access these two variables, unless you are arch specific pci
  48.407 + * code, or pci core code. */
  48.408 +extern struct list_head pci_root_buses;	/* list of all known PCI buses */
  48.409 +extern struct list_head pci_devices;	/* list of all devices */
  48.410 +
  48.411 +void pcibios_fixup_bus(struct pci_bus *);
  48.412 +int __must_check pcibios_enable_device(struct pci_dev *, int mask);
  48.413 +char *pcibios_setup (char *str);
  48.414 +
  48.415 +/* Used only when drivers/pci/setup.c is used */
  48.416 +void pcibios_align_resource(void *, struct resource *, resource_size_t,
  48.417 +				resource_size_t);
  48.418 +void pcibios_update_irq(struct pci_dev *, int irq);
  48.419 +
  48.420 +/* Generic PCI functions used internally */
  48.421 +
  48.422 +extern struct pci_bus *pci_find_bus(int domain, int busnr);
  48.423 +void pci_bus_add_devices(struct pci_bus *bus);
  48.424 +struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
  48.425 +static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
  48.426 +{
  48.427 +	struct pci_bus *root_bus;
  48.428 +	root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
  48.429 +	if (root_bus)
  48.430 +		pci_bus_add_devices(root_bus);
  48.431 +	return root_bus;
  48.432 +}
  48.433 +struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
  48.434 +struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
  48.435 +int pci_scan_slot(struct pci_bus *bus, int devfn);
  48.436 +struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
  48.437 +void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
  48.438 +unsigned int pci_scan_child_bus(struct pci_bus *bus);
  48.439 +int __must_check pci_bus_add_device(struct pci_dev *dev);
  48.440 +void pci_read_bridge_bases(struct pci_bus *child);
  48.441 +struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
  48.442 +int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
  48.443 +extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
  48.444 +extern void pci_dev_put(struct pci_dev *dev);
  48.445 +extern void pci_remove_bus(struct pci_bus *b);
  48.446 +extern void pci_remove_bus_device(struct pci_dev *dev);
  48.447 +extern void pci_stop_bus_device(struct pci_dev *dev);
  48.448 +void pci_setup_cardbus(struct pci_bus *bus);
  48.449 +extern void pci_sort_breadthfirst(void);
  48.450 +
  48.451 +/* Generic PCI functions exported to card drivers */
  48.452 +
  48.453 +struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
  48.454 +struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
  48.455 +struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
  48.456 +int pci_find_capability (struct pci_dev *dev, int cap);
  48.457 +int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
  48.458 +int pci_find_ext_capability (struct pci_dev *dev, int cap);
  48.459 +struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
  48.460 +
  48.461 +struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
  48.462 +				struct pci_dev *from);
  48.463 +struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
  48.464 +				struct pci_dev *from);
  48.465 +
  48.466 +struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
  48.467 +				unsigned int ss_vendor, unsigned int ss_device,
  48.468 +				struct pci_dev *from);
  48.469 +struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
  48.470 +struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
  48.471 +struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
  48.472 +int pci_dev_present(const struct pci_device_id *ids);
  48.473 +
  48.474 +int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
  48.475 +int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
  48.476 +int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
  48.477 +int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
  48.478 +int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
  48.479 +int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
  48.480 +
  48.481 +static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
  48.482 +{
  48.483 +	return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
  48.484 +}
  48.485 +static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
  48.486 +{
  48.487 +	return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
  48.488 +}
  48.489 +static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
  48.490 +{
  48.491 +	return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
  48.492 +}
  48.493 +static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
  48.494 +{
  48.495 +	return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
  48.496 +}
  48.497 +static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
  48.498 +{
  48.499 +	return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
  48.500 +}
  48.501 +static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
  48.502 +{
  48.503 +	return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
  48.504 +}
  48.505 +
  48.506 +int __must_check pci_enable_device(struct pci_dev *dev);
  48.507 +int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
  48.508 +void pci_disable_device(struct pci_dev *dev);
  48.509 +void pci_set_master(struct pci_dev *dev);
  48.510 +#define HAVE_PCI_SET_MWI
  48.511 +int __must_check pci_set_mwi(struct pci_dev *dev);
  48.512 +void pci_clear_mwi(struct pci_dev *dev);
  48.513 +void pci_intx(struct pci_dev *dev, int enable);
  48.514 +int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
  48.515 +int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
  48.516 +void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
  48.517 +int __must_check pci_assign_resource(struct pci_dev *dev, int i);
  48.518 +int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
  48.519 +void pci_restore_bars(struct pci_dev *dev);
  48.520 +
  48.521 +/* ROM control related routines */
  48.522 +void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
  48.523 +void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
  48.524 +void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
  48.525 +void pci_remove_rom(struct pci_dev *pdev);
  48.526 +
  48.527 +/* Power management related routines */
  48.528 +int pci_save_state(struct pci_dev *dev);
  48.529 +int pci_restore_state(struct pci_dev *dev);
  48.530 +int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
  48.531 +pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
  48.532 +int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
  48.533 +
  48.534 +/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
  48.535 +void pci_bus_assign_resources(struct pci_bus *bus);
  48.536 +void pci_bus_size_bridges(struct pci_bus *bus);
  48.537 +int pci_claim_resource(struct pci_dev *, int);
  48.538 +void pci_assign_unassigned_resources(void);
  48.539 +void pdev_enable_device(struct pci_dev *);
  48.540 +void pdev_sort_resources(struct pci_dev *, struct resource_list *);
  48.541 +void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
  48.542 +		    int (*)(struct pci_dev *, u8, u8));
  48.543 +#define HAVE_PCI_REQ_REGIONS	2
  48.544 +int __must_check pci_request_regions(struct pci_dev *, const char *);
  48.545 +void pci_release_regions(struct pci_dev *);
  48.546 +int __must_check pci_request_region(struct pci_dev *, int, const char *);
  48.547 +void pci_release_region(struct pci_dev *, int);
  48.548 +
  48.549 +/* drivers/pci/bus.c */
  48.550 +int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
  48.551 +			struct resource *res, resource_size_t size,
  48.552 +			resource_size_t align, resource_size_t min,
  48.553 +			unsigned int type_mask,
  48.554 +			void (*alignf)(void *, struct resource *,
  48.555 +				resource_size_t, resource_size_t),
  48.556 +			void *alignf_data);
  48.557 +void pci_enable_bridges(struct pci_bus *bus);
  48.558 +
  48.559 +/* Proper probing supporting hot-pluggable devices */
  48.560 +int __must_check __pci_register_driver(struct pci_driver *, struct module *);
  48.561 +static inline int __must_check pci_register_driver(struct pci_driver *driver)
  48.562 +{
  48.563 +	return __pci_register_driver(driver, THIS_MODULE);
  48.564 +}
  48.565 +
  48.566 +void pci_unregister_driver(struct pci_driver *);
  48.567 +void pci_remove_behind_bridge(struct pci_dev *);
  48.568 +struct pci_driver *pci_dev_driver(const struct pci_dev *);
  48.569 +const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
  48.570 +const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
  48.571 +int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
  48.572 +
  48.573 +void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
  48.574 +		  void *userdata);
  48.575 +int pci_cfg_space_size(struct pci_dev *dev);
  48.576 +unsigned char pci_bus_max_busnr(struct pci_bus* bus);
  48.577 +
  48.578 +/* kmem_cache style wrapper around pci_alloc_consistent() */
  48.579 +
  48.580 +#include <linux/dmapool.h>
  48.581 +
  48.582 +#define	pci_pool dma_pool
  48.583 +#define pci_pool_create(name, pdev, size, align, allocation) \
  48.584 +		dma_pool_create(name, &pdev->dev, size, align, allocation)
  48.585 +#define	pci_pool_destroy(pool) dma_pool_destroy(pool)
  48.586 +#define	pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
  48.587 +#define	pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
  48.588 +
  48.589 +enum pci_dma_burst_strategy {
  48.590 +	PCI_DMA_BURST_INFINITY,	/* make bursts as large as possible,
  48.591 +				   strategy_parameter is N/A */
  48.592 +	PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
  48.593 +				   byte boundaries */
  48.594 +	PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
  48.595 +				   strategy_parameter byte boundaries */
  48.596 +};
  48.597 +
  48.598 +#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
  48.599 +extern struct pci_dev *isa_bridge;
  48.600 +#endif
  48.601 +
  48.602 +struct msix_entry {
  48.603 +	u16 	vector;	/* kernel uses to write allocated vector */
  48.604 +	u16	entry;	/* driver uses to specify entry, OS writes */
  48.605 +};
  48.606 +
  48.607 +
  48.608 +#ifndef CONFIG_PCI_MSI
  48.609 +static inline void pci_scan_msi_device(struct pci_dev *dev) {}
  48.610 +static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
  48.611 +static inline void pci_disable_msi(struct pci_dev *dev) {}
  48.612 +static inline int pci_enable_msix(struct pci_dev* dev,
  48.613 +	struct msix_entry *entries, int nvec) {return -1;}
  48.614 +static inline void pci_disable_msix(struct pci_dev *dev) {}
  48.615 +static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
  48.616 +#else
  48.617 +extern void pci_scan_msi_device(struct pci_dev *dev);
  48.618 +extern int pci_enable_msi(struct pci_dev *dev);
  48.619 +extern void pci_disable_msi(struct pci_dev *dev);
  48.620 +extern int pci_enable_msix(struct pci_dev* dev,
  48.621 +	struct msix_entry *entries, int nvec);
  48.622 +extern void pci_disable_msix(struct pci_dev *dev);
  48.623 +extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
  48.624 +#endif
  48.625 +
  48.626 +#ifdef CONFIG_HT_IRQ
  48.627 +/* The functions a driver should call */
  48.628 +int  ht_create_irq(struct pci_dev *dev, int idx);
  48.629 +void ht_destroy_irq(unsigned int irq);
  48.630 +#endif /* CONFIG_HT_IRQ */
  48.631 +
  48.632 +extern void pci_block_user_cfg_access(struct pci_dev *dev);
  48.633 +extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
  48.634 +
  48.635 +/*
  48.636 + * PCI domain support.  Sometimes called PCI segment (eg by ACPI),
  48.637 + * a PCI domain is defined to be a set of PCI busses which share
  48.638 + * configuration space.
  48.639 + */
  48.640 +#ifndef CONFIG_PCI_DOMAINS
  48.641 +static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
  48.642 +static inline int pci_proc_domain(struct pci_bus *bus)
  48.643 +{
  48.644 +	return 0;
  48.645 +}
  48.646 +#endif
  48.647 +
  48.648 +#else /* CONFIG_PCI is not enabled */
  48.649 +
  48.650 +/*
  48.651 + *  If the system does not have PCI, clearly these return errors.  Define
  48.652 + *  these as simple inline functions to avoid hair in drivers.
  48.653 + */
  48.654 +
  48.655 +#define _PCI_NOP(o,s,t) \
  48.656 +	static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
  48.657 +		{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
  48.658 +#define _PCI_NOP_ALL(o,x)	_PCI_NOP(o,byte,u8 x) \
  48.659 +				_PCI_NOP(o,word,u16 x) \
  48.660 +				_PCI_NOP(o,dword,u32 x)
  48.661 +_PCI_NOP_ALL(read, *)
  48.662 +_PCI_NOP_ALL(write,)
  48.663 +
  48.664 +static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
  48.665 +{ return NULL; }
  48.666 +
  48.667 +static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
  48.668 +{ return NULL; }
  48.669 +
  48.670 +static inline struct pci_dev *pci_get_device(unsigned int vendor,
  48.671 +				unsigned int device, struct pci_dev *from)
  48.672 +{ return NULL; }
  48.673 +
  48.674 +static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
  48.675 +				unsigned int device, struct pci_dev *from)
  48.676 +{ return NULL; }
  48.677 +
  48.678 +static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
  48.679 +unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
  48.680 +{ return NULL; }
  48.681 +
  48.682 +static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
  48.683 +{ return NULL; }
  48.684 +
  48.685 +#define pci_dev_present(ids)	(0)
  48.686 +#define pci_dev_put(dev)	do { } while (0)
  48.687 +
  48.688 +static inline void pci_set_master(struct pci_dev *dev) { }
  48.689 +static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
  48.690 +static inline void pci_disable_device(struct pci_dev *dev) { }
  48.691 +static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
  48.692 +static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
  48.693 +static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
  48.694 +static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
  48.695 +static inline void pci_unregister_driver(struct pci_driver *drv) { }
  48.696 +static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
  48.697 +static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
  48.698 +static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
  48.699 +static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
  48.700 +
  48.701 +/* Power management related routines */
  48.702 +static inline int pci_save_state(struct pci_dev *dev) { return 0; }
  48.703 +static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
  48.704 +static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
  48.705 +static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
  48.706 +static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
  48.707 +
  48.708 +#define	isa_bridge	((struct pci_dev *)NULL)
  48.709 +
  48.710 +#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
  48.711 +
  48.712 +static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
  48.713 +static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
  48.714 +
  48.715 +#endif /* CONFIG_PCI */
  48.716 +
  48.717 +/* Include architecture-dependent settings and functions */
  48.718 +
  48.719 +#include <asm/pci.h>
  48.720 +
  48.721 +/* these helpers provide future and backwards compatibility
  48.722 + * for accessing popular PCI BAR info */
  48.723 +#define pci_resource_start(dev,bar)   ((dev)->resource[(bar)].start)
  48.724 +#define pci_resource_end(dev,bar)     ((dev)->resource[(bar)].end)
  48.725 +#define pci_resource_flags(dev,bar)   ((dev)->resource[(bar)].flags)
  48.726 +#define pci_resource_len(dev,bar) \
  48.727 +	((pci_resource_start((dev),(bar)) == 0 &&	\
  48.728 +	  pci_resource_end((dev),(bar)) ==		\
  48.729 +	  pci_resource_start((dev),(bar))) ? 0 :	\
  48.730 +	  						\
  48.731 +	 (pci_resource_end((dev),(bar)) -		\
  48.732 +	  pci_resource_start((dev),(bar)) + 1))
  48.733 +
  48.734 +/* Similar to the helpers above, these manipulate per-pci_dev
  48.735 + * driver-specific data.  They are really just a wrapper around
  48.736 + * the generic device structure functions of these calls.
  48.737 + */
  48.738 +static inline void *pci_get_drvdata (struct pci_dev *pdev)
  48.739 +{
  48.740 +	return dev_get_drvdata(&pdev->dev);
  48.741 +}
  48.742 +
  48.743 +static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
  48.744 +{
  48.745 +	dev_set_drvdata(&pdev->dev, data);
  48.746 +}
  48.747 +
  48.748 +/* If you want to know what to call your pci_dev, ask this function.
  48.749 + * Again, it's a wrapper around the generic device.
  48.750 + */
  48.751 +static inline char *pci_name(struct pci_dev *pdev)
  48.752 +{
  48.753 +	return pdev->dev.bus_id;
  48.754 +}
  48.755 +
  48.756 +
  48.757 +/* Some archs don't want to expose struct resource to userland as-is
  48.758 + * in sysfs and /proc
  48.759 + */
  48.760 +#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
  48.761 +static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
  48.762 +                const struct resource *rsrc, resource_size_t *start,
  48.763 +		resource_size_t *end)
  48.764 +{
  48.765 +	*start = rsrc->start;
  48.766 +	*end = rsrc->end;
  48.767 +}
  48.768 +#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
  48.769 +
  48.770 +
  48.771 +/*
  48.772 + *  The world is not perfect and supplies us with broken PCI devices.
  48.773 + *  For at least a part of these bugs we need a work-around, so both
  48.774 + *  generic (drivers/pci/quirks.c) and per-architecture code can define
  48.775 + *  fixup hooks to be called for particular buggy devices.
  48.776 + */
  48.777 +
  48.778 +struct pci_fixup {
  48.779 +	u16 vendor, device;	/* You can use PCI_ANY_ID here of course */
  48.780 +	void (*hook)(struct pci_dev *dev);
  48.781 +};
  48.782 +
  48.783 +enum pci_fixup_pass {
  48.784 +	pci_fixup_early,	/* Before probing BARs */
  48.785 +	pci_fixup_header,	/* After reading configuration header */
  48.786 +	pci_fixup_final,	/* Final phase of device fixups */
  48.787 +	pci_fixup_enable,	/* pci_enable_device() time */
  48.788 +};
  48.789 +
  48.790 +/* Anonymous variables would be nice... */
  48.791 +#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook)	\
  48.792 +	static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
  48.793 +	__attribute__((__section__(#section))) = { vendor, device, hook };
  48.794 +#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)			\
  48.795 +	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,			\
  48.796 +			vendor##device##hook, vendor, device, hook)
  48.797 +#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook)			\
  48.798 +	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header,			\
  48.799 +			vendor##device##hook, vendor, device, hook)
  48.800 +#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook)			\
  48.801 +	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final,			\
  48.802 +			vendor##device##hook, vendor, device, hook)
  48.803 +#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook)			\
  48.804 +	DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable,			\
  48.805 +			vendor##device##hook, vendor, device, hook)
  48.806 +
  48.807 +
  48.808 +void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
  48.809 +
  48.810 +extern int pci_pci_problems;
  48.811 +#define PCIPCI_FAIL		1	/* No PCI PCI DMA */
  48.812 +#define PCIPCI_TRITON		2
  48.813 +#define PCIPCI_NATOMA		4
  48.814 +#define PCIPCI_VIAETBF		8
  48.815 +#define PCIPCI_VSFX		16
  48.816 +#define PCIPCI_ALIMAGIK		32	/* Need low latency setting */
  48.817 +#define PCIAGP_FAIL		64	/* No PCI to AGP DMA */
  48.818 +
  48.819 +#endif /* __KERNEL__ */
  48.820 +#endif /* LINUX_PCI_H */
    49.1 --- a/xen/include/asm-ia64/linux/README.origin	Tue Dec 12 15:25:02 2006 -0700
    49.2 +++ b/xen/include/asm-ia64/linux/README.origin	Wed Dec 13 11:08:40 2006 -0700
    49.3 @@ -24,3 +24,15 @@ time.h			-> linux/include/linux/time.h
    49.4  timex.h			-> linux/include/linux/timex.h
    49.5  topology.h		-> linux/include/linux/topology.h
    49.6  wait.h			-> linux/include/linux/wait.h
    49.7 +
    49.8 +# The files below are from Linux-2.6.19
    49.9 +completion.h		-> linux/include/linux/completion.h
   49.10 +ioport.h		-> linux/include/linux/ioport.h
   49.11 +klist.h			-> linux/include/linux/klist.h
   49.12 +kref.h			-> linux/include/linux/kref.h
   49.13 +mod_devicetable.h	-> linux/include/linux/mod_devicetable.h
   49.14 +pci_ids.h		-> linux/include/linux/pci_ids.h
   49.15 +pci_regs.h		-> linux/include/linux/pci_regs.h
   49.16 +pm.h			-> linux/include/linux/pm.h
   49.17 +sysfs.h			-> linux/include/linux/sysfs.h
   49.18 +
    50.1 --- a/xen/include/asm-ia64/linux/asm/README.origin	Tue Dec 12 15:25:02 2006 -0700
    50.2 +++ b/xen/include/asm-ia64/linux/asm/README.origin	Wed Dec 13 11:08:40 2006 -0700
    50.3 @@ -41,3 +41,6 @@ topology.h		-> linux/include/asm-ia64/to
    50.4  unaligned.h		-> linux/include/asm-ia64/unaligned.h
    50.5  unistd.h		-> linux/include/asm-ia64/unistd.h
    50.6  unwind.h		-> linux/include/asm-ia64/unwind.h
    50.7 +
    50.8 +# The files below are from Linux-2.6.19
    50.9 +machvec_init.h		-> linux/include/asm-ia64/machvec_init.h
    51.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    51.2 +++ b/xen/include/asm-ia64/linux/asm/machvec_init.h	Wed Dec 13 11:08:40 2006 -0700
    51.3 @@ -0,0 +1,32 @@
    51.4 +#include <asm/machvec.h>
    51.5 +
    51.6 +extern ia64_mv_send_ipi_t ia64_send_ipi;
    51.7 +extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
    51.8 +extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
    51.9 +extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
   51.10 +extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
   51.11 +extern ia64_mv_pci_legacy_write_t ia64_pci_legacy_write;
   51.12 +
   51.13 +extern ia64_mv_inb_t __ia64_inb;
   51.14 +extern ia64_mv_inw_t __ia64_inw;
   51.15 +extern ia64_mv_inl_t __ia64_inl;
   51.16 +extern ia64_mv_outb_t __ia64_outb;
   51.17 +extern ia64_mv_outw_t __ia64_outw;
   51.18 +extern ia64_mv_outl_t __ia64_outl;
   51.19 +extern ia64_mv_mmiowb_t __ia64_mmiowb;
   51.20 +extern ia64_mv_readb_t __ia64_readb;
   51.21 +extern ia64_mv_readw_t __ia64_readw;
   51.22 +extern ia64_mv_readl_t __ia64_readl;
   51.23 +extern ia64_mv_readq_t __ia64_readq;
   51.24 +extern ia64_mv_readb_t __ia64_readb_relaxed;
   51.25 +extern ia64_mv_readw_t __ia64_readw_relaxed;
   51.26 +extern ia64_mv_readl_t __ia64_readl_relaxed;
   51.27 +extern ia64_mv_readq_t __ia64_readq_relaxed;
   51.28 +
   51.29 +#define MACHVEC_HELPER(name)									\
   51.30 + struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec")))	\
   51.31 +	= MACHVEC_INIT(name);
   51.32 +
   51.33 +#define MACHVEC_DEFINE(name)	MACHVEC_HELPER(name)
   51.34 +
   51.35 +MACHVEC_DEFINE(MACHVEC_PLATFORM_NAME)
    52.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    52.2 +++ b/xen/include/asm-ia64/linux/asm/sn/README.origin	Wed Dec 13 11:08:40 2006 -0700
    52.3 @@ -0,0 +1,23 @@
    52.4 +# Source files in this directory are identical copies of linux-2.6.19 files:
    52.5 +# 
    52.6 +# NOTE: DO NOT commit changes to these files!   If a file
    52.7 +# needs to be changed, move it to ../linux-xen and follow
    52.8 +# the instructions in the README there.
    52.9 +
   52.10 +geo.h			-> linux/include/asm-ia64/sn/geo.h
   52.11 +klconfig.h		-> linux/include/asm-ia64/sn/klconfig.h
   52.12 +l1.h			-> linux/include/asm-ia64/sn/l1.h
   52.13 +leds.h			-> linux/include/asm-ia64/sn/leds.h
   52.14 +module.h		-> linux/include/asm-ia64/sn/module.h
   52.15 +pcibus_provider_defs.h	-> linux/include/asm-ia64/sn/pcibus_provider_defs.h
   52.16 +pcidev.h		-> linux/include/asm-ia64/sn/pcidev.h
   52.17 +pda.h			-> linux/include/asm-ia64/sn/pda.h
   52.18 +pic.h			-> linux/include/asm-ia64/sn/pic.h
   52.19 +shub_mmr.h		-> linux/include/asm-ia64/sn/shub_mmr.h
   52.20 +shubio.h		-> linux/include/asm-ia64/sn/shubio.h
   52.21 +simulator.h		-> linux/include/asm-ia64/sn/simulator.h
   52.22 +sn_cpuid.h		-> linux/include/asm-ia64/sn/sn_cpuid.h
   52.23 +sn_feature_sets.h	-> linux/include/asm-ia64/sn/sn_feature_sets.h
   52.24 +tiocp.h			-> linux/include/asm-ia64/sn/tiocp.h
   52.25 +xbow.h			-> linux/arch/ia64/sn/include/xtalk/xbow.h
   52.26 +xwidgetdev.h		-> linux/arch/ia64/sn/include/xtalk/xwidgetdev.h
    53.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    53.2 +++ b/xen/include/asm-ia64/linux/asm/sn/geo.h	Wed Dec 13 11:08:40 2006 -0700
    53.3 @@ -0,0 +1,132 @@
    53.4 +/*
    53.5 + * This file is subject to the terms and conditions of the GNU General Public
    53.6 + * License.  See the file "COPYING" in the main directory of this archive
    53.7 + * for more details.
    53.8 + *
    53.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   53.10 + */
   53.11 +
   53.12 +#ifndef _ASM_IA64_SN_GEO_H
   53.13 +#define _ASM_IA64_SN_GEO_H
   53.14 +
   53.15 +/* The geoid_t implementation below is based loosely on the pcfg_t
   53.16 +   implementation in sys/SN/promcfg.h. */
   53.17 +
   53.18 +/* Type declaractions */
   53.19 +
   53.20 +/* Size of a geoid_t structure (must be before decl. of geoid_u) */
   53.21 +#define GEOID_SIZE	8	/* Would 16 be better?  The size can
   53.22 +				   be different on different platforms. */
   53.23 +
   53.24 +#define MAX_SLOTS	0xf	/* slots per module */
   53.25 +#define MAX_SLABS	0xf	/* slabs per slot */
   53.26 +
   53.27 +typedef unsigned char	geo_type_t;
   53.28 +
   53.29 +/* Fields common to all substructures */
   53.30 +typedef struct geo_common_s {
   53.31 +    moduleid_t	module;		/* The module (box) this h/w lives in */
   53.32 +    geo_type_t	type;		/* What type of h/w is named by this geoid_t */
   53.33 +    slabid_t	slab:4;		/* slab (ASIC), 0 .. 15 within slot */
   53.34 +    slotid_t	slot:4;		/* slot (Blade), 0 .. 15 within module */
   53.35 +} geo_common_t;
   53.36 +
   53.37 +/* Additional fields for particular types of hardware */
   53.38 +typedef struct geo_node_s {
   53.39 +    geo_common_t	common;		/* No additional fields needed */
   53.40 +} geo_node_t;
   53.41 +
   53.42 +typedef struct geo_rtr_s {
   53.43 +    geo_common_t	common;		/* No additional fields needed */
   53.44 +} geo_rtr_t;
   53.45 +
   53.46 +typedef struct geo_iocntl_s {
   53.47 +    geo_common_t	common;		/* No additional fields needed */
   53.48 +} geo_iocntl_t;
   53.49 +
   53.50 +typedef struct geo_pcicard_s {
   53.51 +    geo_iocntl_t	common;
   53.52 +    char		bus;	/* Bus/widget number */
   53.53 +    char		slot;	/* PCI slot number */
   53.54 +} geo_pcicard_t;
   53.55 +
   53.56 +/* Subcomponents of a node */
   53.57 +typedef struct geo_cpu_s {
   53.58 +    geo_node_t	node;
   53.59 +    char	slice;		/* Which CPU on the node */
   53.60 +} geo_cpu_t;
   53.61 +
   53.62 +typedef struct geo_mem_s {
   53.63 +    geo_node_t	node;
   53.64 +    char	membus;		/* The memory bus on the node */
   53.65 +    char	memslot;	/* The memory slot on the bus */
   53.66 +} geo_mem_t;
   53.67 +
   53.68 +
   53.69 +typedef union geoid_u {
   53.70 +    geo_common_t	common;
   53.71 +    geo_node_t		node;
   53.72 +    geo_iocntl_t	iocntl;
   53.73 +    geo_pcicard_t	pcicard;
   53.74 +    geo_rtr_t		rtr;
   53.75 +    geo_cpu_t		cpu;
   53.76 +    geo_mem_t		mem;
   53.77 +    char		padsize[GEOID_SIZE];
   53.78 +} geoid_t;
   53.79 +
   53.80 +
   53.81 +/* Preprocessor macros */
   53.82 +
   53.83 +#define GEO_MAX_LEN	48	/* max. formatted length, plus some pad:
   53.84 +				   module/001c07/slab/5/node/memory/2/slot/4 */
   53.85 +
   53.86 +/* Values for geo_type_t */
   53.87 +#define GEO_TYPE_INVALID	0
   53.88 +#define GEO_TYPE_MODULE		1
   53.89 +#define GEO_TYPE_NODE		2
   53.90 +#define GEO_TYPE_RTR		3
   53.91 +#define GEO_TYPE_IOCNTL		4
   53.92 +#define GEO_TYPE_IOCARD		5
   53.93 +#define GEO_TYPE_CPU		6
   53.94 +#define GEO_TYPE_MEM		7
   53.95 +#define GEO_TYPE_MAX		(GEO_TYPE_MEM+1)
   53.96 +
   53.97 +/* Parameter for hwcfg_format_geoid_compt() */
   53.98 +#define GEO_COMPT_MODULE	1
   53.99 +#define GEO_COMPT_SLAB		2
  53.100 +#define GEO_COMPT_IOBUS		3
  53.101 +#define GEO_COMPT_IOSLOT	4
  53.102 +#define GEO_COMPT_CPU		5
  53.103 +#define GEO_COMPT_MEMBUS	6
  53.104 +#define GEO_COMPT_MEMSLOT	7
  53.105 +
  53.106 +#define GEO_INVALID_STR		"<invalid>"
  53.107 +
  53.108 +#define INVALID_NASID           ((nasid_t)-1)
  53.109 +#define INVALID_CNODEID         ((cnodeid_t)-1)
  53.110 +#define INVALID_PNODEID         ((pnodeid_t)-1)
  53.111 +#define INVALID_SLAB            (slabid_t)-1
  53.112 +#define INVALID_SLOT            (slotid_t)-1
  53.113 +#define INVALID_MODULE          ((moduleid_t)-1)
  53.114 +
  53.115 +static inline slabid_t geo_slab(geoid_t g)
  53.116 +{
  53.117 +	return (g.common.type == GEO_TYPE_INVALID) ?
  53.118 +		INVALID_SLAB : g.common.slab;
  53.119 +}
  53.120 +
  53.121 +static inline slotid_t geo_slot(geoid_t g)
  53.122 +{
  53.123 +	return (g.common.type == GEO_TYPE_INVALID) ?
  53.124 +		INVALID_SLOT : g.common.slot;
  53.125 +}
  53.126 +
  53.127 +static inline moduleid_t geo_module(geoid_t g)
  53.128 +{
  53.129 +	return (g.common.type == GEO_TYPE_INVALID) ?
  53.130 +		INVALID_MODULE : g.common.module;
  53.131 +}
  53.132 +
  53.133 +extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
  53.134 +
  53.135 +#endif /* _ASM_IA64_SN_GEO_H */
    54.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    54.2 +++ b/xen/include/asm-ia64/linux/asm/sn/klconfig.h	Wed Dec 13 11:08:40 2006 -0700
    54.3 @@ -0,0 +1,246 @@
    54.4 +/*
    54.5 + * This file is subject to the terms and conditions of the GNU General Public
    54.6 + * License.  See the file "COPYING" in the main directory of this archive
    54.7 + * for more details.
    54.8 + *
    54.9 + * Derived from IRIX <sys/SN/klconfig.h>.
   54.10 + *
   54.11 + * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc.  All Rights Reserved.
   54.12 + * Copyright (C) 1999 by Ralf Baechle
   54.13 + */
   54.14 +#ifndef _ASM_IA64_SN_KLCONFIG_H
   54.15 +#define _ASM_IA64_SN_KLCONFIG_H
   54.16 +
   54.17 +/*
   54.18 + * The KLCONFIG structures store info about the various BOARDs found
   54.19 + * during Hardware Discovery. In addition, it stores info about the
   54.20 + * components found on the BOARDs.
   54.21 + */
   54.22 +
   54.23 +typedef s32 klconf_off_t;
   54.24 +
   54.25 +
   54.26 +/* Functions/macros needed to use this structure */
   54.27 +
   54.28 +typedef struct kl_config_hdr {
   54.29 +	char		pad[20];
   54.30 +	klconf_off_t	ch_board_info;	/* the link list of boards */
   54.31 +	char		pad0[88];
   54.32 +} kl_config_hdr_t;
   54.33 +
   54.34 +
   54.35 +#define NODE_OFFSET_TO_LBOARD(nasid,off)        (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
   54.36 +
   54.37 +/*
   54.38 + * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
   54.39 + * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to 
   54.40 + * the LOCAL/current NODE. REMOTE means it is attached to a different
   54.41 + * node.(TBD - Need a way to treat ROUTER boards.)
   54.42 + *
   54.43 + * There are 2 different structures to represent these boards -
   54.44 + * lboard - Local board, rboard - remote board. These 2 structures
   54.45 + * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
   54.46 + * Figure below). The first byte of the rboard or lboard structure
   54.47 + * is used to find out its type - no unions are used.
   54.48 + * If it is a lboard, then the config info of this board will be found
   54.49 + * on the local node. (LOCAL NODE BASE + offset value gives pointer to 
   54.50 + * the structure.
   54.51 + * If it is a rboard, the local structure contains the node number
   54.52 + * and the offset of the beginning of the LINKED LIST on the remote node.
   54.53 + * The details of the hardware on a remote node can be built locally,
   54.54 + * if required, by reading the LINKED LIST on the remote node and 
   54.55 + * ignoring all the rboards on that node.
   54.56 + *
   54.57 + * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the 
   54.58 + * First board info on the remote node. The remote node list is 
   54.59 + * traversed as the local list, using the REMOTE BASE ADDRESS and not
   54.60 + * the local base address and ignoring all rboard values.
   54.61 + *
   54.62 + * 
   54.63 + KLCONFIG
   54.64 +
   54.65 + +------------+      +------------+      +------------+      +------------+
   54.66 + |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
   54.67 + +------------+  |   +------------+  |   +------------+  |   +------------+
   54.68 + | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
   54.69 + +------------+  |   +------------+  |   +------------+  |   +------------+
   54.70 + | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
   54.71 + +------------+      +------------+      +------------+      +------------+
   54.72 +
   54.73 +
   54.74 + +------------+
   54.75 + | board info |
   54.76 + +------------+       +--------------------------------+
   54.77 + | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
   54.78 + +------------+       +--------------------------------+
   54.79 + | compt 2    |--+
   54.80 + +------------+  |    +--------------------------------+
   54.81 + |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
   54.82 + +------------+       +--------------------------------+
   54.83 + | errinfo    |--+
   54.84 + +------------+  |    +--------------------------------+
   54.85 +                 +--->|r/l brd errinfo,compt err flags |
   54.86 +                      +--------------------------------+
   54.87 +
   54.88 + *
   54.89 + * Each BOARD consists of COMPONENTs and the BOARD structure has 
   54.90 + * pointers (offsets) to its COMPONENT structure.
   54.91 + * The COMPONENT structure has version info, size and speed info, revision,
   54.92 + * error info and the NIC info. This structure can accommodate any
   54.93 + * BOARD with arbitrary COMPONENT composition.
   54.94 + *
   54.95 + * The ERRORINFO part of each BOARD has error information
   54.96 + * that describes errors about the BOARD itself. It also has flags to
   54.97 + * indicate the COMPONENT(s) on the board that have errors. The error 
   54.98 + * information specific to the COMPONENT is present in the respective 
   54.99 + * COMPONENT structure.
  54.100 + *
  54.101 + * The ERRORINFO structure is also treated like a COMPONENT, ie. the 
  54.102 + * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
  54.103 + * structure also has a pointer to the ERRORINFO structure. This is 
  54.104 + * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
  54.105 + * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where 
  54.106 + * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
  54.107 + * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info 
  54.108 + * which is present on the REMOTE NODE.(TBD)
  54.109 + * REMOTE ERRINFO can be stored on any of the nearest nodes 
  54.110 + * or on all the nearest nodes.(TBD)
  54.111 + * Like BOARD structures, REMOTE ERRINFO structures can be built locally
  54.112 + * using the rboard errinfo pointer.
  54.113 + *
  54.114 + * In order to get useful information from this Data organization, a set of
  54.115 + * interface routines are provided (TBD). The important thing to remember while
  54.116 + * manipulating the structures, is that, the NODE number information should
  54.117 + * be used. If the NODE is non-zero (remote) then each offset should
  54.118 + * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. 
  54.119 + * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
  54.120 + * 
  54.121 + * Note that these structures do not provide much info about connectivity.
  54.122 + * That info will be part of HWGRAPH, which is an extension of the cfg_t
  54.123 + * data structure. (ref IP27prom/cfg.h) It has to be extended to include
  54.124 + * the IO part of the Network(TBD).
  54.125 + *
  54.126 + * The data structures below define the above concepts.
  54.127 + */
  54.128 +
  54.129 +
  54.130 +/*
  54.131 + * BOARD classes
  54.132 + */
  54.133 +
  54.134 +#define KLCLASS_MASK	0xf0   
  54.135 +#define KLCLASS_NONE	0x00
  54.136 +#define KLCLASS_NODE	0x10             /* CPU, Memory and HUB board */
  54.137 +#define KLCLASS_CPU	KLCLASS_NODE	
  54.138 +#define KLCLASS_IO	0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI 
  54.139 +					    and the non-graphics widget boards */
  54.140 +#define KLCLASS_ROUTER	0x30             /* Router board */
  54.141 +#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
  54.142 +                                            so that we can record error info */
  54.143 +#define KLCLASS_IOBRICK	0x70		/* IP35 iobrick */
  54.144 +#define KLCLASS_MAX	8		/* Bump this if a new CLASS is added */
  54.145 +
  54.146 +#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
  54.147 +
  54.148 +
  54.149 +/*
  54.150 + * board types
  54.151 + */
  54.152 +
  54.153 +#define KLTYPE_MASK	0x0f
  54.154 +#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
  54.155 +
  54.156 +#define KLTYPE_SNIA	(KLCLASS_CPU | 0x1)
  54.157 +#define KLTYPE_TIO	(KLCLASS_CPU | 0x2)
  54.158 +
  54.159 +#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
  54.160 +#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
  54.161 +#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
  54.162 +
  54.163 +#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
  54.164 +
  54.165 +#define KLTYPE_IOBRICK		(KLCLASS_IOBRICK | 0x0)
  54.166 +#define KLTYPE_NBRICK		(KLCLASS_IOBRICK | 0x4)
  54.167 +#define KLTYPE_PXBRICK		(KLCLASS_IOBRICK | 0x6)
  54.168 +#define KLTYPE_IXBRICK		(KLCLASS_IOBRICK | 0x7)
  54.169 +#define KLTYPE_CGBRICK		(KLCLASS_IOBRICK | 0x8)
  54.170 +#define KLTYPE_OPUSBRICK	(KLCLASS_IOBRICK | 0x9)
  54.171 +#define KLTYPE_SABRICK          (KLCLASS_IOBRICK | 0xa)
  54.172 +#define KLTYPE_IABRICK		(KLCLASS_IOBRICK | 0xb)
  54.173 +#define KLTYPE_PABRICK          (KLCLASS_IOBRICK | 0xc)
  54.174 +#define KLTYPE_GABRICK		(KLCLASS_IOBRICK | 0xd)
  54.175 +
  54.176 +
  54.177 +/* 
  54.178 + * board structures
  54.179 + */
  54.180 +
  54.181 +#define MAX_COMPTS_PER_BRD 24
  54.182 +
  54.183 +typedef struct lboard_s {
  54.184 +	klconf_off_t 	brd_next_any;     /* Next BOARD */
  54.185 +	unsigned char 	struct_type;      /* type of structure, local or remote */
  54.186 +	unsigned char 	brd_type;         /* type+class */
  54.187 +	unsigned char 	brd_sversion;     /* version of this structure */
  54.188 +        unsigned char 	brd_brevision;    /* board revision */
  54.189 +        unsigned char 	brd_promver;      /* board prom version, if any */
  54.190 + 	unsigned char 	brd_flags;        /* Enabled, Disabled etc */
  54.191 +	unsigned char 	brd_slot;         /* slot number */
  54.192 +	unsigned short	brd_debugsw;      /* Debug switches */
  54.193 +	geoid_t		brd_geoid;	  /* geo id */
  54.194 +	partid_t 	brd_partition;    /* Partition number */
  54.195 +        unsigned short 	brd_diagval;      /* diagnostic value */
  54.196 +        unsigned short 	brd_diagparm;     /* diagnostic parameter */
  54.197 +        unsigned char 	brd_inventory;    /* inventory history */
  54.198 +        unsigned char 	brd_numcompts;    /* Number of components */
  54.199 +        nic_t         	brd_nic;          /* Number in CAN */
  54.200 +	nasid_t		brd_nasid;        /* passed parameter */
  54.201 +	klconf_off_t 	brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
  54.202 +	klconf_off_t 	brd_errinfo;      /* Board's error information */
  54.203 +	struct lboard_s *brd_parent;	  /* Logical parent for this brd */
  54.204 +	char            pad0[4];
  54.205 +	unsigned char	brd_confidence;	  /* confidence that the board is bad */
  54.206 +	nasid_t		brd_owner;        /* who owns this board */
  54.207 +	unsigned char 	brd_nic_flags;    /* To handle 8 more NICs */
  54.208 +	char		pad1[24];	  /* future expansion */
  54.209 +	char		brd_name[32];
  54.210 +	nasid_t		brd_next_same_host; /* host of next brd w/same nasid */
  54.211 +	klconf_off_t	brd_next_same;    /* Next BOARD with same nasid */
  54.212 +} lboard_t;
  54.213 +
  54.214 +/*
  54.215 + * Generic info structure. This stores common info about a 
  54.216 + * component.
  54.217 + */
  54.218 + 
  54.219 +typedef struct klinfo_s {                  /* Generic info */
  54.220 +        unsigned char   struct_type;       /* type of this structure */
  54.221 +        unsigned char   struct_version;    /* version of this structure */
  54.222 +        unsigned char   flags;            /* Enabled, disabled etc */
  54.223 +        unsigned char   revision;         /* component revision */
  54.224 +        unsigned short  diagval;          /* result of diagnostics */
  54.225 +        unsigned short  diagparm;         /* diagnostic parameter */
  54.226 +        unsigned char   inventory;        /* previous inventory status */
  54.227 +        unsigned short  partid;		   /* widget part number */
  54.228 +	nic_t 		nic;              /* MUst be aligned properly */
  54.229 +        unsigned char   physid;           /* physical id of component */
  54.230 +        unsigned int    virtid;           /* virtual id as seen by system */
  54.231 +	unsigned char	widid;	          /* Widget id - if applicable */
  54.232 +	nasid_t		nasid;            /* node number - from parent */
  54.233 +	char		pad1;		  /* pad out structure. */
  54.234 +	char		pad2;		  /* pad out structure. */
  54.235 +	void		*data;
  54.236 +        klconf_off_t	errinfo;          /* component specific errors */
  54.237 +        unsigned short  pad3;             /* pci fields have moved over to */
  54.238 +        unsigned short  pad4;             /* klbri_t */
  54.239 +} klinfo_t ;
  54.240 +
  54.241 +
  54.242 +static inline lboard_t *find_lboard_next(lboard_t * brd)
  54.243 +{
  54.244 +	if (brd && brd->brd_next_any)
  54.245 +		return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
  54.246 +        return NULL;
  54.247 +}
  54.248 +
  54.249 +#endif /* _ASM_IA64_SN_KLCONFIG_H */
    55.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    55.2 +++ b/xen/include/asm-ia64/linux/asm/sn/l1.h	Wed Dec 13 11:08:40 2006 -0700
    55.3 @@ -0,0 +1,51 @@
    55.4 +/*
    55.5 + * This file is subject to the terms and conditions of the GNU General Public
    55.6 + * License.  See the file "COPYING" in the main directory of this archive
    55.7 + * for more details.
    55.8 + *
    55.9 + * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
   55.10 + */
   55.11 +
   55.12 +#ifndef _ASM_IA64_SN_L1_H
   55.13 +#define _ASM_IA64_SN_L1_H
   55.14 +
   55.15 +/* brick type response codes */
   55.16 +#define L1_BRICKTYPE_PX         0x23            /* # */
   55.17 +#define L1_BRICKTYPE_PE         0x25            /* % */
   55.18 +#define L1_BRICKTYPE_N_p0       0x26            /* & */
   55.19 +#define L1_BRICKTYPE_IP45       0x34            /* 4 */
   55.20 +#define L1_BRICKTYPE_IP41       0x35            /* 5 */
   55.21 +#define L1_BRICKTYPE_TWISTER    0x36            /* 6 */ /* IP53 & ROUTER */
   55.22 +#define L1_BRICKTYPE_IX         0x3d            /* = */
   55.23 +#define L1_BRICKTYPE_IP34       0x61            /* a */
   55.24 +#define L1_BRICKTYPE_GA		0x62            /* b */
   55.25 +#define L1_BRICKTYPE_C          0x63            /* c */
   55.26 +#define L1_BRICKTYPE_OPUS_TIO	0x66		/* f */
   55.27 +#define L1_BRICKTYPE_I          0x69            /* i */
   55.28 +#define L1_BRICKTYPE_N          0x6e            /* n */
   55.29 +#define L1_BRICKTYPE_OPUS       0x6f		/* o */
   55.30 +#define L1_BRICKTYPE_P          0x70            /* p */
   55.31 +#define L1_BRICKTYPE_R          0x72            /* r */
   55.32 +#define L1_BRICKTYPE_CHI_CG     0x76            /* v */
   55.33 +#define L1_BRICKTYPE_X          0x78            /* x */
   55.34 +#define L1_BRICKTYPE_X2         0x79            /* y */
   55.35 +#define L1_BRICKTYPE_SA		0x5e            /* ^ */
   55.36 +#define L1_BRICKTYPE_PA		0x6a            /* j */
   55.37 +#define L1_BRICKTYPE_IA		0x6b            /* k */
   55.38 +#define L1_BRICKTYPE_ATHENA	0x2b            /* + */
   55.39 +#define L1_BRICKTYPE_DAYTONA	0x7a            /* z */
   55.40 +#define L1_BRICKTYPE_1932	0x2c		/* . */
   55.41 +#define L1_BRICKTYPE_191010	0x2e		/* , */
   55.42 +
   55.43 +/* board type response codes */
   55.44 +#define L1_BOARDTYPE_IP69       0x0100          /* CA */
   55.45 +#define L1_BOARDTYPE_IP63       0x0200          /* CB */
   55.46 +#define L1_BOARDTYPE_BASEIO     0x0300          /* IB */
   55.47 +#define L1_BOARDTYPE_PCIE2SLOT  0x0400          /* IC */
   55.48 +#define L1_BOARDTYPE_PCIX3SLOT  0x0500          /* ID */
   55.49 +#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600       /* IE */
   55.50 +#define L1_BOARDTYPE_ABACUS     0x0700          /* AB */
   55.51 +#define L1_BOARDTYPE_DAYTONA    0x0800          /* AD */
   55.52 +#define L1_BOARDTYPE_INVAL      (-1)            /* invalid brick type */
   55.53 +
   55.54 +#endif /* _ASM_IA64_SN_L1_H */
    56.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    56.2 +++ b/xen/include/asm-ia64/linux/asm/sn/leds.h	Wed Dec 13 11:08:40 2006 -0700
    56.3 @@ -0,0 +1,33 @@
    56.4 +/*
    56.5 + * This file is subject to the terms and conditions of the GNU General Public
    56.6 + * License.  See the file "COPYING" in the main directory of this archive
    56.7 + * for more details.
    56.8 + * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
    56.9 + */
   56.10 +#ifndef _ASM_IA64_SN_LEDS_H
   56.11 +#define _ASM_IA64_SN_LEDS_H
   56.12 +
   56.13 +#include <asm/sn/addrs.h>
   56.14 +#include <asm/sn/pda.h>
   56.15 +#include <asm/sn/shub_mmr.h>
   56.16 +
   56.17 +#define LED0		(LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
   56.18 +#define LED_CPU_SHIFT	16
   56.19 +
   56.20 +#define LED_CPU_HEARTBEAT	0x01
   56.21 +#define LED_CPU_ACTIVITY	0x02
   56.22 +#define LED_ALWAYS_SET		0x00
   56.23 +
   56.24 +/*
   56.25 + * Basic macros for flashing the LEDS on an SGI SN.
   56.26 + */
   56.27 +
   56.28 +static __inline__ void
   56.29 +set_led_bits(u8 value, u8 mask)
   56.30 +{
   56.31 +	pda->led_state = (pda->led_state & ~mask) | (value & mask);
   56.32 +	*pda->led_address = (short) pda->led_state;
   56.33 +}
   56.34 +
   56.35 +#endif /* _ASM_IA64_SN_LEDS_H */
   56.36 +
    57.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    57.2 +++ b/xen/include/asm-ia64/linux/asm/sn/module.h	Wed Dec 13 11:08:40 2006 -0700
    57.3 @@ -0,0 +1,127 @@
    57.4 +/*
    57.5 + * This file is subject to the terms and conditions of the GNU General Public
    57.6 + * License.  See the file "COPYING" in the main directory of this archive
    57.7 + * for more details.
    57.8 + *
    57.9 + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
   57.10 + */
   57.11 +#ifndef _ASM_IA64_SN_MODULE_H
   57.12 +#define _ASM_IA64_SN_MODULE_H
   57.13 +
   57.14 +/* parameter for format_module_id() */
   57.15 +#define MODULE_FORMAT_BRIEF	1
   57.16 +#define MODULE_FORMAT_LONG	2
   57.17 +#define MODULE_FORMAT_LCD	3
   57.18 +
   57.19 +/*
   57.20 + *	Module id format
   57.21 + *
   57.22 + *	31-16	Rack ID (encoded class, group, number - 16-bit unsigned int)
   57.23 + *	 15-8	Brick type (8-bit ascii character)
   57.24 + *	  7-0	Bay (brick position in rack (0-63) - 8-bit unsigned int)
   57.25 + *
   57.26 + */
   57.27 +
   57.28 +/*
   57.29 + * Macros for getting the brick type
   57.30 + */
   57.31 +#define MODULE_BTYPE_MASK	0xff00
   57.32 +#define MODULE_BTYPE_SHFT	8
   57.33 +#define MODULE_GET_BTYPE(_m)	(((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
   57.34 +#define MODULE_BT_TO_CHAR(_b)	((char)(_b))
   57.35 +#define MODULE_GET_BTCHAR(_m)	(MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
   57.36 +
   57.37 +/*
   57.38 + * Macros for getting the rack ID.
   57.39 + */
   57.40 +#define MODULE_RACK_MASK	0xffff0000
   57.41 +#define MODULE_RACK_SHFT	16
   57.42 +#define MODULE_GET_RACK(_m)	(((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
   57.43 +
   57.44 +/*
   57.45 + * Macros for getting the brick position
   57.46 + */
   57.47 +#define MODULE_BPOS_MASK	0x00ff
   57.48 +#define MODULE_BPOS_SHFT	0
   57.49 +#define MODULE_GET_BPOS(_m)	(((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
   57.50 +
   57.51 +/*
   57.52 + * Macros for encoding and decoding rack IDs
   57.53 + * A rack number consists of three parts:
   57.54 + *   class (0==CPU/mixed, 1==I/O), group, number
   57.55 + *
   57.56 + * Rack number is stored just as it is displayed on the screen:
   57.57 + * a 3-decimal-digit number.
   57.58 + */
   57.59 +#define RACK_CLASS_DVDR         100
   57.60 +#define RACK_GROUP_DVDR         10
   57.61 +#define RACK_NUM_DVDR           1
   57.62 +
   57.63 +#define RACK_CREATE_RACKID(_c, _g, _n)  ((_c) * RACK_CLASS_DVDR +       \
   57.64 +        (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
   57.65 +
   57.66 +#define RACK_GET_CLASS(_r)              ((_r) / RACK_CLASS_DVDR)
   57.67 +#define RACK_GET_GROUP(_r)              (((_r) - RACK_GET_CLASS(_r) *   \
   57.68 +            RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
   57.69 +#define RACK_GET_NUM(_r)                (((_r) - RACK_GET_CLASS(_r) *   \
   57.70 +            RACK_CLASS_DVDR - RACK_GET_GROUP(_r) *      \
   57.71 +            RACK_GROUP_DVDR) / RACK_NUM_DVDR)
   57.72 +
   57.73 +/*
   57.74 + * Macros for encoding and decoding rack IDs
   57.75 + * A rack number consists of three parts:
   57.76 + *   class      1 bit, 0==CPU/mixed, 1==I/O
   57.77 + *   group      2 bits for CPU/mixed, 3 bits for I/O
   57.78 + *   number     3 bits for CPU/mixed, 2 bits for I/O (1 based)
   57.79 + */
   57.80 +#define RACK_GROUP_BITS(_r)     (RACK_GET_CLASS(_r) ? 3 : 2)
   57.81 +#define RACK_NUM_BITS(_r)       (RACK_GET_CLASS(_r) ? 2 : 3)
   57.82 +
   57.83 +#define RACK_CLASS_MASK(_r)     0x20
   57.84 +#define RACK_CLASS_SHFT(_r)     5
   57.85 +#define RACK_ADD_CLASS(_r, _c)  \
   57.86 +        ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
   57.87 +
   57.88 +#define RACK_GROUP_SHFT(_r)     RACK_NUM_BITS(_r)
   57.89 +#define RACK_GROUP_MASK(_r)     \
   57.90 +        ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
   57.91 +#define RACK_ADD_GROUP(_r, _g)  \
   57.92 +        ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
   57.93 +
   57.94 +#define RACK_NUM_SHFT(_r)       0
   57.95 +#define RACK_NUM_MASK(_r)       \
   57.96 +        ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
   57.97 +#define RACK_ADD_NUM(_r, _n)    \
   57.98 +        ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
   57.99 +
  57.100 +
  57.101 +/*
  57.102 + * Brick type definitions
  57.103 + */
  57.104 +#define MAX_BRICK_TYPES         256 /* brick type is stored as uchar */
  57.105 +
  57.106 +extern char brick_types[];
  57.107 +
  57.108 +#define MODULE_CBRICK           0
  57.109 +#define MODULE_RBRICK           1
  57.110 +#define MODULE_IBRICK           2
  57.111 +#define MODULE_KBRICK           3
  57.112 +#define MODULE_XBRICK           4
  57.113 +#define MODULE_DBRICK           5
  57.114 +#define MODULE_PBRICK           6
  57.115 +#define MODULE_NBRICK           7
  57.116 +#define MODULE_PEBRICK          8
  57.117 +#define MODULE_PXBRICK          9
  57.118 +#define MODULE_IXBRICK          10
  57.119 +#define MODULE_CGBRICK		11
  57.120 +#define MODULE_OPUSBRICK        12
  57.121 +#define MODULE_SABRICK		13	/* TIO BringUp Brick */
  57.122 +#define MODULE_IABRICK		14
  57.123 +#define MODULE_PABRICK		15
  57.124 +#define MODULE_GABRICK		16
  57.125 +#define MODULE_OPUS_TIO		17	/* OPUS TIO Riser */
  57.126 +
  57.127 +extern char brick_types[];
  57.128 +extern void format_module_id(char *, moduleid_t, int);
  57.129 +
  57.130 +#endif /* _ASM_IA64_SN_MODULE_H */
    58.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    58.2 +++ b/xen/include/asm-ia64/linux/asm/sn/pcibus_provider_defs.h	Wed Dec 13 11:08:40 2006 -0700
    58.3 @@ -0,0 +1,68 @@
    58.4 +/*
    58.5 + * This file is subject to the terms and conditions of the GNU General Public
    58.6 + * License.  See the file "COPYING" in the main directory of this archive
    58.7 + * for more details.
    58.8 + *
    58.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   58.10 + */
   58.11 +#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
   58.12 +#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
   58.13 +
   58.14 +/*
   58.15 + * SN pci asic types.  Do not ever renumber these or reuse values.  The
   58.16 + * values must agree with what prom thinks they are.
   58.17 + */
   58.18 +
   58.19 +#define PCIIO_ASIC_TYPE_UNKNOWN	0
   58.20 +#define PCIIO_ASIC_TYPE_PPB	1
   58.21 +#define PCIIO_ASIC_TYPE_PIC	2
   58.22 +#define PCIIO_ASIC_TYPE_TIOCP	3
   58.23 +#define PCIIO_ASIC_TYPE_TIOCA	4
   58.24 +#define PCIIO_ASIC_TYPE_TIOCE	5
   58.25 +
   58.26 +#define PCIIO_ASIC_MAX_TYPES	6
   58.27 +
   58.28 +/*
   58.29 + * Common pciio bus provider data.  There should be one of these as the
   58.30 + * first field in any pciio based provider soft structure (e.g. pcibr_soft
   58.31 + * tioca_soft, etc).
   58.32 + */
   58.33 +
   58.34 +struct pcibus_bussoft {
   58.35 +	u32		bs_asic_type;	/* chipset type */
   58.36 +	u32		bs_xid;		/* xwidget id */
   58.37 +	u32		bs_persist_busnum; /* Persistent Bus Number */
   58.38 +	u32		bs_persist_segment; /* Segment Number */
   58.39 +	u64		bs_legacy_io;	/* legacy io pio addr */
   58.40 +	u64		bs_legacy_mem;	/* legacy mem pio addr */
   58.41 +	u64		bs_base;	/* widget base */
   58.42 +	struct xwidget_info	*bs_xwidget_info;
   58.43 +};
   58.44 +
   58.45 +struct pci_controller;
   58.46 +/*
   58.47 + * SN pci bus indirection
   58.48 + */
   58.49 +
   58.50 +struct sn_pcibus_provider {
   58.51 +	dma_addr_t	(*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
   58.52 +	dma_addr_t	(*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
   58.53 +	void		(*dma_unmap)(struct pci_dev *, dma_addr_t, int);
   58.54 +	void *		(*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
   58.55 + 	void		(*force_interrupt)(struct sn_irq_info *);
   58.56 + 	void		(*target_interrupt)(struct sn_irq_info *);
   58.57 +};
   58.58 +
   58.59 +/*
   58.60 + * Flags used by the map interfaces
   58.61 + * bits 3:0 specifies format of passed in address
   58.62 + * bit  4   specifies that address is to be used for MSI
   58.63 + */
   58.64 +
   58.65 +#define SN_DMA_ADDRTYPE(x)	((x) & 0xf)
   58.66 +#define     SN_DMA_ADDR_PHYS	1	/* address is an xio address. */
   58.67 +#define     SN_DMA_ADDR_XIO	2	/* address is phys memory */
   58.68 +#define SN_DMA_MSI		0x10	/* Bus address is to be used for MSI */
   58.69 +
   58.70 +extern struct sn_pcibus_provider *sn_pci_provider[];
   58.71 +#endif				/* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
    59.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    59.2 +++ b/xen/include/asm-ia64/linux/asm/sn/pcidev.h	Wed Dec 13 11:08:40 2006 -0700
    59.3 @@ -0,0 +1,83 @@
    59.4 +/*
    59.5 + * This file is subject to the terms and conditions of the GNU General Public
    59.6 + * License.  See the file "COPYING" in the main directory of this archive
    59.7 + * for more details.
    59.8 + *
    59.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   59.10 + */
   59.11 +#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
   59.12 +#define _ASM_IA64_SN_PCI_PCIDEV_H
   59.13 +
   59.14 +#include <linux/pci.h>
   59.15 +
   59.16 +/*
   59.17 + * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
   59.18 + * the pcidev_info structs for all devices under a controller, we extend the
   59.19 + * definition of pci_controller, via sn_pci_controller, to include a list
   59.20 + * of pcidev_info.
   59.21 + */
   59.22 +struct sn_pci_controller {
   59.23 +	struct pci_controller pci_controller;
   59.24 +	struct list_head pcidev_info;
   59.25 +};
   59.26 +
   59.27 +#define SN_PCI_CONTROLLER(dev) ((struct sn_pci_controller *) dev->sysdata)
   59.28 +
   59.29 +#define SN_PCIDEV_INFO(dev)	sn_pcidev_info_get(dev)
   59.30 +
   59.31 +#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
   59.32 +	(struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
   59.33 +/*
   59.34 + * Given a pci_bus, return the sn pcibus_bussoft struct.  Note that
   59.35 + * this only works for root busses, not for busses represented by PPB's.
   59.36 + */
   59.37 +
   59.38 +#define SN_PCIBUS_BUSSOFT(pci_bus) \
   59.39 +        ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
   59.40 +
   59.41 +#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
   59.42 +	(struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
   59.43 +/*
   59.44 + * Given a struct pci_dev, return the sn pcibus_bussoft struct.  Note
   59.45 + * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
   59.46 + * due to possible PPB's in the path.
   59.47 + */
   59.48 +
   59.49 +#define SN_PCIDEV_BUSSOFT(pci_dev) \
   59.50 +	(SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
   59.51 +
   59.52 +#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
   59.53 +	(SN_PCIDEV_INFO(pci_dev)->pdi_provider)
   59.54 +
   59.55 +#define PCIIO_BUS_NONE	255      /* bus 255 reserved */
   59.56 +#define PCIIO_SLOT_NONE 255
   59.57 +#define PCIIO_FUNC_NONE 255
   59.58 +#define PCIIO_VENDOR_ID_NONE	(-1)
   59.59 +
   59.60 +struct pcidev_info {
   59.61 +	u64		pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
   59.62 +	u64		pdi_slot_host_handle;	/* Bus and devfn Host pci_dev */
   59.63 +
   59.64 +	struct pcibus_bussoft	*pdi_pcibus_info;	/* Kernel common bus soft */
   59.65 +	struct pcidev_info	*pdi_host_pcidev_info;	/* Kernel Host pci_dev */
   59.66 +	struct pci_dev		*pdi_linux_pcidev;	/* Kernel pci_dev */
   59.67 +
   59.68 +	struct sn_irq_info	*pdi_sn_irq_info;
   59.69 +	struct sn_pcibus_provider *pdi_provider;	/* sn pci ops */
   59.70 +	struct pci_dev 		*host_pci_dev;		/* host bus link */
   59.71 +	struct list_head	pdi_list;		/* List of pcidev_info */
   59.72 +};
   59.73 +
   59.74 +extern void sn_irq_fixup(struct pci_dev *pci_dev,
   59.75 +			 struct sn_irq_info *sn_irq_info);
   59.76 +extern void sn_irq_unfixup(struct pci_dev *pci_dev);
   59.77 +extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
   59.78 +extern void sn_pci_controller_fixup(int segment, int busnum,
   59.79 + 				    struct pci_bus *bus);
   59.80 +extern void sn_bus_store_sysdata(struct pci_dev *dev);
   59.81 +extern void sn_bus_free_sysdata(void);
   59.82 +extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
   59.83 +extern void sn_pci_fixup_slot(struct pci_dev *dev);
   59.84 +extern void sn_pci_unfixup_slot(struct pci_dev *dev);
   59.85 +extern void sn_irq_lh_init(void);
   59.86 +#endif				/* _ASM_IA64_SN_PCI_PCIDEV_H */
    60.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    60.2 +++ b/xen/include/asm-ia64/linux/asm/sn/pda.h	Wed Dec 13 11:08:40 2006 -0700
    60.3 @@ -0,0 +1,69 @@
    60.4 +/*
    60.5 + * This file is subject to the terms and conditions of the GNU General Public
    60.6 + * License.  See the file "COPYING" in the main directory of this archive
    60.7 + * for more details.
    60.8 + *
    60.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   60.10 + */
   60.11 +#ifndef _ASM_IA64_SN_PDA_H
   60.12 +#define _ASM_IA64_SN_PDA_H
   60.13 +
   60.14 +#include <linux/cache.h>
   60.15 +#include <asm/percpu.h>
   60.16 +#include <asm/system.h>
   60.17 +
   60.18 +
   60.19 +/*
   60.20 + * CPU-specific data structure.
   60.21 + *
   60.22 + * One of these structures is allocated for each cpu of a NUMA system.
   60.23 + *
   60.24 + * This structure provides a convenient way of keeping together 
   60.25 + * all SN per-cpu data structures. 
   60.26 + */
   60.27 +
   60.28 +typedef struct pda_s {
   60.29 +
   60.30 +	/*
   60.31 +	 * Support for SN LEDs
   60.32 +	 */
   60.33 +	volatile short	*led_address;
   60.34 +	u8		led_state;
   60.35 +	u8		hb_state;	/* supports blinking heartbeat leds */
   60.36 +	unsigned int	hb_count;
   60.37 +
   60.38 +	unsigned int	idle_flag;
   60.39 +	
   60.40 +	volatile unsigned long *bedrock_rev_id;
   60.41 +	volatile unsigned long *pio_write_status_addr;
   60.42 +	unsigned long pio_write_status_val;
   60.43 +	volatile unsigned long *pio_shub_war_cam_addr;
   60.44 +
   60.45 +	unsigned long	sn_in_service_ivecs[4];
   60.46 +	int		sn_lb_int_war_ticks;
   60.47 +	int		sn_last_irq;
   60.48 +	int		sn_first_irq;
   60.49 +} pda_t;
   60.50 +
   60.51 +
   60.52 +#define CACHE_ALIGN(x)	(((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
   60.53 +
   60.54 +/*
   60.55 + * PDA
   60.56 + * Per-cpu private data area for each cpu. The PDA is located immediately after
   60.57 + * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
   60.58 + * cpu but only a small amout of the page is actually used. We put the SNIA PDA
   60.59 + * in the same page as the cpu_data area. Note that there is a check in the setup
   60.60 + * code to verify that we don't overflow the page.
   60.61 + *
   60.62 + * Seems like we should should cache-line align the pda so that any changes in the
   60.63 + * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
   60.64 + * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
   60.65 + */
   60.66 +DECLARE_PER_CPU(struct pda_s, pda_percpu);
   60.67 +
   60.68 +#define pda		(&__ia64_per_cpu_var(pda_percpu))
   60.69 +
   60.70 +#define pdacpu(cpu)	(&per_cpu(pda_percpu, cpu))
   60.71 +
   60.72 +#endif /* _ASM_IA64_SN_PDA_H */
    61.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    61.2 +++ b/xen/include/asm-ia64/linux/asm/sn/pic.h	Wed Dec 13 11:08:40 2006 -0700
    61.3 @@ -0,0 +1,261 @@
    61.4 +/*
    61.5 + * This file is subject to the terms and conditions of the GNU General Public
    61.6 + * License.  See the file "COPYING" in the main directory of this archive
    61.7 + * for more details.
    61.8 + *
    61.9 + * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
   61.10 + */
   61.11 +#ifndef _ASM_IA64_SN_PCI_PIC_H
   61.12 +#define _ASM_IA64_SN_PCI_PIC_H
   61.13 +
   61.14 +/*
   61.15 + * PIC AS DEVICE ZERO
   61.16 + * ------------------
   61.17 + *
   61.18 + * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
   61.19 + * be designated as 'device 0'.   That is a departure from earlier SGI
   61.20 + * PCI bridges.  Because of that we use config space 1 to access the
   61.21 + * config space of the first actual PCI device on the bus.
   61.22 + * Here's what the PIC manual says:
   61.23 + *
   61.24 + *     The current PCI-X bus specification now defines that the parent
   61.25 + *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
   61.26 + *     reduced the total number of devices from 8 to 4 and removed the
   61.27 + *     device registers and windows, now only supporting devices 0,1,2, and
   61.28 + *     3. PIC did leave all 8 configuration space windows. The reason was
   61.29 + *     there was nothing to gain by removing them. Here in lies the problem.
   61.30 + *     The device numbering we do using 0 through 3 is unrelated to the device
   61.31 + *     numbering which PCI-X requires in configuration space. In the past we
   61.32 + *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
   61.33 + *     PCI-X requires we start a 1, not 0 and currently the PX brick
   61.34 + *     does associate our:
   61.35 + *
   61.36 + *         device 0 with configuration space window 1,
   61.37 + *         device 1 with configuration space window 2,
   61.38 + *         device 2 with configuration space window 3,
   61.39 + *         device 3 with configuration space window 4.
   61.40 + *
   61.41 + * The net effect is that all config space access are off-by-one with
   61.42 + * relation to other per-slot accesses on the PIC.
   61.43 + * Here is a table that shows some of that:
   61.44 + *
   61.45 + *                               Internal Slot#
   61.46 + *           |
   61.47 + *           |     0         1        2         3
   61.48 + * ----------|---------------------------------------
   61.49 + * config    |  0x21000   0x22000  0x23000   0x24000
   61.50 + *           |
   61.51 + * even rrb  |  0[0]      n/a      1[0]      n/a	[] == implied even/odd
   61.52 + *           |
   61.53 + * odd rrb   |  n/a       0[1]     n/a       1[1]
   61.54 + *           |
   61.55 + * int dev   |  00       01        10        11
   61.56 + *           |
   61.57 + * ext slot# |  1        2         3         4
   61.58 + * ----------|---------------------------------------
   61.59 + */
   61.60 +
   61.61 +#define PIC_ATE_TARGETID_SHFT           8
   61.62 +#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFFUL
   61.63 +#define PIC_PCI64_ATTR_TARG_SHFT        60
   61.64 +
   61.65 +
   61.66 +/*****************************************************************************
   61.67 + *********************** PIC MMR structure mapping ***************************
   61.68 + *****************************************************************************/
   61.69 +
   61.70 +/* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
   61.71 + * of a 64-bit register.  When writing PIC registers, always write the
   61.72 + * entire 64 bits.
   61.73 + */
   61.74 +
   61.75 +struct pic {
   61.76 +
   61.77 +    /* 0x000000-0x00FFFF -- Local Registers */
   61.78 +
   61.79 +    /* 0x000000-0x000057 -- Standard Widget Configuration */
   61.80 +    u64		p_wid_id;			/* 0x000000 */
   61.81 +    u64		p_wid_stat;			/* 0x000008 */
   61.82 +    u64		p_wid_err_upper;		/* 0x000010 */
   61.83 +    u64		p_wid_err_lower;		/* 0x000018 */
   61.84 +    #define p_wid_err p_wid_err_lower
   61.85 +    u64		p_wid_control;			/* 0x000020 */
   61.86 +    u64		p_wid_req_timeout;		/* 0x000028 */
   61.87 +    u64		p_wid_int_upper;		/* 0x000030 */
   61.88 +    u64		p_wid_int_lower;		/* 0x000038 */
   61.89 +    #define p_wid_int p_wid_int_lower
   61.90 +    u64		p_wid_err_cmdword;		/* 0x000040 */
   61.91 +    u64		p_wid_llp;			/* 0x000048 */
   61.92 +    u64		p_wid_tflush;			/* 0x000050 */
   61.93 +
   61.94 +    /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
   61.95 +    u64		p_wid_aux_err;			/* 0x000058 */
   61.96 +    u64		p_wid_resp_upper;		/* 0x000060 */
   61.97 +    u64		p_wid_resp_lower;		/* 0x000068 */
   61.98 +    #define p_wid_resp p_wid_resp_lower
   61.99 +    u64		p_wid_tst_pin_ctrl;		/* 0x000070 */
  61.100 +    u64		p_wid_addr_lkerr;		/* 0x000078 */
  61.101 +
  61.102 +    /* 0x000080-0x00008F -- PMU & MAP */
  61.103 +    u64		p_dir_map;			/* 0x000080 */
  61.104 +    u64		_pad_000088;			/* 0x000088 */
  61.105 +
  61.106 +    /* 0x000090-0x00009F -- SSRAM */
  61.107 +    u64		p_map_fault;			/* 0x000090 */
  61.108 +    u64		_pad_000098;			/* 0x000098 */
  61.109 +
  61.110 +    /* 0x0000A0-0x0000AF -- Arbitration */
  61.111 +    u64		p_arb;				/* 0x0000A0 */
  61.112 +    u64		_pad_0000A8;			/* 0x0000A8 */
  61.113 +
  61.114 +    /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
  61.115 +    u64		p_ate_parity_err;		/* 0x0000B0 */
  61.116 +    u64		_pad_0000B8;			/* 0x0000B8 */
  61.117 +
  61.118 +    /* 0x0000C0-0x0000FF -- PCI/GIO */
  61.119 +    u64		p_bus_timeout;			/* 0x0000C0 */
  61.120 +    u64		p_pci_cfg;			/* 0x0000C8 */
  61.121 +    u64		p_pci_err_upper;		/* 0x0000D0 */
  61.122 +    u64		p_pci_err_lower;		/* 0x0000D8 */
  61.123 +    #define p_pci_err p_pci_err_lower
  61.124 +    u64		_pad_0000E0[4];			/* 0x0000{E0..F8} */
  61.125 +
  61.126 +    /* 0x000100-0x0001FF -- Interrupt */
  61.127 +    u64		p_int_status;			/* 0x000100 */
  61.128 +    u64		p_int_enable;			/* 0x000108 */
  61.129 +    u64		p_int_rst_stat;			/* 0x000110 */
  61.130 +    u64		p_int_mode;			/* 0x000118 */
  61.131 +    u64		p_int_device;			/* 0x000120 */
  61.132 +    u64		p_int_host_err;			/* 0x000128 */
  61.133 +    u64		p_int_addr[8];			/* 0x0001{30,,,68} */
  61.134 +    u64		p_err_int_view;			/* 0x000170 */
  61.135 +    u64		p_mult_int;			/* 0x000178 */
  61.136 +    u64		p_force_always[8];		/* 0x0001{80,,,B8} */
  61.137 +    u64		p_force_pin[8];			/* 0x0001{C0,,,F8} */
  61.138 +
  61.139 +    /* 0x000200-0x000298 -- Device */
  61.140 +    u64		p_device[4];			/* 0x0002{00,,,18} */
  61.141 +    u64		_pad_000220[4];			/* 0x0002{20,,,38} */
  61.142 +    u64		p_wr_req_buf[4];		/* 0x0002{40,,,58} */
  61.143 +    u64		_pad_000260[4];			/* 0x0002{60,,,78} */
  61.144 +    u64		p_rrb_map[2];			/* 0x0002{80,,,88} */
  61.145 +    #define p_even_resp p_rrb_map[0]			/* 0x000280 */
  61.146 +    #define p_odd_resp  p_rrb_map[1]			/* 0x000288 */
  61.147 +    u64		p_resp_status;			/* 0x000290 */
  61.148 +    u64		p_resp_clear;			/* 0x000298 */
  61.149 +
  61.150 +    u64		_pad_0002A0[12];		/* 0x0002{A0..F8} */
  61.151 +
  61.152 +    /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
  61.153 +    struct {
  61.154 +	u64	upper;				/* 0x0003{00,,,F0} */
  61.155 +	u64	lower;				/* 0x0003{08,,,F8} */
  61.156 +    } p_buf_addr_match[16];
  61.157 +
  61.158 +    /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
  61.159 +    struct {
  61.160 +	u64	flush_w_touch;			/* 0x000{400,,,5C0} */
  61.161 +	u64	flush_wo_touch;			/* 0x000{408,,,5C8} */
  61.162 +	u64	inflight;			/* 0x000{410,,,5D0} */
  61.163 +	u64	prefetch;			/* 0x000{418,,,5D8} */
  61.164 +	u64	total_pci_retry;		/* 0x000{420,,,5E0} */
  61.165 +	u64	max_pci_retry;			/* 0x000{428,,,5E8} */
  61.166 +	u64	max_latency;			/* 0x000{430,,,5F0} */
  61.167 +	u64	clear_all;			/* 0x000{438,,,5F8} */
  61.168 +    } p_buf_count[8];
  61.169 +
  61.170 +
  61.171 +    /* 0x000600-0x0009FF -- PCI/X registers */
  61.172 +    u64		p_pcix_bus_err_addr;		/* 0x000600 */
  61.173 +    u64		p_pcix_bus_err_attr;		/* 0x000608 */
  61.174 +    u64		p_pcix_bus_err_data;		/* 0x000610 */
  61.175 +    u64		p_pcix_pio_split_addr;		/* 0x000618 */
  61.176 +    u64		p_pcix_pio_split_attr;		/* 0x000620 */
  61.177 +    u64		p_pcix_dma_req_err_attr;	/* 0x000628 */
  61.178 +    u64		p_pcix_dma_req_err_addr;	/* 0x000630 */
  61.179 +    u64		p_pcix_timeout;			/* 0x000638 */
  61.180 +
  61.181 +    u64		_pad_000640[120];		/* 0x000{640,,,9F8} */
  61.182 +
  61.183 +    /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
  61.184 +    struct {
  61.185 +	u64	p_buf_addr;			/* 0x000{A00,,,AF0} */
  61.186 +	u64	p_buf_attr;			/* 0X000{A08,,,AF8} */
  61.187 +    } p_pcix_read_buf_64[16];
  61.188 +
  61.189 +    struct {
  61.190 +	u64	p_buf_addr;			/* 0x000{B00,,,BE0} */
  61.191 +	u64	p_buf_attr;			/* 0x000{B08,,,BE8} */
  61.192 +	u64	p_buf_valid;			/* 0x000{B10,,,BF0} */
  61.193 +	u64	__pad1;				/* 0x000{B18,,,BF8} */
  61.194 +    } p_pcix_write_buf_64[8];
  61.195 +
  61.196 +    /* End of Local Registers -- Start of Address Map space */
  61.197 +
  61.198 +    char		_pad_000c00[0x010000 - 0x000c00];
  61.199 +
  61.200 +    /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
  61.201 +    u64		p_int_ate_ram[1024];		/* 0x010000-0x011fff */
  61.202 +
  61.203 +    /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
  61.204 +    u64		p_int_ate_ram_mp[1024];		/* 0x012000-0x013fff */
  61.205 +
  61.206 +    char		_pad_014000[0x18000 - 0x014000];
  61.207 +
  61.208 +    /* 0x18000-0x197F8 -- PIC Write Request Ram */
  61.209 +    u64		p_wr_req_lower[256];		/* 0x18000 - 0x187F8 */
  61.210 +    u64		p_wr_req_upper[256];		/* 0x18800 - 0x18FF8 */
  61.211 +    u64		p_wr_req_parity[256];		/* 0x19000 - 0x197F8 */
  61.212 +
  61.213 +    char		_pad_019800[0x20000 - 0x019800];
  61.214 +
  61.215 +    /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
  61.216 +    union {
  61.217 +	u8		c[0x1000 / 1];			/* 0x02{0000,,,7FFF} */
  61.218 +	u16	s[0x1000 / 2];			/* 0x02{0000,,,7FFF} */
  61.219 +	u32	l[0x1000 / 4];			/* 0x02{0000,,,7FFF} */
  61.220 +	u64	d[0x1000 / 8];			/* 0x02{0000,,,7FFF} */
  61.221 +	union {
  61.222 +	    u8	c[0x100 / 1];
  61.223 +	    u16	s[0x100 / 2];
  61.224 +	    u32	l[0x100 / 4];
  61.225 +	    u64	d[0x100 / 8];
  61.226 +	} f[8];
  61.227 +    } p_type0_cfg_dev[8];				/* 0x02{0000,,,7FFF} */
  61.228 +
  61.229 +    /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
  61.230 +    union {
  61.231 +	u8		c[0x1000 / 1];			/* 0x028000-0x029000 */
  61.232 +	u16	s[0x1000 / 2];			/* 0x028000-0x029000 */
  61.233 +	u32	l[0x1000 / 4];			/* 0x028000-0x029000 */
  61.234 +	u64	d[0x1000 / 8];			/* 0x028000-0x029000 */
  61.235 +	union {
  61.236 +	    u8	c[0x100 / 1];
  61.237 +	    u16	s[0x100 / 2];
  61.238 +	    u32	l[0x100 / 4];
  61.239 +	    u64	d[0x100 / 8];
  61.240 +	} f[8];
  61.241 +    } p_type1_cfg;					/* 0x028000-0x029000 */
  61.242 +
  61.243 +    char		_pad_029000[0x030000-0x029000];
  61.244 +
  61.245 +    /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
  61.246 +    union {
  61.247 +	u8		c[8 / 1];
  61.248 +	u16	s[8 / 2];
  61.249 +	u32	l[8 / 4];
  61.250 +	u64	d[8 / 8];
  61.251 +    } p_pci_iack;					/* 0x030000-0x030007 */
  61.252 +
  61.253 +    char		_pad_030007[0x040000-0x030008];
  61.254 +
  61.255 +    /* 0x040000-0x030007 -- PCIX Special Cycle */
  61.256 +    union {
  61.257 +	u8		c[8 / 1];
  61.258 +	u16	s[8 / 2];
  61.259 +	u32	l[8 / 4];
  61.260 +	u64	d[8 / 8];
  61.261 +    } p_pcix_cycle;					/* 0x040000-0x040007 */
  61.262 +};
  61.263 +
  61.264 +#endif                          /* _ASM_IA64_SN_PCI_PIC_H */
    62.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    62.2 +++ b/xen/include/asm-ia64/linux/asm/sn/shub_mmr.h	Wed Dec 13 11:08:40 2006 -0700
    62.3 @@ -0,0 +1,502 @@
    62.4 +/*
    62.5 + *
    62.6 + * This file is subject to the terms and conditions of the GNU General Public
    62.7 + * License.  See the file "COPYING" in the main directory of this archive
    62.8 + * for more details.
    62.9 + *
   62.10 + * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.
   62.11 + */
   62.12 +
   62.13 +#ifndef _ASM_IA64_SN_SHUB_MMR_H
   62.14 +#define _ASM_IA64_SN_SHUB_MMR_H
   62.15 +
   62.16 +/* ==================================================================== */
   62.17 +/*                        Register "SH_IPI_INT"                         */
   62.18 +/*               SHub Inter-Processor Interrupt Registers               */
   62.19 +/* ==================================================================== */
   62.20 +#define SH1_IPI_INT			__IA64_UL_CONST(0x0000000110000380)
   62.21 +#define SH2_IPI_INT			__IA64_UL_CONST(0x0000000010000380)
   62.22 +
   62.23 +/*   SH_IPI_INT_TYPE                                                    */
   62.24 +/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
   62.25 +#define SH_IPI_INT_TYPE_SHFT				0
   62.26 +#define SH_IPI_INT_TYPE_MASK		__IA64_UL_CONST(0x0000000000000007)
   62.27 +
   62.28 +/*   SH_IPI_INT_AGT                                                     */
   62.29 +/*   Description:  Agent, must be 0 for SHub                            */
   62.30 +#define SH_IPI_INT_AGT_SHFT				3
   62.31 +#define SH_IPI_INT_AGT_MASK		__IA64_UL_CONST(0x0000000000000008)
   62.32 +
   62.33 +/*   SH_IPI_INT_PID                                                     */
   62.34 +/*   Description:  Processor ID, same setting as on targeted McKinley  */
   62.35 +#define SH_IPI_INT_PID_SHFT                      	4
   62.36 +#define SH_IPI_INT_PID_MASK		__IA64_UL_CONST(0x00000000000ffff0)
   62.37 +
   62.38 +/*   SH_IPI_INT_BASE                                                    */
   62.39 +/*   Description:  Optional interrupt vector area, 2MB aligned          */
   62.40 +#define SH_IPI_INT_BASE_SHFT				21
   62.41 +#define SH_IPI_INT_BASE_MASK 		__IA64_UL_CONST(0x0003ffffffe00000)
   62.42 +
   62.43 +/*   SH_IPI_INT_IDX                                                     */
   62.44 +/*   Description:  Targeted McKinley interrupt vector                   */
   62.45 +#define SH_IPI_INT_IDX_SHFT				52
   62.46 +#define SH_IPI_INT_IDX_MASK		__IA64_UL_CONST(0x0ff0000000000000)
   62.47 +
   62.48 +/*   SH_IPI_INT_SEND                                                    */
   62.49 +/*   Description:  Send Interrupt Message to PI, This generates a puls  */
   62.50 +#define SH_IPI_INT_SEND_SHFT				63
   62.51 +#define SH_IPI_INT_SEND_MASK		__IA64_UL_CONST(0x8000000000000000)
   62.52 +
   62.53 +/* ==================================================================== */
   62.54 +/*                     Register "SH_EVENT_OCCURRED"                     */
   62.55 +/*                    SHub Interrupt Event Occurred                     */
   62.56 +/* ==================================================================== */
   62.57 +#define SH1_EVENT_OCCURRED		__IA64_UL_CONST(0x0000000110010000)
   62.58 +#define SH1_EVENT_OCCURRED_ALIAS	__IA64_UL_CONST(0x0000000110010008)
   62.59 +#define SH2_EVENT_OCCURRED		__IA64_UL_CONST(0x0000000010010000)
   62.60 +#define SH2_EVENT_OCCURRED_ALIAS 	__IA64_UL_CONST(0x0000000010010008)
   62.61 +
   62.62 +/* ==================================================================== */
   62.63 +/*                     Register "SH_PI_CAM_CONTROL"                     */
   62.64 +/*                      CRB CAM MMR Access Control                      */
   62.65 +/* ==================================================================== */
   62.66 +#define SH1_PI_CAM_CONTROL		__IA64_UL_CONST(0x0000000120050300)
   62.67 +
   62.68 +/* ==================================================================== */
   62.69 +/*                        Register "SH_SHUB_ID"                         */
   62.70 +/*                            SHub ID Number                            */
   62.71 +/* ==================================================================== */
   62.72 +#define SH1_SHUB_ID			__IA64_UL_CONST(0x0000000110060580)
   62.73 +#define SH1_SHUB_ID_REVISION_SHFT			28
   62.74 +#define SH1_SHUB_ID_REVISION_MASK	__IA64_UL_CONST(0x00000000f0000000)
   62.75 +
   62.76 +/* ==================================================================== */
   62.77 +/*                          Register "SH_RTC"                           */
   62.78 +/*                           Real-time Clock                            */
   62.79 +/* ==================================================================== */
   62.80 +#define SH1_RTC				__IA64_UL_CONST(0x00000001101c0000)
   62.81 +#define SH2_RTC				__IA64_UL_CONST(0x00000002101c0000)
   62.82 +#define SH_RTC_MASK			__IA64_UL_CONST(0x007fffffffffffff)
   62.83 +
   62.84 +/* ==================================================================== */
   62.85 +/*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
   62.86 +/*                      PIO Write Status for CPU 0 & 1                  */
   62.87 +/* ==================================================================== */
   62.88 +#define SH1_PIO_WRITE_STATUS_0		__IA64_UL_CONST(0x0000000120070200)
   62.89 +#define SH1_PIO_WRITE_STATUS_1		__IA64_UL_CONST(0x0000000120070280)
   62.90 +#define SH2_PIO_WRITE_STATUS_0		__IA64_UL_CONST(0x0000000020070200)
   62.91 +#define SH2_PIO_WRITE_STATUS_1		__IA64_UL_CONST(0x0000000020070280)
   62.92 +#define SH2_PIO_WRITE_STATUS_2		__IA64_UL_CONST(0x0000000020070300)
   62.93 +#define SH2_PIO_WRITE_STATUS_3		__IA64_UL_CONST(0x0000000020070380)
   62.94 +
   62.95 +/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
   62.96 +/*   Description:  Deadlock response detected                           */
   62.97 +#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT		1
   62.98 +#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
   62.99 +					__IA64_UL_CONST(0x0000000000000002)
  62.100 +
  62.101 +/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
  62.102 +/*   Description:  Count of currently pending PIO writes                */
  62.103 +#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT	56
  62.104 +#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
  62.105 +					__IA64_UL_CONST(0x3f00000000000000)
  62.106 +
  62.107 +/* ==================================================================== */
  62.108 +/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
  62.109 +/* ==================================================================== */
  62.110 +#define SH1_PIO_WRITE_STATUS_0_ALIAS	__IA64_UL_CONST(0x0000000120070208)
  62.111 +#define SH2_PIO_WRITE_STATUS_0_ALIAS	__IA64_UL_CONST(0x0000000020070208)
  62.112 +
  62.113 +/* ==================================================================== */
  62.114 +/*                     Register "SH_EVENT_OCCURRED"                     */
  62.115 +/*                    SHub Interrupt Event Occurred                     */
  62.116 +/* ==================================================================== */
  62.117 +/*   SH_EVENT_OCCURRED_UART_INT                                         */
  62.118 +/*   Description:  Pending Junk Bus UART Interrupt                      */
  62.119 +#define SH_EVENT_OCCURRED_UART_INT_SHFT			20
  62.120 +#define SH_EVENT_OCCURRED_UART_INT_MASK	__IA64_UL_CONST(0x0000000000100000)
  62.121 +
  62.122 +/*   SH_EVENT_OCCURRED_IPI_INT                                          */
  62.123 +/*   Description:  Pending IPI Interrupt                                */
  62.124 +#define SH_EVENT_OCCURRED_IPI_INT_SHFT			28
  62.125 +#define SH_EVENT_OCCURRED_IPI_INT_MASK	__IA64_UL_CONST(0x0000000010000000)
  62.126 +
  62.127 +/*   SH_EVENT_OCCURRED_II_INT0                                          */
  62.128 +/*   Description:  Pending II 0 Interrupt                               */
  62.129 +#define SH_EVENT_OCCURRED_II_INT0_SHFT			29
  62.130 +#define SH_EVENT_OCCURRED_II_INT0_MASK	__IA64_UL_CONST(0x0000000020000000)
  62.131 +
  62.132 +/*   SH_EVENT_OCCURRED_II_INT1                                          */
  62.133 +/*   Description:  Pending II 1 Interrupt                               */
  62.134 +#define SH_EVENT_OCCURRED_II_INT1_SHFT			30
  62.135 +#define SH_EVENT_OCCURRED_II_INT1_MASK	__IA64_UL_CONST(0x0000000040000000)
  62.136 +
  62.137 +/*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
  62.138 +/*   Description:  Pending SHUB 2 EXT IO INT2                           */
  62.139 +#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT		33
  62.140 +#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
  62.141 +
  62.142 +/*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
  62.143 +/*   Description:  Pending SHUB 2 EXT IO INT3                           */
  62.144 +#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT		34
  62.145 +#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
  62.146 +
  62.147 +#define SH_ALL_INT_MASK \
  62.148 +	(SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
  62.149 +	 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
  62.150 +	 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
  62.151 +	 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
  62.152 +
  62.153 +
  62.154 +/* ==================================================================== */
  62.155 +/*                         LEDS                                         */
  62.156 +/* ==================================================================== */
  62.157 +#define SH1_REAL_JUNK_BUS_LED0			0x7fed00000UL
  62.158 +#define SH1_REAL_JUNK_BUS_LED1			0x7fed10000UL
  62.159 +#define SH1_REAL_JUNK_BUS_LED2			0x7fed20000UL
  62.160 +#define SH1_REAL_JUNK_BUS_LED3			0x7fed30000UL
  62.161 +
  62.162 +#define SH2_REAL_JUNK_BUS_LED0			0xf0000000UL
  62.163 +#define SH2_REAL_JUNK_BUS_LED1			0xf0010000UL
  62.164 +#define SH2_REAL_JUNK_BUS_LED2			0xf0020000UL
  62.165 +#define SH2_REAL_JUNK_BUS_LED3			0xf0030000UL
  62.166 +
  62.167 +/* ==================================================================== */
  62.168 +/*                         Register "SH1_PTC_0"                         */
  62.169 +/*       Puge Translation Cache Message Configuration Information       */
  62.170 +/* ==================================================================== */
  62.171 +#define SH1_PTC_0			__IA64_UL_CONST(0x00000001101a0000)
  62.172 +
  62.173 +/*   SH1_PTC_0_A                                                        */
  62.174 +/*   Description:  Type                                                 */
  62.175 +#define SH1_PTC_0_A_SHFT				0
  62.176 +
  62.177 +/*   SH1_PTC_0_PS                                                       */
  62.178 +/*   Description:  Page Size                                            */
  62.179 +#define SH1_PTC_0_PS_SHFT				2
  62.180 +
  62.181 +/*   SH1_PTC_0_RID                                                      */
  62.182 +/*   Description:  Region ID                                            */
  62.183 +#define SH1_PTC_0_RID_SHFT				8
  62.184 +
  62.185 +/*   SH1_PTC_0_START                                                    */
  62.186 +/*   Description:  Start                                                */
  62.187 +#define SH1_PTC_0_START_SHFT				63
  62.188 +
  62.189 +/* ==================================================================== */
  62.190 +/*                         Register "SH1_PTC_1"                         */
  62.191 +/*       Puge Translation Cache Message Configuration Information       */
  62.192 +/* ==================================================================== */
  62.193 +#define SH1_PTC_1			__IA64_UL_CONST(0x00000001101a0080)
  62.194 +
  62.195 +/*   SH1_PTC_1_START                                                    */
  62.196 +/*   Description:  PTC_1 Start                                          */
  62.197 +#define SH1_PTC_1_START_SHFT				63
  62.198 +
  62.199 +/* ==================================================================== */
  62.200 +/*                         Register "SH2_PTC"                           */
  62.201 +/*       Puge Translation Cache Message Configuration Information       */
  62.202 +/* ==================================================================== */
  62.203 +#define SH2_PTC				__IA64_UL_CONST(0x0000000170000000)
  62.204 +
  62.205 +/*   SH2_PTC_A                                                          */
  62.206 +/*   Description:  Type                                                 */
  62.207 +#define SH2_PTC_A_SHFT					0
  62.208 +
  62.209 +/*   SH2_PTC_PS                                                         */
  62.210 +/*   Description:  Page Size                                            */
  62.211 +#define SH2_PTC_PS_SHFT					2
  62.212 +
  62.213 +/*   SH2_PTC_RID                                                      */
  62.214 +/*   Description:  Region ID                                            */
  62.215 +#define SH2_PTC_RID_SHFT				4
  62.216 +
  62.217 +/*   SH2_PTC_START                                                      */
  62.218 +/*   Description:  Start                                                */
  62.219 +#define SH2_PTC_START_SHFT				63
  62.220 +
  62.221 +/*   SH2_PTC_ADDR_RID                                                   */
  62.222 +/*   Description:  Region ID                                            */
  62.223 +#define SH2_PTC_ADDR_SHFT				4
  62.224 +#define SH2_PTC_ADDR_MASK		__IA64_UL_CONST(0x1ffffffffffff000)
  62.225 +
  62.226 +/* ==================================================================== */
  62.227 +/*                    Register "SH_RTC1_INT_CONFIG"                     */
  62.228 +/*                SHub RTC 1 Interrupt Config Registers                 */
  62.229 +/* ==================================================================== */
  62.230 +
  62.231 +#define SH1_RTC1_INT_CONFIG		__IA64_UL_CONST(0x0000000110001480)
  62.232 +#define SH2_RTC1_INT_CONFIG		__IA64_UL_CONST(0x0000000010001480)
  62.233 +#define SH_RTC1_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
  62.234 +#define SH_RTC1_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.235 +
  62.236 +/*   SH_RTC1_INT_CONFIG_TYPE                                            */
  62.237 +/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  62.238 +#define SH_RTC1_INT_CONFIG_TYPE_SHFT			0
  62.239 +#define SH_RTC1_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
  62.240 +
  62.241 +/*   SH_RTC1_INT_CONFIG_AGT                                             */
  62.242 +/*   Description:  Agent, must be 0 for SHub                            */
  62.243 +#define SH_RTC1_INT_CONFIG_AGT_SHFT			3
  62.244 +#define SH_RTC1_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
  62.245 +
  62.246 +/*   SH_RTC1_INT_CONFIG_PID                                             */
  62.247 +/*   Description:  Processor ID, same setting as on targeted McKinley  */
  62.248 +#define SH_RTC1_INT_CONFIG_PID_SHFT			4
  62.249 +#define SH_RTC1_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
  62.250 +
  62.251 +/*   SH_RTC1_INT_CONFIG_BASE                                            */
  62.252 +/*   Description:  Optional interrupt vector area, 2MB aligned          */
  62.253 +#define SH_RTC1_INT_CONFIG_BASE_SHFT			21
  62.254 +#define SH_RTC1_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
  62.255 +
  62.256 +/*   SH_RTC1_INT_CONFIG_IDX                                             */
  62.257 +/*   Description:  Targeted McKinley interrupt vector                   */
  62.258 +#define SH_RTC1_INT_CONFIG_IDX_SHFT			52
  62.259 +#define SH_RTC1_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
  62.260 +
  62.261 +/* ==================================================================== */
  62.262 +/*                    Register "SH_RTC1_INT_ENABLE"                     */
  62.263 +/*                SHub RTC 1 Interrupt Enable Registers                 */
  62.264 +/* ==================================================================== */
  62.265 +
  62.266 +#define SH1_RTC1_INT_ENABLE		__IA64_UL_CONST(0x0000000110001500)
  62.267 +#define SH2_RTC1_INT_ENABLE		__IA64_UL_CONST(0x0000000010001500)
  62.268 +#define SH_RTC1_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
  62.269 +#define SH_RTC1_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.270 +
  62.271 +/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
  62.272 +/*   Description:  Enable RTC 1 Interrupt                               */
  62.273 +#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT		0
  62.274 +#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
  62.275 +					__IA64_UL_CONST(0x0000000000000001)
  62.276 +
  62.277 +/* ==================================================================== */
  62.278 +/*                    Register "SH_RTC2_INT_CONFIG"                     */
  62.279 +/*                SHub RTC 2 Interrupt Config Registers                 */
  62.280 +/* ==================================================================== */
  62.281 +
  62.282 +#define SH1_RTC2_INT_CONFIG		__IA64_UL_CONST(0x0000000110001580)
  62.283 +#define SH2_RTC2_INT_CONFIG		__IA64_UL_CONST(0x0000000010001580)
  62.284 +#define SH_RTC2_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
  62.285 +#define SH_RTC2_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.286 +
  62.287 +/*   SH_RTC2_INT_CONFIG_TYPE                                            */
  62.288 +/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  62.289 +#define SH_RTC2_INT_CONFIG_TYPE_SHFT			0
  62.290 +#define SH_RTC2_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
  62.291 +
  62.292 +/*   SH_RTC2_INT_CONFIG_AGT                                             */
  62.293 +/*   Description:  Agent, must be 0 for SHub                            */
  62.294 +#define SH_RTC2_INT_CONFIG_AGT_SHFT			3
  62.295 +#define SH_RTC2_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
  62.296 +
  62.297 +/*   SH_RTC2_INT_CONFIG_PID                                             */
  62.298 +/*   Description:  Processor ID, same setting as on targeted McKinley  */
  62.299 +#define SH_RTC2_INT_CONFIG_PID_SHFT			4
  62.300 +#define SH_RTC2_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
  62.301 +
  62.302 +/*   SH_RTC2_INT_CONFIG_BASE                                            */
  62.303 +/*   Description:  Optional interrupt vector area, 2MB aligned          */
  62.304 +#define SH_RTC2_INT_CONFIG_BASE_SHFT			21
  62.305 +#define SH_RTC2_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
  62.306 +
  62.307 +/*   SH_RTC2_INT_CONFIG_IDX                                             */
  62.308 +/*   Description:  Targeted McKinley interrupt vector                   */
  62.309 +#define SH_RTC2_INT_CONFIG_IDX_SHFT			52
  62.310 +#define SH_RTC2_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
  62.311 +
  62.312 +/* ==================================================================== */
  62.313 +/*                    Register "SH_RTC2_INT_ENABLE"                     */
  62.314 +/*                SHub RTC 2 Interrupt Enable Registers                 */
  62.315 +/* ==================================================================== */
  62.316 +
  62.317 +#define SH1_RTC2_INT_ENABLE		__IA64_UL_CONST(0x0000000110001600)
  62.318 +#define SH2_RTC2_INT_ENABLE		__IA64_UL_CONST(0x0000000010001600)
  62.319 +#define SH_RTC2_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
  62.320 +#define SH_RTC2_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.321 +
  62.322 +/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
  62.323 +/*   Description:  Enable RTC 2 Interrupt                               */
  62.324 +#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT		0
  62.325 +#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
  62.326 +					__IA64_UL_CONST(0x0000000000000001)
  62.327 +
  62.328 +/* ==================================================================== */
  62.329 +/*                    Register "SH_RTC3_INT_CONFIG"                     */
  62.330 +/*                SHub RTC 3 Interrupt Config Registers                 */
  62.331 +/* ==================================================================== */
  62.332 +
  62.333 +#define SH1_RTC3_INT_CONFIG		__IA64_UL_CONST(0x0000000110001680)
  62.334 +#define SH2_RTC3_INT_CONFIG		__IA64_UL_CONST(0x0000000010001680)
  62.335 +#define SH_RTC3_INT_CONFIG_MASK		__IA64_UL_CONST(0x0ff3ffffffefffff)
  62.336 +#define SH_RTC3_INT_CONFIG_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.337 +
  62.338 +/*   SH_RTC3_INT_CONFIG_TYPE                                            */
  62.339 +/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  62.340 +#define SH_RTC3_INT_CONFIG_TYPE_SHFT			0
  62.341 +#define SH_RTC3_INT_CONFIG_TYPE_MASK	__IA64_UL_CONST(0x0000000000000007)
  62.342 +
  62.343 +/*   SH_RTC3_INT_CONFIG_AGT                                             */
  62.344 +/*   Description:  Agent, must be 0 for SHub                            */
  62.345 +#define SH_RTC3_INT_CONFIG_AGT_SHFT			3
  62.346 +#define SH_RTC3_INT_CONFIG_AGT_MASK	__IA64_UL_CONST(0x0000000000000008)
  62.347 +
  62.348 +/*   SH_RTC3_INT_CONFIG_PID                                             */
  62.349 +/*   Description:  Processor ID, same setting as on targeted McKinley  */
  62.350 +#define SH_RTC3_INT_CONFIG_PID_SHFT			4
  62.351 +#define SH_RTC3_INT_CONFIG_PID_MASK	__IA64_UL_CONST(0x00000000000ffff0)
  62.352 +
  62.353 +/*   SH_RTC3_INT_CONFIG_BASE                                            */
  62.354 +/*   Description:  Optional interrupt vector area, 2MB aligned          */
  62.355 +#define SH_RTC3_INT_CONFIG_BASE_SHFT			21
  62.356 +#define SH_RTC3_INT_CONFIG_BASE_MASK	__IA64_UL_CONST(0x0003ffffffe00000)
  62.357 +
  62.358 +/*   SH_RTC3_INT_CONFIG_IDX                                             */
  62.359 +/*   Description:  Targeted McKinley interrupt vector                   */
  62.360 +#define SH_RTC3_INT_CONFIG_IDX_SHFT			52
  62.361 +#define SH_RTC3_INT_CONFIG_IDX_MASK	__IA64_UL_CONST(0x0ff0000000000000)
  62.362 +
  62.363 +/* ==================================================================== */
  62.364 +/*                    Register "SH_RTC3_INT_ENABLE"                     */
  62.365 +/*                SHub RTC 3 Interrupt Enable Registers                 */
  62.366 +/* ==================================================================== */
  62.367 +
  62.368 +#define SH1_RTC3_INT_ENABLE		__IA64_UL_CONST(0x0000000110001700)
  62.369 +#define SH2_RTC3_INT_ENABLE		__IA64_UL_CONST(0x0000000010001700)
  62.370 +#define SH_RTC3_INT_ENABLE_MASK		__IA64_UL_CONST(0x0000000000000001)
  62.371 +#define SH_RTC3_INT_ENABLE_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.372 +
  62.373 +/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
  62.374 +/*   Description:  Enable RTC 3 Interrupt                               */
  62.375 +#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT		0
  62.376 +#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
  62.377 +					__IA64_UL_CONST(0x0000000000000001)
  62.378 +
  62.379 +/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
  62.380 +/*   Description:  Pending RTC 1 Interrupt                              */
  62.381 +#define SH_EVENT_OCCURRED_RTC1_INT_SHFT			24
  62.382 +#define SH_EVENT_OCCURRED_RTC1_INT_MASK	__IA64_UL_CONST(0x0000000001000000)
  62.383 +
  62.384 +/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
  62.385 +/*   Description:  Pending RTC 2 Interrupt                              */
  62.386 +#define SH_EVENT_OCCURRED_RTC2_INT_SHFT			25
  62.387 +#define SH_EVENT_OCCURRED_RTC2_INT_MASK	__IA64_UL_CONST(0x0000000002000000)
  62.388 +
  62.389 +/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
  62.390 +/*   Description:  Pending RTC 3 Interrupt                              */
  62.391 +#define SH_EVENT_OCCURRED_RTC3_INT_SHFT			26
  62.392 +#define SH_EVENT_OCCURRED_RTC3_INT_MASK	__IA64_UL_CONST(0x0000000004000000)
  62.393 +
  62.394 +/* ==================================================================== */
  62.395 +/*                       Register "SH_IPI_ACCESS"                       */
  62.396 +/*                 CPU interrupt Access Permission Bits                 */
  62.397 +/* ==================================================================== */
  62.398 +
  62.399 +#define SH1_IPI_ACCESS			__IA64_UL_CONST(0x0000000110060480)
  62.400 +#define SH2_IPI_ACCESS0			__IA64_UL_CONST(0x0000000010060c00)
  62.401 +#define SH2_IPI_ACCESS1			__IA64_UL_CONST(0x0000000010060c80)
  62.402 +#define SH2_IPI_ACCESS2			__IA64_UL_CONST(0x0000000010060d00)
  62.403 +#define SH2_IPI_ACCESS3			__IA64_UL_CONST(0x0000000010060d80)
  62.404 +
  62.405 +/* ==================================================================== */
  62.406 +/*                        Register "SH_INT_CMPB"                        */
  62.407 +/*                  RTC Compare Value for Processor B                   */
  62.408 +/* ==================================================================== */
  62.409 +
  62.410 +#define SH1_INT_CMPB			__IA64_UL_CONST(0x00000001101b0080)
  62.411 +#define SH2_INT_CMPB			__IA64_UL_CONST(0x00000000101b0080)
  62.412 +#define SH_INT_CMPB_MASK		__IA64_UL_CONST(0x007fffffffffffff)
  62.413 +#define SH_INT_CMPB_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.414 +
  62.415 +/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
  62.416 +/*   Description:  Real Time Clock Compare                              */
  62.417 +#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT			0
  62.418 +#define SH_INT_CMPB_REAL_TIME_CMPB_MASK	__IA64_UL_CONST(0x007fffffffffffff)
  62.419 +
  62.420 +/* ==================================================================== */
  62.421 +/*                        Register "SH_INT_CMPC"                        */
  62.422 +/*                  RTC Compare Value for Processor C                   */
  62.423 +/* ==================================================================== */
  62.424 +
  62.425 +#define SH1_INT_CMPC			__IA64_UL_CONST(0x00000001101b0100)
  62.426 +#define SH2_INT_CMPC			__IA64_UL_CONST(0x00000000101b0100)
  62.427 +#define SH_INT_CMPC_MASK		__IA64_UL_CONST(0x007fffffffffffff)
  62.428 +#define SH_INT_CMPC_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.429 +
  62.430 +/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
  62.431 +/*   Description:  Real Time Clock Compare                              */
  62.432 +#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT			0
  62.433 +#define SH_INT_CMPC_REAL_TIME_CMPC_MASK	__IA64_UL_CONST(0x007fffffffffffff)
  62.434 +
  62.435 +/* ==================================================================== */
  62.436 +/*                        Register "SH_INT_CMPD"                        */
  62.437 +/*                  RTC Compare Value for Processor D                   */
  62.438 +/* ==================================================================== */
  62.439 +
  62.440 +#define SH1_INT_CMPD			__IA64_UL_CONST(0x00000001101b0180)
  62.441 +#define SH2_INT_CMPD			__IA64_UL_CONST(0x00000000101b0180)
  62.442 +#define SH_INT_CMPD_MASK		__IA64_UL_CONST(0x007fffffffffffff)
  62.443 +#define SH_INT_CMPD_INIT		__IA64_UL_CONST(0x0000000000000000)
  62.444 +
  62.445 +/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
  62.446 +/*   Description:  Real Time Clock Compare                              */
  62.447 +#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT			0
  62.448 +#define SH_INT_CMPD_REAL_TIME_CMPD_MASK	__IA64_UL_CONST(0x007fffffffffffff)
  62.449 +
  62.450 +/* ==================================================================== */
  62.451 +/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
  62.452 +/*                      privilege vector for acc=0                      */
  62.453 +/* ==================================================================== */
  62.454 +#define SH1_MD_DQLP_MMR_DIR_PRIVEC0	__IA64_UL_CONST(0x0000000100030300)
  62.455 +
  62.456 +/* ==================================================================== */
  62.457 +/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
  62.458 +/*                      privilege vector for acc=0                      */
  62.459 +/* ==================================================================== */
  62.460 +#define SH1_MD_DQRP_MMR_DIR_PRIVEC0	__IA64_UL_CONST(0x0000000100050300)
  62.461 +
  62.462 +/* ==================================================================== */
  62.463 +/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
  62.464 +/* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
  62.465 +/* It is acceptible to use (for example) SH_IPI_INT to reference the    */
  62.466 +/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
  62.467 +/* on the type of the SHUB. Do not use these #defines in performance    */
  62.468 +/* critical code  or loops - there is a small performance penalty.      */
  62.469 +/* ==================================================================== */
  62.470 +#define shubmmr(a,b) 		(is_shub2() ? a##2_##b : a##1_##b)
  62.471 +
  62.472 +#define SH_REAL_JUNK_BUS_LED0	shubmmr(SH, REAL_JUNK_BUS_LED0)
  62.473 +#define SH_IPI_INT		shubmmr(SH, IPI_INT)
  62.474 +#define SH_EVENT_OCCURRED	shubmmr(SH, EVENT_OCCURRED)
  62.475 +#define SH_EVENT_OCCURRED_ALIAS	shubmmr(SH, EVENT_OCCURRED_ALIAS)
  62.476 +#define SH_RTC			shubmmr(SH, RTC)
  62.477 +#define SH_RTC1_INT_CONFIG	shubmmr(SH, RTC1_INT_CONFIG)
  62.478 +#define SH_RTC1_INT_ENABLE	shubmmr(SH, RTC1_INT_ENABLE)
  62.479 +#define SH_RTC2_INT_CONFIG	shubmmr(SH, RTC2_INT_CONFIG)
  62.480 +#define SH_RTC2_INT_ENABLE	shubmmr(SH, RTC2_INT_ENABLE)
  62.481 +#define SH_RTC3_INT_CONFIG	shubmmr(SH, RTC3_INT_CONFIG)
  62.482 +#define SH_RTC3_INT_ENABLE	shubmmr(SH, RTC3_INT_ENABLE)
  62.483 +#define SH_INT_CMPB		shubmmr(SH, INT_CMPB)
  62.484 +#define SH_INT_CMPC		shubmmr(SH, INT_CMPC)
  62.485 +#define SH_INT_CMPD		shubmmr(SH, INT_CMPD)
  62.486 +
  62.487 +/* ========================================================================== */
  62.488 +/*                        Register "SH2_BT_ENG_CSR_0"                         */
  62.489 +/*                    Engine 0 Control and Status Register                    */
  62.490 +/* ========================================================================== */
  62.491 +
  62.492 +#define SH2_BT_ENG_CSR_0		__IA64_UL_CONST(0x0000000030040000)
  62.493 +#define SH2_BT_ENG_SRC_ADDR_0		__IA64_UL_CONST(0x0000000030040080)
  62.494 +#define SH2_BT_ENG_DEST_ADDR_0		__IA64_UL_CONST(0x0000000030040100)
  62.495 +#define SH2_BT_ENG_NOTIF_ADDR_0		__IA64_UL_CONST(0x0000000030040180)
  62.496 +
  62.497 +/* ========================================================================== */
  62.498 +/*                       BTE interfaces 1-3                                   */
  62.499 +/* ========================================================================== */
  62.500 +
  62.501 +#define SH2_BT_ENG_CSR_1		__IA64_UL_CONST(0x0000000030050000)
  62.502 +#define SH2_BT_ENG_CSR_2		__IA64_UL_CONST(0x0000000030060000)
  62.503 +#define SH2_BT_ENG_CSR_3		__IA64_UL_CONST(0x0000000030070000)
  62.504 +
  62.505 +#endif /* _ASM_IA64_SN_SHUB_MMR_H */
    63.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    63.2 +++ b/xen/include/asm-ia64/linux/asm/sn/shubio.h	Wed Dec 13 11:08:40 2006 -0700
    63.3 @@ -0,0 +1,3358 @@
    63.4 +/*
    63.5 + * This file is subject to the terms and conditions of the GNU General Public
    63.6 + * License.  See the file "COPYING" in the main directory of this archive
    63.7 + * for more details.
    63.8 + *
    63.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
   63.10 + */
   63.11 +
   63.12 +#ifndef _ASM_IA64_SN_SHUBIO_H
   63.13 +#define _ASM_IA64_SN_SHUBIO_H
   63.14 +
   63.15 +#define HUB_WIDGET_ID_MAX	0xf
   63.16 +#define IIO_NUM_ITTES		7
   63.17 +#define HUB_NUM_BIG_WINDOW	(IIO_NUM_ITTES - 1)
   63.18 +
   63.19 +#define		IIO_WID			0x00400000	/* Crosstalk Widget Identification */
   63.20 +							/* This register is also accessible from
   63.21 +							 * Crosstalk at address 0x0.  */
   63.22 +#define		IIO_WSTAT		0x00400008	/* Crosstalk Widget Status */
   63.23 +#define		IIO_WCR			0x00400020	/* Crosstalk Widget Control Register */
   63.24 +#define		IIO_ILAPR		0x00400100	/* IO Local Access Protection Register */
   63.25 +#define		IIO_ILAPO		0x00400108	/* IO Local Access Protection Override */
   63.26 +#define		IIO_IOWA		0x00400110	/* IO Outbound Widget Access */
   63.27 +#define		IIO_IIWA		0x00400118	/* IO Inbound Widget Access */
   63.28 +#define		IIO_IIDEM		0x00400120	/* IO Inbound Device Error Mask */
   63.29 +#define		IIO_ILCSR		0x00400128	/* IO LLP Control and Status Register */
   63.30 +#define		IIO_ILLR		0x00400130	/* IO LLP Log Register    */
   63.31 +#define		IIO_IIDSR		0x00400138	/* IO Interrupt Destination */
   63.32 +
   63.33 +#define		IIO_IGFX0		0x00400140	/* IO Graphics Node-Widget Map 0 */
   63.34 +#define		IIO_IGFX1		0x00400148	/* IO Graphics Node-Widget Map 1 */
   63.35 +
   63.36 +#define		IIO_ISCR0		0x00400150	/* IO Scratch Register 0 */
   63.37 +#define		IIO_ISCR1		0x00400158	/* IO Scratch Register 1 */
   63.38 +
   63.39 +#define		IIO_ITTE1		0x00400160	/* IO Translation Table Entry 1 */
   63.40 +#define		IIO_ITTE2		0x00400168	/* IO Translation Table Entry 2 */
   63.41 +#define		IIO_ITTE3		0x00400170	/* IO Translation Table Entry 3 */
   63.42 +#define		IIO_ITTE4		0x00400178	/* IO Translation Table Entry 4 */
   63.43 +#define		IIO_ITTE5		0x00400180	/* IO Translation Table Entry 5 */
   63.44 +#define		IIO_ITTE6		0x00400188	/* IO Translation Table Entry 6 */
   63.45 +#define		IIO_ITTE7		0x00400190	/* IO Translation Table Entry 7 */
   63.46 +
   63.47 +#define		IIO_IPRB0		0x00400198	/* IO PRB Entry 0   */
   63.48 +#define		IIO_IPRB8		0x004001A0	/* IO PRB Entry 8   */
   63.49 +#define		IIO_IPRB9		0x004001A8	/* IO PRB Entry 9   */
   63.50 +#define		IIO_IPRBA		0x004001B0	/* IO PRB Entry A   */
   63.51 +#define		IIO_IPRBB		0x004001B8	/* IO PRB Entry B   */
   63.52 +#define		IIO_IPRBC		0x004001C0	/* IO PRB Entry C   */
   63.53 +#define		IIO_IPRBD		0x004001C8	/* IO PRB Entry D   */
   63.54 +#define		IIO_IPRBE		0x004001D0	/* IO PRB Entry E   */
   63.55 +#define		IIO_IPRBF		0x004001D8	/* IO PRB Entry F   */
   63.56 +
   63.57 +#define		IIO_IXCC		0x004001E0	/* IO Crosstalk Credit Count Timeout */
   63.58 +#define		IIO_IMEM		0x004001E8	/* IO Miscellaneous Error Mask */
   63.59 +#define		IIO_IXTT		0x004001F0	/* IO Crosstalk Timeout Threshold */
   63.60 +#define		IIO_IECLR		0x004001F8	/* IO Error Clear Register */
   63.61 +#define		IIO_IBCR		0x00400200	/* IO BTE Control Register */
   63.62 +
   63.63 +#define		IIO_IXSM		0x00400208	/* IO Crosstalk Spurious Message */
   63.64 +#define		IIO_IXSS		0x00400210	/* IO Crosstalk Spurious Sideband */
   63.65 +
   63.66 +#define		IIO_ILCT		0x00400218	/* IO LLP Channel Test    */
   63.67 +
   63.68 +#define		IIO_IIEPH1 		0x00400220	/* IO Incoming Error Packet Header, Part 1 */
   63.69 +#define		IIO_IIEPH2 		0x00400228	/* IO Incoming Error Packet Header, Part 2 */
   63.70 +
   63.71 +#define		IIO_ISLAPR 		0x00400230	/* IO SXB Local Access Protection Regster */
   63.72 +#define		IIO_ISLAPO 		0x00400238	/* IO SXB Local Access Protection Override */
   63.73 +
   63.74 +#define		IIO_IWI			0x00400240	/* IO Wrapper Interrupt Register */
   63.75 +#define		IIO_IWEL		0x00400248	/* IO Wrapper Error Log Register */
   63.76 +#define		IIO_IWC			0x00400250	/* IO Wrapper Control Register */
   63.77 +#define		IIO_IWS			0x00400258	/* IO Wrapper Status Register */
   63.78 +#define		IIO_IWEIM		0x00400260	/* IO Wrapper Error Interrupt Masking Register */
   63.79 +
   63.80 +#define		IIO_IPCA		0x00400300	/* IO PRB Counter Adjust */
   63.81 +
   63.82 +#define		IIO_IPRTE0_A		0x00400308	/* IO PIO Read Address Table Entry 0, Part A */
   63.83 +#define		IIO_IPRTE1_A		0x00400310	/* IO PIO Read Address Table Entry 1, Part A */
   63.84 +#define		IIO_IPRTE2_A		0x00400318	/* IO PIO Read Address Table Entry 2, Part A */
   63.85 +#define		IIO_IPRTE3_A		0x00400320	/* IO PIO Read Address Table Entry 3, Part A */
   63.86 +#define		IIO_IPRTE4_A		0x00400328	/* IO PIO Read Address Table Entry 4, Part A */
   63.87 +#define		IIO_IPRTE5_A		0x00400330	/* IO PIO Read Address Table Entry 5, Part A */
   63.88 +#define		IIO_IPRTE6_A		0x00400338	/* IO PIO Read Address Table Entry 6, Part A */
   63.89 +#define		IIO_IPRTE7_A		0x00400340	/* IO PIO Read Address Table Entry 7, Part A */
   63.90 +
   63.91 +#define		IIO_IPRTE0_B		0x00400348	/* IO PIO Read Address Table Entry 0, Part B */
   63.92 +#define		IIO_IPRTE1_B		0x00400350	/* IO PIO Read Address Table Entry 1, Part B */
   63.93 +#define		IIO_IPRTE2_B		0x00400358	/* IO PIO Read Address Table Entry 2, Part B */
   63.94 +#define		IIO_IPRTE3_B		0x00400360	/* IO PIO Read Address Table Entry 3, Part B */
   63.95 +#define		IIO_IPRTE4_B		0x00400368	/* IO PIO Read Address Table Entry 4, Part B */
   63.96 +#define		IIO_IPRTE5_B		0x00400370	/* IO PIO Read Address Table Entry 5, Part B */
   63.97 +#define		IIO_IPRTE6_B		0x00400378	/* IO PIO Read Address Table Entry 6, Part B */
   63.98 +#define		IIO_IPRTE7_B		0x00400380	/* IO PIO Read Address Table Entry 7, Part B */
   63.99 +
  63.100 +#define		IIO_IPDR		0x00400388	/* IO PIO Deallocation Register */
  63.101 +#define		IIO_ICDR		0x00400390	/* IO CRB Entry Deallocation Register */
  63.102 +#define		IIO_IFDR		0x00400398	/* IO IOQ FIFO Depth Register */
  63.103 +#define		IIO_IIAP		0x004003A0	/* IO IIQ Arbitration Parameters */
  63.104 +#define		IIO_ICMR		0x004003A8	/* IO CRB Management Register */
  63.105 +#define		IIO_ICCR		0x004003B0	/* IO CRB Control Register */
  63.106 +#define		IIO_ICTO		0x004003B8	/* IO CRB Timeout   */
  63.107 +#define		IIO_ICTP		0x004003C0	/* IO CRB Timeout Prescalar */
  63.108 +
  63.109 +#define		IIO_ICRB0_A		0x00400400	/* IO CRB Entry 0_A */
  63.110 +#define		IIO_ICRB0_B		0x00400408	/* IO CRB Entry 0_B */
  63.111 +#define		IIO_ICRB0_C		0x00400410	/* IO CRB Entry 0_C */
  63.112 +#define		IIO_ICRB0_D		0x00400418	/* IO CRB Entry 0_D */
  63.113 +#define		IIO_ICRB0_E		0x00400420	/* IO CRB Entry 0_E */
  63.114 +
  63.115 +#define		IIO_ICRB1_A		0x00400430	/* IO CRB Entry 1_A */
  63.116 +#define		IIO_ICRB1_B		0x00400438	/* IO CRB Entry 1_B */
  63.117 +#define		IIO_ICRB1_C		0x00400440	/* IO CRB Entry 1_C */
  63.118 +#define		IIO_ICRB1_D		0x00400448	/* IO CRB Entry 1_D */
  63.119 +#define		IIO_ICRB1_E		0x00400450	/* IO CRB Entry 1_E */
  63.120 +
  63.121 +#define		IIO_ICRB2_A		0x00400460	/* IO CRB Entry 2_A */
  63.122 +#define		IIO_ICRB2_B		0x00400468	/* IO CRB Entry 2_B */
  63.123 +#define		IIO_ICRB2_C		0x00400470	/* IO CRB Entry 2_C */
  63.124 +#define		IIO_ICRB2_D		0x00400478	/* IO CRB Entry 2_D */
  63.125 +#define		IIO_ICRB2_E		0x00400480	/* IO CRB Entry 2_E */
  63.126 +
  63.127 +#define		IIO_ICRB3_A		0x00400490	/* IO CRB Entry 3_A */
  63.128 +#define		IIO_ICRB3_B		0x00400498	/* IO CRB Entry 3_B */
  63.129 +#define		IIO_ICRB3_C		0x004004a0	/* IO CRB Entry 3_C */
  63.130 +#define		IIO_ICRB3_D		0x004004a8	/* IO CRB Entry 3_D */
  63.131 +#define		IIO_ICRB3_E		0x004004b0	/* IO CRB Entry 3_E */
  63.132 +
  63.133 +#define		IIO_ICRB4_A		0x004004c0	/* IO CRB Entry 4_A */
  63.134 +#define		IIO_ICRB4_B		0x004004c8	/* IO CRB Entry 4_B */
  63.135 +#define		IIO_ICRB4_C		0x004004d0	/* IO CRB Entry 4_C */
  63.136 +#define		IIO_ICRB4_D		0x004004d8	/* IO CRB Entry 4_D */
  63.137 +#define		IIO_ICRB4_E		0x004004e0	/* IO CRB Entry 4_E */
  63.138 +
  63.139 +#define		IIO_ICRB5_A		0x004004f0	/* IO CRB Entry 5_A */
  63.140 +#define		IIO_ICRB5_B		0x004004f8	/* IO CRB Entry 5_B */
  63.141 +#define		IIO_ICRB5_C		0x00400500	/* IO CRB Entry 5_C */
  63.142 +#define		IIO_ICRB5_D		0x00400508	/* IO CRB Entry 5_D */
  63.143 +#define		IIO_ICRB5_E		0x00400510	/* IO CRB Entry 5_E */
  63.144 +
  63.145 +#define		IIO_ICRB6_A		0x00400520	/* IO CRB Entry 6_A */
  63.146 +#define		IIO_ICRB6_B		0x00400528	/* IO CRB Entry 6_B */
  63.147 +#define		IIO_ICRB6_C		0x00400530	/* IO CRB Entry 6_C */
  63.148 +#define		IIO_ICRB6_D		0x00400538	/* IO CRB Entry 6_D */
  63.149 +#define		IIO_ICRB6_E		0x00400540	/* IO CRB Entry 6_E */
  63.150 +
  63.151 +#define		IIO_ICRB7_A		0x00400550	/* IO CRB Entry 7_A */
  63.152 +#define		IIO_ICRB7_B		0x00400558	/* IO CRB Entry 7_B */
  63.153 +#define		IIO_ICRB7_C		0x00400560	/* IO CRB Entry 7_C */
  63.154 +#define		IIO_ICRB7_D		0x00400568	/* IO CRB Entry 7_D */
  63.155 +#define		IIO_ICRB7_E		0x00400570	/* IO CRB Entry 7_E */
  63.156 +
  63.157 +#define		IIO_ICRB8_A		0x00400580	/* IO CRB Entry 8_A */
  63.158 +#define		IIO_ICRB8_B		0x00400588	/* IO CRB Entry 8_B */
  63.159 +#define		IIO_ICRB8_C		0x00400590	/* IO CRB Entry 8_C */
  63.160 +#define		IIO_ICRB8_D		0x00400598	/* IO CRB Entry 8_D */
  63.161 +#define		IIO_ICRB8_E		0x004005a0	/* IO CRB Entry 8_E */
  63.162 +
  63.163 +#define		IIO_ICRB9_A		0x004005b0	/* IO CRB Entry 9_A */
  63.164 +#define		IIO_ICRB9_B		0x004005b8	/* IO CRB Entry 9_B */
  63.165 +#define		IIO_ICRB9_C		0x004005c0	/* IO CRB Entry 9_C */
  63.166 +#define		IIO_ICRB9_D		0x004005c8	/* IO CRB Entry 9_D */
  63.167 +#define		IIO_ICRB9_E		0x004005d0	/* IO CRB Entry 9_E */
  63.168 +
  63.169 +#define		IIO_ICRBA_A		0x004005e0	/* IO CRB Entry A_A */
  63.170 +#define		IIO_ICRBA_B		0x004005e8	/* IO CRB Entry A_B */
  63.171 +#define		IIO_ICRBA_C		0x004005f0	/* IO CRB Entry A_C */
  63.172 +#define		IIO_ICRBA_D		0x004005f8	/* IO CRB Entry A_D */
  63.173 +#define		IIO_ICRBA_E		0x00400600	/* IO CRB Entry A_E */
  63.174 +
  63.175 +#define		IIO_ICRBB_A		0x00400610	/* IO CRB Entry B_A */
  63.176 +#define		IIO_ICRBB_B		0x00400618	/* IO CRB Entry B_B */
  63.177 +#define		IIO_ICRBB_C		0x00400620	/* IO CRB Entry B_C */
  63.178 +#define		IIO_ICRBB_D		0x00400628	/* IO CRB Entry B_D */
  63.179 +#define		IIO_ICRBB_E		0x00400630	/* IO CRB Entry B_E */
  63.180 +
  63.181 +#define		IIO_ICRBC_A		0x00400640	/* IO CRB Entry C_A */
  63.182 +#define		IIO_ICRBC_B		0x00400648	/* IO CRB Entry C_B */
  63.183 +#define		IIO_ICRBC_C		0x00400650	/* IO CRB Entry C_C */
  63.184 +#define		IIO_ICRBC_D		0x00400658	/* IO CRB Entry C_D */
  63.185 +#define		IIO_ICRBC_E		0x00400660	/* IO CRB Entry C_E */
  63.186 +
  63.187 +#define		IIO_ICRBD_A		0x00400670	/* IO CRB Entry D_A */
  63.188 +#define		IIO_ICRBD_B		0x00400678	/* IO CRB Entry D_B */
  63.189 +#define		IIO_ICRBD_C		0x00400680	/* IO CRB Entry D_C */
  63.190 +#define		IIO_ICRBD_D		0x00400688	/* IO CRB Entry D_D */
  63.191 +#define		IIO_ICRBD_E		0x00400690	/* IO CRB Entry D_E */
  63.192 +
  63.193 +#define		IIO_ICRBE_A		0x004006a0	/* IO CRB Entry E_A */
  63.194 +#define		IIO_ICRBE_B		0x004006a8	/* IO CRB Entry E_B */
  63.195 +#define		IIO_ICRBE_C		0x004006b0	/* IO CRB Entry E_C */
  63.196 +#define		IIO_ICRBE_D		0x004006b8	/* IO CRB Entry E_D */
  63.197 +#define		IIO_ICRBE_E		0x004006c0	/* IO CRB Entry E_E */
  63.198 +
  63.199 +#define		IIO_ICSML		0x00400700	/* IO CRB Spurious Message Low */
  63.200 +#define		IIO_ICSMM		0x00400708	/* IO CRB Spurious Message Middle */
  63.201 +#define		IIO_ICSMH		0x00400710	/* IO CRB Spurious Message High */
  63.202 +
  63.203 +#define		IIO_IDBSS		0x00400718	/* IO Debug Submenu Select */
  63.204 +
  63.205 +#define		IIO_IBLS0		0x00410000	/* IO BTE Length Status 0 */
  63.206 +#define		IIO_IBSA0		0x00410008	/* IO BTE Source Address 0 */
  63.207 +#define		IIO_IBDA0		0x00410010	/* IO BTE Destination Address 0 */
  63.208 +#define		IIO_IBCT0		0x00410018	/* IO BTE Control Terminate 0 */
  63.209 +#define		IIO_IBNA0		0x00410020	/* IO BTE Notification Address 0 */
  63.210 +#define		IIO_IBIA0		0x00410028	/* IO BTE Interrupt Address 0 */
  63.211 +#define		IIO_IBLS1		0x00420000	/* IO BTE Length Status 1 */
  63.212 +#define		IIO_IBSA1		0x00420008	/* IO BTE Source Address 1 */
  63.213 +#define		IIO_IBDA1		0x00420010	/* IO BTE Destination Address 1 */
  63.214 +#define		IIO_IBCT1		0x00420018	/* IO BTE Control Terminate 1 */
  63.215 +#define		IIO_IBNA1		0x00420020	/* IO BTE Notification Address 1 */
  63.216 +#define		IIO_IBIA1		0x00420028	/* IO BTE Interrupt Address 1 */
  63.217 +
  63.218 +#define		IIO_IPCR		0x00430000	/* IO Performance Control */
  63.219 +#define		IIO_IPPR		0x00430008	/* IO Performance Profiling */
  63.220 +
  63.221 +/************************************************************************
  63.222 + *									*
  63.223 + * Description:  This register echoes some information from the         *
  63.224 + * LB_REV_ID register. It is available through Crosstalk as described   *
  63.225 + * above. The REV_NUM and MFG_NUM fields receive their values from      *
  63.226 + * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
  63.227 + * The PART_NUM field's value is the Crosstalk device ID number that    *
  63.228 + * Steve Miller assigned to the SHub chip.                              *
  63.229 + *									*
  63.230 + ************************************************************************/
  63.231 +
  63.232 +typedef union ii_wid_u {
  63.233 +	u64 ii_wid_regval;
  63.234 +	struct {
  63.235 +		u64 w_rsvd_1:1;
  63.236 +		u64 w_mfg_num:11;
  63.237 +		u64 w_part_num:16;
  63.238 +		u64 w_rev_num:4;
  63.239 +		u64 w_rsvd:32;
  63.240 +	} ii_wid_fld_s;
  63.241 +} ii_wid_u_t;
  63.242 +
  63.243 +/************************************************************************
  63.244 + *									*
  63.245 + *  The fields in this register are set upon detection of an error      *
  63.246 + * and cleared by various mechanisms, as explained in the               *
  63.247 + * description.                                                         *
  63.248 + *									*
  63.249 + ************************************************************************/
  63.250 +
  63.251 +typedef union ii_wstat_u {
  63.252 +	u64 ii_wstat_regval;
  63.253 +	struct {
  63.254 +		u64 w_pending:4;
  63.255 +		u64 w_xt_crd_to:1;
  63.256 +		u64 w_xt_tail_to:1;
  63.257 +		u64 w_rsvd_3:3;
  63.258 +		u64 w_tx_mx_rty:1;
  63.259 +		u64 w_rsvd_2:6;
  63.260 +		u64 w_llp_tx_cnt:8;
  63.261 +		u64 w_rsvd_1:8;
  63.262 +		u64 w_crazy:1;
  63.263 +		u64 w_rsvd:31;
  63.264 +	} ii_wstat_fld_s;
  63.265 +} ii_wstat_u_t;
  63.266 +
  63.267 +/************************************************************************
  63.268 + *									*
  63.269 + * Description:  This is a read-write enabled register. It controls     *
  63.270 + * various aspects of the Crosstalk flow control.                       *
  63.271 + *									*
  63.272 + ************************************************************************/
  63.273 +
  63.274 +typedef union ii_wcr_u {
  63.275 +	u64 ii_wcr_regval;
  63.276 +	struct {
  63.277 +		u64 w_wid:4;
  63.278 +		u64 w_tag:1;
  63.279 +		u64 w_rsvd_1:8;
  63.280 +		u64 w_dst_crd:3;
  63.281 +		u64 w_f_bad_pkt:1;
  63.282 +		u64 w_dir_con:1;
  63.283 +		u64 w_e_thresh:5;
  63.284 +		u64 w_rsvd:41;
  63.285 +	} ii_wcr_fld_s;
  63.286 +} ii_wcr_u_t;
  63.287 +
  63.288 +/************************************************************************
  63.289 + *									*
  63.290 + * Description:  This register's value is a bit vector that guards      *
  63.291 + * access to local registers within the II as well as to external       *
  63.292 + * Crosstalk widgets. Each bit in the register corresponds to a         *
  63.293 + * particular region in the system; a region consists of one, two or    *
  63.294 + * four nodes (depending on the value of the REGION_SIZE field in the   *
  63.295 + * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
  63.296 + * protection provided by this register applies to PIO read             *
  63.297 + * operations as well as PIO write operations. The II will perform a    *
  63.298 + * PIO read or write request only if the bit for the requestor's        *
  63.299 + * region is set; otherwise, the II will not perform the requested      *
  63.300 + * operation and will return an error response. When a PIO read or      *
  63.301 + * write request targets an external Crosstalk widget, then not only    *
  63.302 + * must the bit for the requestor's region be set in the ILAPR, but     *
  63.303 + * also the target widget's bit in the IOWA register must be set in     *
  63.304 + * order for the II to perform the requested operation; otherwise,      *
  63.305 + * the II will return an error response. Hence, the protection          *
  63.306 + * provided by the IOWA register supplements the protection provided    *
  63.307 + * by the ILAPR for requests that target external Crosstalk widgets.    *
  63.308 + * This register itself can be accessed only by the nodes whose         *
  63.309 + * region ID bits are enabled in this same register. It can also be     *
  63.310 + * accessed through the IAlias space by the local processors.           *
  63.311 + * The reset value of this register allows access by all nodes.         *
  63.312 + *									*
  63.313 + ************************************************************************/
  63.314 +
  63.315 +typedef union ii_ilapr_u {
  63.316 +	u64 ii_ilapr_regval;
  63.317 +	struct {
  63.318 +		u64 i_region:64;
  63.319 +	} ii_ilapr_fld_s;
  63.320 +} ii_ilapr_u_t;
  63.321 +
  63.322 +/************************************************************************
  63.323 + *									*
  63.324 + * Description:  A write to this register of the 64-bit value           *
  63.325 + * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
  63.326 + * corresponding to the region of the requestor to be set (allow        *
  63.327 + * access). A write of any other value will be ignored. Access          *
  63.328 + * protection for this register is "SGIrules".                          *
  63.329 + * This register can also be accessed through the IAlias space.         *
  63.330 + * However, this access will not change the access permissions in the   *
  63.331 + * ILAPR.                                                               *
  63.332 + *									*
  63.333 + ************************************************************************/
  63.334 +
  63.335 +typedef union ii_ilapo_u {
  63.336 +	u64 ii_ilapo_regval;
  63.337 +	struct {
  63.338 +		u64 i_io_ovrride:64;
  63.339 +	} ii_ilapo_fld_s;
  63.340 +} ii_ilapo_u_t;
  63.341 +
  63.342 +/************************************************************************
  63.343 + *									*
  63.344 + *  This register qualifies all the PIO and Graphics writes launched    *
  63.345 + * from the SHUB towards a widget.                                      *
  63.346 + *									*
  63.347 + ************************************************************************/
  63.348 +
  63.349 +typedef union ii_iowa_u {
  63.350 +	u64 ii_iowa_regval;
  63.351 +	struct {
  63.352 +		u64 i_w0_oac:1;
  63.353 +		u64 i_rsvd_1:7;
  63.354 +		u64 i_wx_oac:8;
  63.355 +		u64 i_rsvd:48;
  63.356 +	} ii_iowa_fld_s;
  63.357 +} ii_iowa_u_t;
  63.358 +
  63.359 +/************************************************************************
  63.360 + *									*
  63.361 + * Description:  This register qualifies all the requests launched      *
  63.362 + * from a widget towards the Shub. This register is intended to be      *
  63.363 + * used by software in case of misbehaving widgets.                     *
  63.364 + *									*
  63.365 + *									*
  63.366 + ************************************************************************/
  63.367 +
  63.368 +typedef union ii_iiwa_u {
  63.369 +	u64 ii_iiwa_regval;
  63.370 +	struct {
  63.371 +		u64 i_w0_iac:1;
  63.372 +		u64 i_rsvd_1:7;
  63.373 +		u64 i_wx_iac:8;
  63.374 +		u64 i_rsvd:48;
  63.375 +	} ii_iiwa_fld_s;
  63.376 +} ii_iiwa_u_t;
  63.377 +
  63.378 +/************************************************************************
  63.379 + *									*
  63.380 + * Description:  This register qualifies all the operations launched    *
  63.381 + * from a widget towards the SHub. It allows individual access          *
  63.382 + * control for up to 8 devices per widget. A device refers to           *
  63.383 + * individual DMA master hosted by a widget.                            *
  63.384 + * The bits in each field of this register are cleared by the Shub      *
  63.385 + * upon detection of an error which requires the device to be           *
  63.386 + * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
  63.387 + * Crosstalk). Whether or not a device has access rights to this        *
  63.388 + * Shub is determined by an AND of the device enable bit in the         *
  63.389 + * appropriate field of this register and the corresponding bit in      *
  63.390 + * the Wx_IAC field (for the widget which this device belongs to).      *
  63.391 + * The bits in this field are set by writing a 1 to them. Incoming      *
  63.392 + * replies from Crosstalk are not subject to this access control        *
  63.393 + * mechanism.                                                           *
  63.394 + *									*
  63.395 + ************************************************************************/
  63.396 +
  63.397 +typedef union ii_iidem_u {
  63.398 +	u64 ii_iidem_regval;
  63.399 +	struct {
  63.400 +		u64 i_w8_dxs:8;
  63.401 +		u64 i_w9_dxs:8;
  63.402 +		u64 i_wa_dxs:8;
  63.403 +		u64 i_wb_dxs:8;
  63.404 +		u64 i_wc_dxs:8;
  63.405 +		u64 i_wd_dxs:8;
  63.406 +		u64 i_we_dxs:8;
  63.407 +		u64 i_wf_dxs:8;
  63.408 +	} ii_iidem_fld_s;
  63.409 +} ii_iidem_u_t;
  63.410 +
  63.411 +/************************************************************************
  63.412 + *									*
  63.413 + *  This register contains the various programmable fields necessary    *
  63.414 + * for controlling and observing the LLP signals.                       *
  63.415 + *									*
  63.416 + ************************************************************************/
  63.417 +
  63.418 +typedef union ii_ilcsr_u {
  63.419 +	u64 ii_ilcsr_regval;
  63.420 +	struct {
  63.421 +		u64 i_nullto:6;
  63.422 +		u64 i_rsvd_4:2;
  63.423 +		u64 i_wrmrst:1;
  63.424 +		u64 i_rsvd_3:1;
  63.425 +		u64 i_llp_en:1;
  63.426 +		u64 i_bm8:1;
  63.427 +		u64 i_llp_stat:2;
  63.428 +		u64 i_remote_power:1;
  63.429 +		u64 i_rsvd_2:1;
  63.430 +		u64 i_maxrtry:10;
  63.431 +		u64 i_d_avail_sel:2;
  63.432 +		u64 i_rsvd_1:4;
  63.433 +		u64 i_maxbrst:10;
  63.434 +		u64 i_rsvd:22;
  63.435 +
  63.436 +	} ii_ilcsr_fld_s;
  63.437 +} ii_ilcsr_u_t;
  63.438 +
  63.439 +/************************************************************************
  63.440 + *									*
  63.441 + *  This is simply a status registers that monitors the LLP error       *
  63.442 + * rate.								*
  63.443 + *									*
  63.444 + ************************************************************************/
  63.445 +
  63.446 +typedef union ii_illr_u {
  63.447 +	u64 ii_illr_regval;
  63.448 +	struct {
  63.449 +		u64 i_sn_cnt:16;
  63.450 +		u64 i_cb_cnt:16;
  63.451 +		u64 i_rsvd:32;
  63.452 +	} ii_illr_fld_s;
  63.453 +} ii_illr_u_t;
  63.454 +
  63.455 +/************************************************************************
  63.456 + *									*
  63.457 + * Description:  All II-detected non-BTE error interrupts are           *
  63.458 + * specified via this register.                                         *
  63.459 + * NOTE: The PI interrupt register address is hardcoded in the II. If   *
  63.460 + * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
  63.461 + * packet) to address offset 0x0180_0090 within the local register      *
  63.462 + * address space of PI0 on the node specified by the NODE field. If     *
  63.463 + * PI_ID==1, then the II sends the interrupt request to address         *
  63.464 + * offset 0x01A0_0090 within the local register address space of PI1    *
  63.465 + * on the node specified by the NODE field.                             *
  63.466 + *									*
  63.467 + ************************************************************************/
  63.468 +
  63.469 +typedef union ii_iidsr_u {
  63.470 +	u64 ii_iidsr_regval;
  63.471 +	struct {
  63.472 +		u64 i_level:8;
  63.473 +		u64 i_pi_id:1;
  63.474 +		u64 i_node:11;
  63.475 +		u64 i_rsvd_3:4;
  63.476 +		u64 i_enable:1;
  63.477 +		u64 i_rsvd_2:3;
  63.478 +		u64 i_int_sent:2;
  63.479 +		u64 i_rsvd_1:2;
  63.480 +		u64 i_pi0_forward_int:1;
  63.481 +		u64 i_pi1_forward_int:1;
  63.482 +		u64 i_rsvd:30;
  63.483 +	} ii_iidsr_fld_s;
  63.484 +} ii_iidsr_u_t;
  63.485 +
  63.486 +/************************************************************************
  63.487 + *									*
  63.488 + *  There are two instances of this register. This register is used     *
  63.489 + * for matching up the incoming responses from the graphics widget to   *
  63.490 + * the processor that initiated the graphics operation. The             *
  63.491 + * write-responses are converted to graphics credits and returned to    *
  63.492 + * the processor so that the processor interface can manage the flow    *
  63.493 + * control.                                                             *
  63.494 + *									*
  63.495 + ************************************************************************/
  63.496 +
  63.497 +typedef union ii_igfx0_u {
  63.498 +	u64 ii_igfx0_regval;
  63.499 +	struct {
  63.500 +		u64 i_w_num:4;
  63.501 +		u64 i_pi_id:1;
  63.502 +		u64 i_n_num:12;
  63.503 +		u64 i_p_num:1;
  63.504 +		u64 i_rsvd:46;
  63.505 +	} ii_igfx0_fld_s;
  63.506 +} ii_igfx0_u_t;
  63.507 +
  63.508 +/************************************************************************
  63.509 + *									*
  63.510 + *  There are two instances of this register. This register is used     *
  63.511 + * for matching up the incoming responses from the graphics widget to   *
  63.512 + * the processor that initiated the graphics operation. The             *
  63.513 + * write-responses are converted to graphics credits and returned to    *
  63.514 + * the processor so that the processor interface can manage the flow    *
  63.515 + * control.                                                             *
  63.516 + *									*
  63.517 + ************************************************************************/
  63.518 +
  63.519 +typedef union ii_igfx1_u {
  63.520 +	u64 ii_igfx1_regval;
  63.521 +	struct {
  63.522 +		u64 i_w_num:4;
  63.523 +		u64 i_pi_id:1;
  63.524 +		u64 i_n_num:12;
  63.525 +		u64 i_p_num:1;
  63.526 +		u64 i_rsvd:46;
  63.527 +	} ii_igfx1_fld_s;
  63.528 +} ii_igfx1_u_t;
  63.529 +
  63.530 +/************************************************************************
  63.531 + *									*
  63.532 + *  There are two instances of this registers. These registers are      *
  63.533 + * used as scratch registers for software use.                          *
  63.534 + *									*
  63.535 + ************************************************************************/
  63.536 +
  63.537 +typedef union ii_iscr0_u {
  63.538 +	u64 ii_iscr0_regval;
  63.539 +	struct {
  63.540 +		u64 i_scratch:64;
  63.541 +	} ii_iscr0_fld_s;
  63.542 +} ii_iscr0_u_t;
  63.543 +
  63.544 +/************************************************************************
  63.545 + *									*
  63.546 + *  There are two instances of this registers. These registers are      *
  63.547 + * used as scratch registers for software use.                          *
  63.548 + *									*
  63.549 + ************************************************************************/
  63.550 +
  63.551 +typedef union ii_iscr1_u {
  63.552 +	u64 ii_iscr1_regval;
  63.553 +	struct {
  63.554 +		u64 i_scratch:64;
  63.555 +	} ii_iscr1_fld_s;
  63.556 +} ii_iscr1_u_t;
  63.557 +
  63.558 +/************************************************************************
  63.559 + *									*
  63.560 + * Description:  There are seven instances of translation table entry   *
  63.561 + * registers. Each register maps a Shub Big Window to a 48-bit          *
  63.562 + * address on Crosstalk.                                                *
  63.563 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.564 + * number) are used to select one of these 7 registers. The Widget      *
  63.565 + * number field is then derived from the W_NUM field for synthesizing   *
  63.566 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.567 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.568 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.569 + * addressable by the SHub is thus the lower 16 GBytes per widget       * 
  63.570 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.571 + * space can be accessed.                                               *
  63.572 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.573 + * Window number) are used to select one of these 7 registers. The      *
  63.574 + * Widget number field is then derived from the W_NUM field for         *
  63.575 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.576 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.577 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.578 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.579 + * Crosstalk space addressable by the Shub is thus the lower            *
  63.580 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.581 + * of this space can be accessed.                                       *
  63.582 + *									*
  63.583 + ************************************************************************/
  63.584 +
  63.585 +typedef union ii_itte1_u {
  63.586 +	u64 ii_itte1_regval;
  63.587 +	struct {
  63.588 +		u64 i_offset:5;
  63.589 +		u64 i_rsvd_1:3;
  63.590 +		u64 i_w_num:4;
  63.591 +		u64 i_iosp:1;
  63.592 +		u64 i_rsvd:51;
  63.593 +	} ii_itte1_fld_s;
  63.594 +} ii_itte1_u_t;
  63.595 +
  63.596 +/************************************************************************
  63.597 + *									*
  63.598 + * Description:  There are seven instances of translation table entry   *
  63.599 + * registers. Each register maps a Shub Big Window to a 48-bit          *
  63.600 + * address on Crosstalk.                                                *
  63.601 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.602 + * number) are used to select one of these 7 registers. The Widget      *
  63.603 + * number field is then derived from the W_NUM field for synthesizing   *
  63.604 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.605 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.606 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.607 + * addressable by the Shub is thus the lower 16 GBytes per widget       *
  63.608 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.609 + * space can be accessed.                                               *
  63.610 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.611 + * Window number) are used to select one of these 7 registers. The      *
  63.612 + * Widget number field is then derived from the W_NUM field for         *
  63.613 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.614 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.615 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.616 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.617 + * Crosstalk space addressable by the Shub is thus the lower            *
  63.618 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.619 + * of this space can be accessed.                                       *
  63.620 + *									*
  63.621 + ************************************************************************/
  63.622 +
  63.623 +typedef union ii_itte2_u {
  63.624 +	u64 ii_itte2_regval;
  63.625 +	struct {
  63.626 +		u64 i_offset:5;
  63.627 +		u64 i_rsvd_1:3;
  63.628 +		u64 i_w_num:4;
  63.629 +		u64 i_iosp:1;
  63.630 +		u64 i_rsvd:51;
  63.631 +	} ii_itte2_fld_s;
  63.632 +} ii_itte2_u_t;
  63.633 +
  63.634 +/************************************************************************
  63.635 + *									*
  63.636 + * Description:  There are seven instances of translation table entry   *
  63.637 + * registers. Each register maps a Shub Big Window to a 48-bit          *
  63.638 + * address on Crosstalk.                                                *
  63.639 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.640 + * number) are used to select one of these 7 registers. The Widget      *
  63.641 + * number field is then derived from the W_NUM field for synthesizing   *
  63.642 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.643 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.644 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.645 + * addressable by the Shub is thus the lower 16 GBytes per widget       *
  63.646 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.647 + * space can be accessed.                                               *
  63.648 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.649 + * Window number) are used to select one of these 7 registers. The      *
  63.650 + * Widget number field is then derived from the W_NUM field for         *
  63.651 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.652 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.653 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.654 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.655 + * Crosstalk space addressable by the SHub is thus the lower            *
  63.656 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.657 + * of this space can be accessed.                                       *
  63.658 + *									*
  63.659 + ************************************************************************/
  63.660 +
  63.661 +typedef union ii_itte3_u {
  63.662 +	u64 ii_itte3_regval;
  63.663 +	struct {
  63.664 +		u64 i_offset:5;
  63.665 +		u64 i_rsvd_1:3;
  63.666 +		u64 i_w_num:4;
  63.667 +		u64 i_iosp:1;
  63.668 +		u64 i_rsvd:51;
  63.669 +	} ii_itte3_fld_s;
  63.670 +} ii_itte3_u_t;
  63.671 +
  63.672 +/************************************************************************
  63.673 + *									*
  63.674 + * Description:  There are seven instances of translation table entry   *
  63.675 + * registers. Each register maps a SHub Big Window to a 48-bit          *
  63.676 + * address on Crosstalk.                                                *
  63.677 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.678 + * number) are used to select one of these 7 registers. The Widget      *
  63.679 + * number field is then derived from the W_NUM field for synthesizing   *
  63.680 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.681 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.682 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.683 + * addressable by the SHub is thus the lower 16 GBytes per widget       *
  63.684 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.685 + * space can be accessed.                                               *
  63.686 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.687 + * Window number) are used to select one of these 7 registers. The      *
  63.688 + * Widget number field is then derived from the W_NUM field for         *
  63.689 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.690 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.691 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.692 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.693 + * Crosstalk space addressable by the SHub is thus the lower            *
  63.694 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.695 + * of this space can be accessed.                                       *
  63.696 + *									*
  63.697 + ************************************************************************/
  63.698 +
  63.699 +typedef union ii_itte4_u {
  63.700 +	u64 ii_itte4_regval;
  63.701 +	struct {
  63.702 +		u64 i_offset:5;
  63.703 +		u64 i_rsvd_1:3;
  63.704 +		u64 i_w_num:4;
  63.705 +		u64 i_iosp:1;
  63.706 +		u64 i_rsvd:51;
  63.707 +	} ii_itte4_fld_s;
  63.708 +} ii_itte4_u_t;
  63.709 +
  63.710 +/************************************************************************
  63.711 + *									*
  63.712 + * Description:  There are seven instances of translation table entry   *
  63.713 + * registers. Each register maps a SHub Big Window to a 48-bit          *
  63.714 + * address on Crosstalk.                                                *
  63.715 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.716 + * number) are used to select one of these 7 registers. The Widget      *
  63.717 + * number field is then derived from the W_NUM field for synthesizing   *
  63.718 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.719 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.720 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.721 + * addressable by the Shub is thus the lower 16 GBytes per widget       *
  63.722 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.723 + * space can be accessed.                                               *
  63.724 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.725 + * Window number) are used to select one of these 7 registers. The      *
  63.726 + * Widget number field is then derived from the W_NUM field for         *
  63.727 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.728 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.729 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.730 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.731 + * Crosstalk space addressable by the Shub is thus the lower            *
  63.732 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.733 + * of this space can be accessed.                                       *
  63.734 + *									*
  63.735 + ************************************************************************/
  63.736 +
  63.737 +typedef union ii_itte5_u {
  63.738 +	u64 ii_itte5_regval;
  63.739 +	struct {
  63.740 +		u64 i_offset:5;
  63.741 +		u64 i_rsvd_1:3;
  63.742 +		u64 i_w_num:4;
  63.743 +		u64 i_iosp:1;
  63.744 +		u64 i_rsvd:51;
  63.745 +	} ii_itte5_fld_s;
  63.746 +} ii_itte5_u_t;
  63.747 +
  63.748 +/************************************************************************
  63.749 + *									*
  63.750 + * Description:  There are seven instances of translation table entry   *
  63.751 + * registers. Each register maps a Shub Big Window to a 48-bit          *
  63.752 + * address on Crosstalk.                                                *
  63.753 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.754 + * number) are used to select one of these 7 registers. The Widget      *
  63.755 + * number field is then derived from the W_NUM field for synthesizing   *
  63.756 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.757 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.758 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.759 + * addressable by the Shub is thus the lower 16 GBytes per widget       *
  63.760 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.761 + * space can be accessed.                                               *
  63.762 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.763 + * Window number) are used to select one of these 7 registers. The      *
  63.764 + * Widget number field is then derived from the W_NUM field for         *
  63.765 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.766 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.767 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.768 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.769 + * Crosstalk space addressable by the Shub is thus the lower            *
  63.770 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.771 + * of this space can be accessed.                                       *
  63.772 + *									*
  63.773 + ************************************************************************/
  63.774 +
  63.775 +typedef union ii_itte6_u {
  63.776 +	u64 ii_itte6_regval;
  63.777 +	struct {
  63.778 +		u64 i_offset:5;
  63.779 +		u64 i_rsvd_1:3;
  63.780 +		u64 i_w_num:4;
  63.781 +		u64 i_iosp:1;
  63.782 +		u64 i_rsvd:51;
  63.783 +	} ii_itte6_fld_s;
  63.784 +} ii_itte6_u_t;
  63.785 +
  63.786 +/************************************************************************
  63.787 + *									*
  63.788 + * Description:  There are seven instances of translation table entry   *
  63.789 + * registers. Each register maps a Shub Big Window to a 48-bit          *
  63.790 + * address on Crosstalk.                                                *
  63.791 + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
  63.792 + * number) are used to select one of these 7 registers. The Widget      *
  63.793 + * number field is then derived from the W_NUM field for synthesizing   *
  63.794 + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
  63.795 + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
  63.796 + * are padded with zeros. Although the maximum Crosstalk space          *
  63.797 + * addressable by the Shub is thus the lower 16 GBytes per widget       *
  63.798 + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
  63.799 + * space can be accessed.                                               *
  63.800 + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
  63.801 + * Window number) are used to select one of these 7 registers. The      *
  63.802 + * Widget number field is then derived from the W_NUM field for         *
  63.803 + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
  63.804 + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
  63.805 + * field is used as Crosstalk[47], and remainder of the Crosstalk       *
  63.806 + * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
  63.807 + * Crosstalk space addressable by the SHub is thus the lower            *
  63.808 + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
  63.809 + * of this space can be accessed.                                       *
  63.810 + *									*
  63.811 + ************************************************************************/
  63.812 +
  63.813 +typedef union ii_itte7_u {
  63.814 +	u64 ii_itte7_regval;
  63.815 +	struct {
  63.816 +		u64 i_offset:5;
  63.817 +		u64 i_rsvd_1:3;
  63.818 +		u64 i_w_num:4;
  63.819 +		u64 i_iosp:1;
  63.820 +		u64 i_rsvd:51;
  63.821 +	} ii_itte7_fld_s;
  63.822 +} ii_itte7_u_t;
  63.823 +
  63.824 +/************************************************************************
  63.825 + *									*
  63.826 + * Description:  There are 9 instances of this register, one per        *
  63.827 + * actual widget in this implementation of SHub and Crossbow.           *
  63.828 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  63.829 + * refers to Crossbow's internal space.                                 *
  63.830 + * This register contains the state elements per widget that are        *
  63.831 + * necessary to manage the PIO flow control on Crosstalk and on the     *
  63.832 + * Router Network. See the PIO Flow Control chapter for a complete      *
  63.833 + * description of this register                                         *
  63.834 + * The SPUR_WR bit requires some explanation. When this register is     *
  63.835 + * written, the new value of the C field is captured in an internal     *
  63.836 + * register so the hardware can remember what the programmer wrote      *
  63.837 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
  63.838 + * increments above this stored value, which indicates that there       *
  63.839 + * have been more responses received than requests sent. The SPUR_WR    *
  63.840 + * bit cannot be cleared until a value is written to the IPRBx          *
  63.841 + * register; the write will correct the C field and capture its new     *
  63.842 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  63.843 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  63.844 + * .    								*
  63.845 + *									*
  63.846 + ************************************************************************/
  63.847 +
  63.848 +typedef union ii_iprb0_u {
  63.849 +	u64 ii_iprb0_regval;
  63.850 +	struct {
  63.851 +		u64 i_c:8;
  63.852 +		u64 i_na:14;
  63.853 +		u64 i_rsvd_2:2;
  63.854 +		u64 i_nb:14;
  63.855 +		u64 i_rsvd_1:2;
  63.856 +		u64 i_m:2;
  63.857 +		u64 i_f:1;
  63.858 +		u64 i_of_cnt:5;
  63.859 +		u64 i_error:1;
  63.860 +		u64 i_rd_to:1;
  63.861 +		u64 i_spur_wr:1;
  63.862 +		u64 i_spur_rd:1;
  63.863 +		u64 i_rsvd:11;
  63.864 +		u64 i_mult_err:1;
  63.865 +	} ii_iprb0_fld_s;
  63.866 +} ii_iprb0_u_t;
  63.867 +
  63.868 +/************************************************************************
  63.869 + *									*
  63.870 + * Description:  There are 9 instances of this register, one per        *
  63.871 + * actual widget in this implementation of SHub and Crossbow.           *
  63.872 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  63.873 + * refers to Crossbow's internal space.                                 *
  63.874 + * This register contains the state elements per widget that are        *
  63.875 + * necessary to manage the PIO flow control on Crosstalk and on the     *
  63.876 + * Router Network. See the PIO Flow Control chapter for a complete      *
  63.877 + * description of this register                                         *
  63.878 + * The SPUR_WR bit requires some explanation. When this register is     *
  63.879 + * written, the new value of the C field is captured in an internal     *
  63.880 + * register so the hardware can remember what the programmer wrote      *
  63.881 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
  63.882 + * increments above this stored value, which indicates that there       *
  63.883 + * have been more responses received than requests sent. The SPUR_WR    *
  63.884 + * bit cannot be cleared until a value is written to the IPRBx          *
  63.885 + * register; the write will correct the C field and capture its new     *
  63.886 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  63.887 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  63.888 + * .    								*
  63.889 + *									*
  63.890 + ************************************************************************/
  63.891 +
  63.892 +typedef union ii_iprb8_u {
  63.893 +	u64 ii_iprb8_regval;
  63.894 +	struct {
  63.895 +		u64 i_c:8;
  63.896 +		u64 i_na:14;
  63.897 +		u64 i_rsvd_2:2;
  63.898 +		u64 i_nb:14;
  63.899 +		u64 i_rsvd_1:2;
  63.900 +		u64 i_m:2;
  63.901 +		u64 i_f:1;
  63.902 +		u64 i_of_cnt:5;
  63.903 +		u64 i_error:1;
  63.904 +		u64 i_rd_to:1;
  63.905 +		u64 i_spur_wr:1;
  63.906 +		u64 i_spur_rd:1;
  63.907 +		u64 i_rsvd:11;
  63.908 +		u64 i_mult_err:1;
  63.909 +	} ii_iprb8_fld_s;
  63.910 +} ii_iprb8_u_t;
  63.911 +
  63.912 +/************************************************************************
  63.913 + *									*
  63.914 + * Description:  There are 9 instances of this register, one per        *
  63.915 + * actual widget in this implementation of SHub and Crossbow.           *
  63.916 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  63.917 + * refers to Crossbow's internal space.                                 *
  63.918 + * This register contains the state elements per widget that are        *
  63.919 + * necessary to manage the PIO flow control on Crosstalk and on the     *
  63.920 + * Router Network. See the PIO Flow Control chapter for a complete      *
  63.921 + * description of this register                                         *
  63.922 + * The SPUR_WR bit requires some explanation. When this register is     *
  63.923 + * written, the new value of the C field is captured in an internal     *
  63.924 + * register so the hardware can remember what the programmer wrote      *
  63.925 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
  63.926 + * increments above this stored value, which indicates that there       *
  63.927 + * have been more responses received than requests sent. The SPUR_WR    *
  63.928 + * bit cannot be cleared until a value is written to the IPRBx          *
  63.929 + * register; the write will correct the C field and capture its new     *
  63.930 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  63.931 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  63.932 + * .    								*
  63.933 + *									*
  63.934 + ************************************************************************/
  63.935 +
  63.936 +typedef union ii_iprb9_u {
  63.937 +	u64 ii_iprb9_regval;
  63.938 +	struct {
  63.939 +		u64 i_c:8;
  63.940 +		u64 i_na:14;
  63.941 +		u64 i_rsvd_2:2;
  63.942 +		u64 i_nb:14;
  63.943 +		u64 i_rsvd_1:2;
  63.944 +		u64 i_m:2;
  63.945 +		u64 i_f:1;
  63.946 +		u64 i_of_cnt:5;
  63.947 +		u64 i_error:1;
  63.948 +		u64 i_rd_to:1;
  63.949 +		u64 i_spur_wr:1;
  63.950 +		u64 i_spur_rd:1;
  63.951 +		u64 i_rsvd:11;
  63.952 +		u64 i_mult_err:1;
  63.953 +	} ii_iprb9_fld_s;
  63.954 +} ii_iprb9_u_t;
  63.955 +
  63.956 +/************************************************************************
  63.957 + *									*
  63.958 + * Description:  There are 9 instances of this register, one per        *
  63.959 + * actual widget in this implementation of SHub and Crossbow.        *
  63.960 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
  63.961 + * refers to Crossbow's internal space.                                 *
  63.962 + * This register contains the state elements per widget that are        *
  63.963 + * necessary to manage the PIO flow control on Crosstalk and on the     *
  63.964 + * Router Network. See the PIO Flow Control chapter for a complete      *
  63.965 + * description of this register                                         *
  63.966 + * The SPUR_WR bit requires some explanation. When this register is     *
  63.967 + * written, the new value of the C field is captured in an internal     *
  63.968 + * register so the hardware can remember what the programmer wrote      *
  63.969 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
  63.970 + * increments above this stored value, which indicates that there       *
  63.971 + * have been more responses received than requests sent. The SPUR_WR    *
  63.972 + * bit cannot be cleared until a value is written to the IPRBx          *
  63.973 + * register; the write will correct the C field and capture its new     *
  63.974 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
  63.975 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
  63.976 + *									*
  63.977 + *									*
  63.978 + ************************************************************************/
  63.979 +
  63.980 +typedef union ii_iprba_u {
  63.981 +	u64 ii_iprba_regval;
  63.982 +	struct {
  63.983 +		u64 i_c:8;
  63.984 +		u64 i_na:14;
  63.985 +		u64 i_rsvd_2:2;
  63.986 +		u64 i_nb:14;
  63.987 +		u64 i_rsvd_1:2;
  63.988 +		u64 i_m:2;
  63.989 +		u64 i_f:1;
  63.990 +		u64 i_of_cnt:5;
  63.991 +		u64 i_error:1;
  63.992 +		u64 i_rd_to:1;
  63.993 +		u64 i_spur_wr:1;
  63.994 +		u64 i_spur_rd:1;
  63.995 +		u64 i_rsvd:11;
  63.996 +		u64 i_mult_err:1;
  63.997 +	} ii_iprba_fld_s;
  63.998 +} ii_iprba_u_t;
  63.999 +
 63.1000 +/************************************************************************
 63.1001 + *									*
 63.1002 + * Description:  There are 9 instances of this register, one per        *
 63.1003 + * actual widget in this implementation of SHub and Crossbow.           *
 63.1004 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 63.1005 + * refers to Crossbow's internal space.                                 *
 63.1006 + * This register contains the state elements per widget that are        *
 63.1007 + * necessary to manage the PIO flow control on Crosstalk and on the     *
 63.1008 + * Router Network. See the PIO Flow Control chapter for a complete      *
 63.1009 + * description of this register                                         *
 63.1010 + * The SPUR_WR bit requires some explanation. When this register is     *
 63.1011 + * written, the new value of the C field is captured in an internal     *
 63.1012 + * register so the hardware can remember what the programmer wrote      *
 63.1013 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 63.1014 + * increments above this stored value, which indicates that there       *
 63.1015 + * have been more responses received than requests sent. The SPUR_WR    *
 63.1016 + * bit cannot be cleared until a value is written to the IPRBx          *
 63.1017 + * register; the write will correct the C field and capture its new     *
 63.1018 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 63.1019 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 63.1020 + * .    								*
 63.1021 + *									*
 63.1022 + ************************************************************************/
 63.1023 +
 63.1024 +typedef union ii_iprbb_u {
 63.1025 +	u64 ii_iprbb_regval;
 63.1026 +	struct {
 63.1027 +		u64 i_c:8;
 63.1028 +		u64 i_na:14;
 63.1029 +		u64 i_rsvd_2:2;
 63.1030 +		u64 i_nb:14;
 63.1031 +		u64 i_rsvd_1:2;
 63.1032 +		u64 i_m:2;
 63.1033 +		u64 i_f:1;
 63.1034 +		u64 i_of_cnt:5;
 63.1035 +		u64 i_error:1;
 63.1036 +		u64 i_rd_to:1;
 63.1037 +		u64 i_spur_wr:1;
 63.1038 +		u64 i_spur_rd:1;
 63.1039 +		u64 i_rsvd:11;
 63.1040 +		u64 i_mult_err:1;
 63.1041 +	} ii_iprbb_fld_s;
 63.1042 +} ii_iprbb_u_t;
 63.1043 +
 63.1044 +/************************************************************************
 63.1045 + *									*
 63.1046 + * Description:  There are 9 instances of this register, one per        *
 63.1047 + * actual widget in this implementation of SHub and Crossbow.           *
 63.1048 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 63.1049 + * refers to Crossbow's internal space.                                 *
 63.1050 + * This register contains the state elements per widget that are        *
 63.1051 + * necessary to manage the PIO flow control on Crosstalk and on the     *
 63.1052 + * Router Network. See the PIO Flow Control chapter for a complete      *
 63.1053 + * description of this register                                         *
 63.1054 + * The SPUR_WR bit requires some explanation. When this register is     *
 63.1055 + * written, the new value of the C field is captured in an internal     *
 63.1056 + * register so the hardware can remember what the programmer wrote      *
 63.1057 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 63.1058 + * increments above this stored value, which indicates that there       *
 63.1059 + * have been more responses received than requests sent. The SPUR_WR    *
 63.1060 + * bit cannot be cleared until a value is written to the IPRBx          *
 63.1061 + * register; the write will correct the C field and capture its new     *
 63.1062 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 63.1063 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 63.1064 + * .    								*
 63.1065 + *									*
 63.1066 + ************************************************************************/
 63.1067 +
 63.1068 +typedef union ii_iprbc_u {
 63.1069 +	u64 ii_iprbc_regval;
 63.1070 +	struct {
 63.1071 +		u64 i_c:8;
 63.1072 +		u64 i_na:14;
 63.1073 +		u64 i_rsvd_2:2;
 63.1074 +		u64 i_nb:14;
 63.1075 +		u64 i_rsvd_1:2;
 63.1076 +		u64 i_m:2;
 63.1077 +		u64 i_f:1;
 63.1078 +		u64 i_of_cnt:5;
 63.1079 +		u64 i_error:1;
 63.1080 +		u64 i_rd_to:1;
 63.1081 +		u64 i_spur_wr:1;
 63.1082 +		u64 i_spur_rd:1;
 63.1083 +		u64 i_rsvd:11;
 63.1084 +		u64 i_mult_err:1;
 63.1085 +	} ii_iprbc_fld_s;
 63.1086 +} ii_iprbc_u_t;
 63.1087 +
 63.1088 +/************************************************************************
 63.1089 + *									*
 63.1090 + * Description:  There are 9 instances of this register, one per        *
 63.1091 + * actual widget in this implementation of SHub and Crossbow.           *
 63.1092 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 63.1093 + * refers to Crossbow's internal space.                                 *
 63.1094 + * This register contains the state elements per widget that are        *
 63.1095 + * necessary to manage the PIO flow control on Crosstalk and on the     *
 63.1096 + * Router Network. See the PIO Flow Control chapter for a complete      *
 63.1097 + * description of this register                                         *
 63.1098 + * The SPUR_WR bit requires some explanation. When this register is     *
 63.1099 + * written, the new value of the C field is captured in an internal     *
 63.1100 + * register so the hardware can remember what the programmer wrote      *
 63.1101 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 63.1102 + * increments above this stored value, which indicates that there       *
 63.1103 + * have been more responses received than requests sent. The SPUR_WR    *
 63.1104 + * bit cannot be cleared until a value is written to the IPRBx          *
 63.1105 + * register; the write will correct the C field and capture its new     *
 63.1106 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 63.1107 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 63.1108 + * .    								*
 63.1109 + *									*
 63.1110 + ************************************************************************/
 63.1111 +
 63.1112 +typedef union ii_iprbd_u {
 63.1113 +	u64 ii_iprbd_regval;
 63.1114 +	struct {
 63.1115 +		u64 i_c:8;
 63.1116 +		u64 i_na:14;
 63.1117 +		u64 i_rsvd_2:2;
 63.1118 +		u64 i_nb:14;
 63.1119 +		u64 i_rsvd_1:2;
 63.1120 +		u64 i_m:2;
 63.1121 +		u64 i_f:1;
 63.1122 +		u64 i_of_cnt:5;
 63.1123 +		u64 i_error:1;
 63.1124 +		u64 i_rd_to:1;
 63.1125 +		u64 i_spur_wr:1;
 63.1126 +		u64 i_spur_rd:1;
 63.1127 +		u64 i_rsvd:11;
 63.1128 +		u64 i_mult_err:1;
 63.1129 +	} ii_iprbd_fld_s;
 63.1130 +} ii_iprbd_u_t;
 63.1131 +
 63.1132 +/************************************************************************
 63.1133 + *									*
 63.1134 + * Description:  There are 9 instances of this register, one per        *
 63.1135 + * actual widget in this implementation of SHub and Crossbow.           *
 63.1136 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 63.1137 + * refers to Crossbow's internal space.                                 *
 63.1138 + * This register contains the state elements per widget that are        *
 63.1139 + * necessary to manage the PIO flow control on Crosstalk and on the     *
 63.1140 + * Router Network. See the PIO Flow Control chapter for a complete      *
 63.1141 + * description of this register                                         *
 63.1142 + * The SPUR_WR bit requires some explanation. When this register is     *
 63.1143 + * written, the new value of the C field is captured in an internal     *
 63.1144 + * register so the hardware can remember what the programmer wrote      *
 63.1145 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 63.1146 + * increments above this stored value, which indicates that there       *
 63.1147 + * have been more responses received than requests sent. The SPUR_WR    *
 63.1148 + * bit cannot be cleared until a value is written to the IPRBx          *
 63.1149 + * register; the write will correct the C field and capture its new     *
 63.1150 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 63.1151 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 63.1152 + * .    								*
 63.1153 + *									*
 63.1154 + ************************************************************************/
 63.1155 +
 63.1156 +typedef union ii_iprbe_u {
 63.1157 +	u64 ii_iprbe_regval;
 63.1158 +	struct {
 63.1159 +		u64 i_c:8;
 63.1160 +		u64 i_na:14;
 63.1161 +		u64 i_rsvd_2:2;
 63.1162 +		u64 i_nb:14;
 63.1163 +		u64 i_rsvd_1:2;
 63.1164 +		u64 i_m:2;
 63.1165 +		u64 i_f:1;
 63.1166 +		u64 i_of_cnt:5;
 63.1167 +		u64 i_error:1;
 63.1168 +		u64 i_rd_to:1;
 63.1169 +		u64 i_spur_wr:1;
 63.1170 +		u64 i_spur_rd:1;
 63.1171 +		u64 i_rsvd:11;
 63.1172 +		u64 i_mult_err:1;
 63.1173 +	} ii_iprbe_fld_s;
 63.1174 +} ii_iprbe_u_t;
 63.1175 +
 63.1176 +/************************************************************************
 63.1177 + *									*
 63.1178 + * Description:  There are 9 instances of this register, one per        *
 63.1179 + * actual widget in this implementation of Shub and Crossbow.           *
 63.1180 + * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 63.1181 + * refers to Crossbow's internal space.                                 *
 63.1182 + * This register contains the state elements per widget that are        *
 63.1183 + * necessary to manage the PIO flow control on Crosstalk and on the     *
 63.1184 + * Router Network. See the PIO Flow Control chapter for a complete      *
 63.1185 + * description of this register                                         *
 63.1186 + * The SPUR_WR bit requires some explanation. When this register is     *
 63.1187 + * written, the new value of the C field is captured in an internal     *
 63.1188 + * register so the hardware can remember what the programmer wrote      *
 63.1189 + * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 63.1190 + * increments above this stored value, which indicates that there       *
 63.1191 + * have been more responses received than requests sent. The SPUR_WR    *
 63.1192 + * bit cannot be cleared until a value is written to the IPRBx          *
 63.1193 + * register; the write will correct the C field and capture its new     *
 63.1194 + * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 63.1195 + * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 63.1196 + * .    								*
 63.1197 + *									*
 63.1198 + ************************************************************************/
 63.1199 +
 63.1200 +typedef union ii_iprbf_u {
 63.1201 +	u64 ii_iprbf_regval;
 63.1202 +	struct {
 63.1203 +		u64 i_c:8;
 63.1204 +		u64 i_na:14;
 63.1205 +		u64 i_rsvd_2:2;
 63.1206 +		u64 i_nb:14;
 63.1207 +		u64 i_rsvd_1:2;
 63.1208 +		u64 i_m:2;
 63.1209 +		u64 i_f:1;
 63.1210 +		u64 i_of_cnt:5;
 63.1211 +		u64 i_error:1;
 63.1212 +		u64 i_rd_to:1;
 63.1213 +		u64 i_spur_wr:1;
 63.1214 +		u64 i_spur_rd:1;
 63.1215 +		u64 i_rsvd:11;
 63.1216 +		u64 i_mult_err:1;
 63.1217 +	} ii_iprbe_fld_s;
 63.1218 +} ii_iprbf_u_t;
 63.1219 +
 63.1220 +/************************************************************************
 63.1221 + *									*
 63.1222 + *  This register specifies the timeout value to use for monitoring     *
 63.1223 + * Crosstalk credits which are used outbound to Crosstalk. An           *
 63.1224 + * internal counter called the Crosstalk Credit Timeout Counter         *
 63.1225 + * increments every 128 II clocks. The counter starts counting          *
 63.1226 + * anytime the credit count drops below a threshold, and resets to      *
 63.1227 + * zero (stops counting) anytime the credit count is at or above the    *
 63.1228 + * threshold. The threshold is 1 credit in direct connect mode and 2    *
 63.1229 + * in Crossbow connect mode. When the internal Crosstalk Credit         *
 63.1230 + * Timeout Counter reaches the value programmed in this register, a     *
 63.1231 + * Crosstalk Credit Timeout has occurred. The internal counter is not   *
 63.1232 + * readable from software, and stops counting at its maximum value,     *
 63.1233 + * so it cannot cause more than one interrupt.                          *
 63.1234 + *									*
 63.1235 + ************************************************************************/
 63.1236 +
 63.1237 +typedef union ii_ixcc_u {
 63.1238 +	u64 ii_ixcc_regval;
 63.1239 +	struct {
 63.1240 +		u64 i_time_out:26;
 63.1241 +		u64 i_rsvd:38;
 63.1242 +	} ii_ixcc_fld_s;
 63.1243 +} ii_ixcc_u_t;
 63.1244 +
 63.1245 +/************************************************************************
 63.1246 + *									*
 63.1247 + * Description:  This register qualifies all the PIO and DMA            *
 63.1248 + * operations launched from widget 0 towards the SHub. In               *
 63.1249 + * addition, it also qualifies accesses by the BTE streams.             *
 63.1250 + * The bits in each field of this register are cleared by the SHub      *
 63.1251 + * upon detection of an error which requires widget 0 or the BTE        *
 63.1252 + * streams to be terminated. Whether or not widget x has access         *
 63.1253 + * rights to this SHub is determined by an AND of the device            *
 63.1254 + * enable bit in the appropriate field of this register and bit 0 in    *
 63.1255 + * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
 63.1256 + * them. Incoming replies from Crosstalk are not subject to this        *
 63.1257 + * access control mechanism.                                            *
 63.1258 + *									*
 63.1259 + ************************************************************************/
 63.1260 +
 63.1261 +typedef union ii_imem_u {
 63.1262 +	u64 ii_imem_regval;
 63.1263 +	struct {
 63.1264 +		u64 i_w0_esd:1;
 63.1265 +		u64 i_rsvd_3:3;
 63.1266 +		u64 i_b0_esd:1;
 63.1267 +		u64 i_rsvd_2:3;
 63.1268 +		u64 i_b1_esd:1;
 63.1269 +		u64 i_rsvd_1:3;
 63.1270 +		u64 i_clr_precise:1;
 63.1271 +		u64 i_rsvd:51;
 63.1272 +	} ii_imem_fld_s;
 63.1273 +} ii_imem_u_t;
 63.1274 +
 63.1275 +/************************************************************************
 63.1276 + *									*
 63.1277 + * Description:  This register specifies the timeout value to use for   *
 63.1278 + * monitoring Crosstalk tail flits coming into the Shub in the          *
 63.1279 + * TAIL_TO field. An internal counter associated with this register     *
 63.1280 + * is incremented every 128 II internal clocks (7 bits). The counter    *
 63.1281 + * starts counting anytime a header micropacket is received and stops   *
 63.1282 + * counting (and resets to zero) any time a micropacket with a Tail     *
 63.1283 + * bit is received. Once the counter reaches the threshold value        *
 63.1284 + * programmed in this register, it generates an interrupt to the        *
 63.1285 + * processor that is programmed into the IIDSR. The counter saturates   *
 63.1286 + * (does not roll over) at its maximum value, so it cannot cause        *
 63.1287 + * another interrupt until after it is cleared.                         *
 63.1288 + * The register also contains the Read Response Timeout values. The     *
 63.1289 + * Prescalar is 23 bits, and counts II clocks. An internal counter      *
 63.1290 + * increments on every II clock and when it reaches the value in the    *
 63.1291 + * Prescalar field, all IPRTE registers with their valid bits set       *
 63.1292 + * have their Read Response timers bumped. Whenever any of them match   *
 63.1293 + * the value in the RRSP_TO field, a Read Response Timeout has          *
 63.1294 + * occurred, and error handling occurs as described in the Error        *
 63.1295 + * Handling section of this document.                                   *
 63.1296 + *									*
 63.1297 + ************************************************************************/
 63.1298 +
 63.1299 +typedef union ii_ixtt_u {
 63.1300 +	u64 ii_ixtt_regval;
 63.1301 +	struct {
 63.1302 +		u64 i_tail_to:26;
 63.1303 +		u64 i_rsvd_1:6;
 63.1304 +		u64 i_rrsp_ps:23;
 63.1305 +		u64 i_rrsp_to:5;
 63.1306 +		u64 i_rsvd:4;
 63.1307 +	} ii_ixtt_fld_s;
 63.1308 +} ii_ixtt_u_t;
 63.1309 +
 63.1310 +/************************************************************************
 63.1311 + *									*
 63.1312 + *  Writing a 1 to the fields of this register clears the appropriate   *
 63.1313 + * error bits in other areas of SHub. Note that when the                *
 63.1314 + * E_PRB_x bits are used to clear error bits in PRB registers,          *
 63.1315 + * SPUR_RD and SPUR_WR may persist, because they require additional     *
 63.1316 + * action to clear them. See the IPRBx and IXSS Register                *
 63.1317 + * specifications.                                                      *
 63.1318 + *									*
 63.1319 + ************************************************************************/
 63.1320 +
 63.1321 +typedef union ii_ieclr_u {
 63.1322 +	u64 ii_ieclr_regval;
 63.1323 +