ia64/xen-unstable

changeset 16317:ddc9e6b2babb

cpufreq, amd: Xen support for architectural AMD pstate driver

With the third generation Opteron parts, AMD switched to an
architecturally defined interface for PowerNow! that uses
different MSRs than previous versions.

Add support in msr-index.h and traps.c for the new interface.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
author Keir Fraser <keir@xensource.com>
date Mon Nov 05 10:45:07 2007 +0000 (2007-11-05)
parents 28487ba2ea1e
children a609b4fc411d
files xen/arch/x86/traps.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/traps.c	Mon Nov 05 10:16:30 2007 +0000
     1.2 +++ b/xen/arch/x86/traps.c	Mon Nov 05 10:45:07 2007 +0000
     1.3 @@ -1845,6 +1845,17 @@ static int emulate_privileged_op(struct 
     1.4  #endif
     1.5          case MSR_K7_FID_VID_STATUS:
     1.6          case MSR_K7_FID_VID_CTL:
     1.7 +        case MSR_K8_PSTATE_LIMIT:
     1.8 +        case MSR_K8_PSTATE_CTRL:
     1.9 +        case MSR_K8_PSTATE_STATUS:
    1.10 +        case MSR_K8_PSTATE0:
    1.11 +        case MSR_K8_PSTATE1:
    1.12 +        case MSR_K8_PSTATE2:
    1.13 +        case MSR_K8_PSTATE3:
    1.14 +        case MSR_K8_PSTATE4:
    1.15 +        case MSR_K8_PSTATE5:
    1.16 +        case MSR_K8_PSTATE6:
    1.17 +        case MSR_K8_PSTATE7:
    1.18              if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
    1.19                   (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ||
    1.20                   wrmsr_safe(regs->ecx, eax, edx) )
    1.21 @@ -1897,6 +1908,17 @@ static int emulate_privileged_op(struct 
    1.22  #endif
    1.23          case MSR_K7_FID_VID_CTL:
    1.24          case MSR_K7_FID_VID_STATUS:
    1.25 +        case MSR_K8_PSTATE_LIMIT:
    1.26 +        case MSR_K8_PSTATE_CTRL:
    1.27 +        case MSR_K8_PSTATE_STATUS:
    1.28 +        case MSR_K8_PSTATE0:
    1.29 +        case MSR_K8_PSTATE1:
    1.30 +        case MSR_K8_PSTATE2:
    1.31 +        case MSR_K8_PSTATE3:
    1.32 +        case MSR_K8_PSTATE4:
    1.33 +        case MSR_K8_PSTATE5:
    1.34 +        case MSR_K8_PSTATE6:
    1.35 +        case MSR_K8_PSTATE7:
    1.36              if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
    1.37                   (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ||
    1.38                   rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
     2.1 --- a/xen/include/asm-x86/msr-index.h	Mon Nov 05 10:16:30 2007 +0000
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Mon Nov 05 10:45:07 2007 +0000
     2.3 @@ -165,6 +165,17 @@
     2.4  #define MSR_K8_HWCR			0xc0010015
     2.5  #define MSR_K7_FID_VID_CTL		0xc0010041
     2.6  #define MSR_K7_FID_VID_STATUS		0xc0010042
     2.7 +#define MSR_K8_PSTATE_LIMIT		0xc0010061
     2.8 +#define MSR_K8_PSTATE_CTRL		0xc0010062
     2.9 +#define MSR_K8_PSTATE_STATUS		0xc0010063
    2.10 +#define MSR_K8_PSTATE0			0xc0010064
    2.11 +#define MSR_K8_PSTATE1			0xc0010065
    2.12 +#define MSR_K8_PSTATE2			0xc0010066
    2.13 +#define MSR_K8_PSTATE3			0xc0010067
    2.14 +#define MSR_K8_PSTATE4			0xc0010068
    2.15 +#define MSR_K8_PSTATE5			0xc0010069
    2.16 +#define MSR_K8_PSTATE6			0xc001006A
    2.17 +#define MSR_K8_PSTATE7			0xc001006B
    2.18  #define MSR_K8_ENABLE_C1E		0xc0010055
    2.19  #define MSR_K8_VM_CR			0xc0010114
    2.20  #define MSR_K8_VM_HSAVE_PA		0xc0010117