ia64/xen-unstable

changeset 130:dc2f8bc0b538

bitkeeper revision 1.22.2.7 (3e4540ce236_3mBFvJr9jn3-rPO3sA)

Support (untested) for Intel E1000 driver. This required adding a
bunch of new linux headers, and a fair bit of tidying. It correctly
detects the card, but I haven't sent/received any packets.
author iap10@labyrinth.cl.cam.ac.uk
date Sat Feb 08 17:39:26 2003 +0000 (2003-02-08)
parents 314a968df74d
children 643a74d7c497 c710f555d13a
files .rootkeys xen-2.4.16/arch/i386/process.c xen-2.4.16/drivers/net/Makefile xen-2.4.16/drivers/net/e1000/LICENSE xen-2.4.16/drivers/net/e1000/Makefile xen-2.4.16/drivers/net/e1000/e1000.h xen-2.4.16/drivers/net/e1000/e1000_ethtool.c xen-2.4.16/drivers/net/e1000/e1000_hw.c xen-2.4.16/drivers/net/e1000/e1000_hw.h xen-2.4.16/drivers/net/e1000/e1000_main.c xen-2.4.16/drivers/net/e1000/e1000_osdep.h xen-2.4.16/drivers/net/e1000/e1000_param.c xen-2.4.16/drivers/pci/pci.c xen-2.4.16/include/asm-i386/irq.h xen-2.4.16/include/asm-i386/uaccess.h xen-2.4.16/include/xeno/ethtool.h xen-2.4.16/include/xeno/if_vlan.h xen-2.4.16/include/xeno/kernel.h xen-2.4.16/include/xeno/netdevice.h xen-2.4.16/include/xeno/notifier.h xen-2.4.16/include/xeno/pci.h xen-2.4.16/include/xeno/reboot.h xen-2.4.16/include/xeno/types.h
line diff
     1.1 --- a/.rootkeys	Sat Feb 08 17:32:45 2003 +0000
     1.2 +++ b/.rootkeys	Sat Feb 08 17:39:26 2003 +0000
     1.3 @@ -73,6 +73,15 @@ 3ddb79bfl_DWxZQFKiJ2BXrSedV4lg xen-2.4.1
     1.4  3ddb79bfLVGtyXNJS4NQg-lP21rndA xen-2.4.16/drivers/net/8139too.c
     1.5  3ddb79c0tWiE8xIFHszxipeVCGKTSA xen-2.4.16/drivers/net/Makefile
     1.6  3ddb79bfU-H1Hms4BuJEPPydjXUEaQ xen-2.4.16/drivers/net/Space.c
     1.7 +3e4540ccS4bfbx9rLiLElP0F1OVwZA xen-2.4.16/drivers/net/e1000/LICENSE
     1.8 +3e4540ccXG6af_6-u0IiKKvtdGHJyA xen-2.4.16/drivers/net/e1000/Makefile
     1.9 +3e4540ccoY2eo4VIkbR4sCOj0bVzSA xen-2.4.16/drivers/net/e1000/e1000.h
    1.10 +3e4540ccvUz0j2ejQ9Z9djEGc93wRA xen-2.4.16/drivers/net/e1000/e1000_ethtool.c
    1.11 +3e4540ccjqsc94nU3C4w3ZJaxFZFjA xen-2.4.16/drivers/net/e1000/e1000_hw.c
    1.12 +3e4540cczrrQVyyj-s1-viyX1kMUlA xen-2.4.16/drivers/net/e1000/e1000_hw.h
    1.13 +3e4540ccvQ9Dtoh9tV-L3ULUwN9X7g xen-2.4.16/drivers/net/e1000/e1000_main.c
    1.14 +3e4540cc3t7_y-YLeyMG2pX9xtdXPA xen-2.4.16/drivers/net/e1000/e1000_osdep.h
    1.15 +3e4540cct_8Ig-Y1W_vM2gS_u7mC0A xen-2.4.16/drivers/net/e1000/e1000_param.c
    1.16  3ddb79c0GejJrp1U6W4G6dYi-RiH4A xen-2.4.16/drivers/net/eepro100.c
    1.17  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen-2.4.16/drivers/net/net_init.c
    1.18  3ddb79c0fQgORkFlqWZdP-6cDHyFIQ xen-2.4.16/drivers/net/pcnet32.c
    1.19 @@ -199,6 +208,7 @@ 3ddb79c0MM575N4YvMSiw9EqKH4JDA xen-2.4.1
    1.20  3ddb79c1yHLp08JhgPxIMcZ8DwN9hg xen-2.4.16/include/xeno/if.h
    1.21  3ddb79c1RCWOkWPQRzbYVTX_e-E7CA xen-2.4.16/include/xeno/if_ether.h
    1.22  3ddb79c2IYah7z7hkzPyOiG8szKkyw xen-2.4.16/include/xeno/if_packet.h
    1.23 +3e4540ccefnCkeqtD_dW_CBOjXUSYw xen-2.4.16/include/xeno/if_vlan.h
    1.24  3df0af1c-QrOEqpPHq4uL3NZzCeJCg xen-2.4.16/include/xeno/in.h
    1.25  3ddb79c0GurNF9tDWqQbAwJFH8ugfA xen-2.4.16/include/xeno/init.h
    1.26  3ddb79c1Vi5VleJAOKHAlY0G2zAsgw xen-2.4.16/include/xeno/interrupt.h
    1.27 @@ -207,6 +217,7 @@ 3ddb79c1nzaWu8NoF4xCCMSFJR4MlA xen-2.4.1
    1.28  3ddb79c2qAxCOABlkKtD8Txohe-qEw xen-2.4.16/include/xeno/irq.h
    1.29  3ddb79c2b3qe-6Ann09FqZBF4IrJaQ xen-2.4.16/include/xeno/irq_cpustat.h
    1.30  3ddb79c11w_O7z7YZJnzuDSxaK5LlA xen-2.4.16/include/xeno/kdev_t.h
    1.31 +3e4540ccPHqIIv2pvnQ1gV8LUnoHIg xen-2.4.16/include/xeno/kernel.h
    1.32  3ddb79c1NfYlOrWNqgZkj9EwtFfJow xen-2.4.16/include/xeno/lib.h
    1.33  3ddb79c18Ajy7micDGQQfJ0zWgEHtA xen-2.4.16/include/xeno/list.h
    1.34  3ddb79c0_s2_wgV0cA6tztEaeyy1NA xen-2.4.16/include/xeno/major.h
    1.35 @@ -215,10 +226,12 @@ 3ddb79c1gs2VbLbQlw0dcDUXYIepDA xen-2.4.1
    1.36  3ddb79c13p9iHn1XAp0IS1qvj4yDsg xen-2.4.16/include/xeno/module.h
    1.37  3ddb79c1ieLZfGSFwfvvSQ2NK1BMSg xen-2.4.16/include/xeno/multiboot.h
    1.38  3ddb79c0CLfAlJLg1ohdPD-Jjn-jxg xen-2.4.16/include/xeno/netdevice.h
    1.39 +3e4540ccaugeWGdOuphJKj6WFw1jkw xen-2.4.16/include/xeno/notifier.h
    1.40  3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen-2.4.16/include/xeno/pci.h
    1.41  3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen-2.4.16/include/xeno/pci_ids.h
    1.42  3ddb79c2byJwwNNkiES__A9H4Cvc4g xen-2.4.16/include/xeno/pkt_sched.h
    1.43  3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen-2.4.16/include/xeno/prefetch.h
    1.44 +3e4540ccU1sgCx8seIMGlahmMfv7yQ xen-2.4.16/include/xeno/reboot.h
    1.45  3ddb79c0LzqqS0LhAQ50ekgj4oGl7Q xen-2.4.16/include/xeno/sched.h
    1.46  3ddb79c0VDeD-Oft5eNfMneTU3D1dQ xen-2.4.16/include/xeno/skbuff.h
    1.47  3ddb79c14dXIhP7C2ahnoD08K90G_w xen-2.4.16/include/xeno/slab.h
     2.1 --- a/xen-2.4.16/arch/i386/process.c	Sat Feb 08 17:32:45 2003 +0000
     2.2 +++ b/xen-2.4.16/arch/i386/process.c	Sat Feb 08 17:39:26 2003 +0000
     2.3 @@ -12,8 +12,6 @@
     2.4   */
     2.5  
     2.6  #define __KERNEL_SYSCALLS__
     2.7 -#include <stdarg.h>
     2.8 -
     2.9  #include <xeno/config.h>
    2.10  #include <xeno/lib.h>
    2.11  #include <xeno/errno.h>
     3.1 --- a/xen-2.4.16/drivers/net/Makefile	Sat Feb 08 17:32:45 2003 +0000
     3.2 +++ b/xen-2.4.16/drivers/net/Makefile	Sat Feb 08 17:39:26 2003 +0000
     3.3 @@ -3,8 +3,10 @@ include $(BASEDIR)/Rules.mk
     3.4  
     3.5  default: $(OBJS)
     3.6  	$(MAKE) -C tulip
     3.7 -	$(LD) -r -o driver.o $(OBJS) tulip/tulip.o 
     3.8 +	$(MAKE) -C e1000
     3.9 +	$(LD) -r -o driver.o $(OBJS) tulip/tulip.o e1000/e1000.o
    3.10  
    3.11  clean:
    3.12  	$(MAKE) -C tulip clean
    3.13 +	$(MAKE) -C e1000 clean
    3.14  	rm -f *.o *~ core
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen-2.4.16/drivers/net/e1000/LICENSE	Sat Feb 08 17:39:26 2003 +0000
     4.3 @@ -0,0 +1,339 @@
     4.4 +
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   4.267 +    EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
   4.268 +    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 
   4.269 +    ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH 
   4.270 +    YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 
   4.271 +    NECESSARY SERVICING, REPAIR OR CORRECTION. 
   4.272 +
   4.273 +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 
   4.274 +    WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 
   4.275 +    REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 
   4.276 +    DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 
   4.277 +    DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM 
   4.278 +    (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 
   4.279 +    INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF 
   4.280 +    THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR 
   4.281 +    OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
   4.282 +
   4.283 +END OF TERMS AND CONDITIONS
   4.284 +
   4.285 +How to Apply These Terms to Your New Programs
   4.286 +
   4.287 +If you develop a new program, and you want it to be of the greatest 
   4.288 +possible use to the public, the best way to achieve this is to make it free 
   4.289 +software which everyone can redistribute and change under these terms. 
   4.290 +
   4.291 +To do so, attach the following notices to the program. It is safest to 
   4.292 +attach them to the start of each source file to most effectively convey the
   4.293 +exclusion of warranty; and each file should have at least the "copyright" 
   4.294 +line and a pointer to where the full notice is found. 
   4.295 +
   4.296 +one line to give the program's name and an idea of what it does.
   4.297 +Copyright (C) yyyy  name of author
   4.298 +
   4.299 +This program is free software; you can redistribute it and/or modify it 
   4.300 +under the terms of the GNU General Public License as published by the Free 
   4.301 +Software Foundation; either version 2 of the License, or (at your option) 
   4.302 +any later version.
   4.303 +
   4.304 +This program is distributed in the hope that it will be useful, but WITHOUT 
   4.305 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   4.306 +FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   4.307 +more details.
   4.308 +
   4.309 +You should have received a copy of the GNU General Public License along with
   4.310 +this program; if not, write to the Free Software Foundation, Inc., 59 
   4.311 +Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   4.312 +
   4.313 +Also add information on how to contact you by electronic and paper mail. 
   4.314 +
   4.315 +If the program is interactive, make it output a short notice like this when 
   4.316 +it starts in an interactive mode: 
   4.317 +
   4.318 +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes 
   4.319 +with ABSOLUTELY NO WARRANTY; for details type 'show w'.  This is free 
   4.320 +software, and you are welcome to redistribute it under certain conditions; 
   4.321 +type 'show c' for details.
   4.322 +
   4.323 +The hypothetical commands 'show w' and 'show c' should show the appropriate 
   4.324 +parts of the General Public License. Of course, the commands you use may be 
   4.325 +called something other than 'show w' and 'show c'; they could even be 
   4.326 +mouse-clicks or menu items--whatever suits your program. 
   4.327 +
   4.328 +You should also get your employer (if you work as a programmer) or your 
   4.329 +school, if any, to sign a "copyright disclaimer" for the program, if 
   4.330 +necessary. Here is a sample; alter the names: 
   4.331 +
   4.332 +Yoyodyne, Inc., hereby disclaims all copyright interest in the program 
   4.333 +'Gnomovision' (which makes passes at compilers) written by James Hacker.
   4.334 +
   4.335 +signature of Ty Coon, 1 April 1989
   4.336 +Ty Coon, President of Vice
   4.337 +
   4.338 +This General Public License does not permit incorporating your program into 
   4.339 +proprietary programs. If your program is a subroutine library, you may 
   4.340 +consider it more useful to permit linking proprietary applications with the 
   4.341 +library. If this is what you want to do, use the GNU Library General Public 
   4.342 +License instead of this License.
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen-2.4.16/drivers/net/e1000/Makefile	Sat Feb 08 17:39:26 2003 +0000
     5.3 @@ -0,0 +1,39 @@
     5.4 +################################################################################
     5.5 +#
     5.6 +# 
     5.7 +# Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     5.8 +# 
     5.9 +# This program is free software; you can redistribute it and/or modify it 
    5.10 +# under the terms of the GNU General Public License as published by the Free 
    5.11 +# Software Foundation; either version 2 of the License, or (at your option) 
    5.12 +# any later version.
    5.13 +# 
    5.14 +# This program is distributed in the hope that it will be useful, but WITHOUT 
    5.15 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    5.16 +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    5.17 +# more details.
    5.18 +# 
    5.19 +# You should have received a copy of the GNU General Public License along with
    5.20 +# this program; if not, write to the Free Software Foundation, Inc., 59 
    5.21 +# Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    5.22 +# 
    5.23 +# The full GNU General Public License is included in this distribution in the
    5.24 +# file called LICENSE.
    5.25 +# 
    5.26 +# Contact Information:
    5.27 +# Linux NICS <linux.nics@intel.com>
    5.28 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    5.29 +#
    5.30 +################################################################################
    5.31 +
    5.32 +#
    5.33 +# Makefile for the Intel(R) PRO/1000 ethernet driver
    5.34 +#
    5.35 +
    5.36 +include $(BASEDIR)/Rules.mk
    5.37 +
    5.38 +default: $(OBJS)
    5.39 +	$(LD) -r -o e1000.o $(OBJS)
    5.40 +
    5.41 +clean:
    5.42 +	rm -f *.o *~ core
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000.h	Sat Feb 08 17:39:26 2003 +0000
     6.3 @@ -0,0 +1,209 @@
     6.4 +/*******************************************************************************
     6.5 +
     6.6 +  
     6.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     6.8 +  
     6.9 +  This program is free software; you can redistribute it and/or modify it 
    6.10 +  under the terms of the GNU General Public License as published by the Free 
    6.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    6.12 +  any later version.
    6.13 +  
    6.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    6.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    6.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    6.17 +  more details.
    6.18 +  
    6.19 +  You should have received a copy of the GNU General Public License along with
    6.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    6.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    6.22 +  
    6.23 +  The full GNU General Public License is included in this distribution in the
    6.24 +  file called LICENSE.
    6.25 +  
    6.26 +  Contact Information:
    6.27 +  Linux NICS <linux.nics@intel.com>
    6.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    6.29 +
    6.30 +*******************************************************************************/
    6.31 +
    6.32 +
    6.33 +/* Linux PRO/1000 Ethernet Driver main header file */
    6.34 +
    6.35 +#ifndef _E1000_H_
    6.36 +#define _E1000_H_
    6.37 +
    6.38 +//#include <linux/stddef.h>
    6.39 +#include <linux/config.h>
    6.40 +#include <linux/module.h>
    6.41 +#include <linux/types.h>
    6.42 +#include <asm/byteorder.h>
    6.43 +#include <linux/init.h>
    6.44 +#include <linux/mm.h>
    6.45 +#include <linux/errno.h>
    6.46 +#include <linux/ioport.h>
    6.47 +#include <linux/pci.h>
    6.48 +#include <linux/kernel.h>
    6.49 +#include <linux/netdevice.h>
    6.50 +#include <linux/etherdevice.h>
    6.51 +#include <linux/skbuff.h>
    6.52 +#include <linux/delay.h>
    6.53 +#include <linux/timer.h>
    6.54 +#include <linux/slab.h>
    6.55 +#include <linux/interrupt.h>
    6.56 +//#include <linux/string.h>
    6.57 +//#include <linux/pagemap.h>
    6.58 +#include <asm/bitops.h>
    6.59 +#include <asm/io.h>
    6.60 +#include <asm/irq.h>
    6.61 +//#include <linux/capability.h>
    6.62 +#include <linux/in.h>
    6.63 +//#include <linux/ip.h>
    6.64 +//#include <linux/tcp.h>
    6.65 +//#include <linux/udp.h>
    6.66 +//#include <net/pkt_sched.h>
    6.67 +#include <linux/list.h>
    6.68 +#include <linux/reboot.h>
    6.69 +#include <linux/tqueue.h>
    6.70 +#include <linux/ethtool.h>
    6.71 +#include <linux/if_vlan.h>
    6.72 +
    6.73 +#define BAR_0		0
    6.74 +#define BAR_1		1
    6.75 +#define BAR_5		5
    6.76 +#define PCI_DMA_64BIT	0xffffffffffffffffULL
    6.77 +#define PCI_DMA_32BIT	0x00000000ffffffffULL
    6.78 +
    6.79 +
    6.80 +struct e1000_adapter;
    6.81 +
    6.82 +// XEN XXX
    6.83 +#define DBG 1
    6.84 +
    6.85 +#include "e1000_hw.h"
    6.86 +
    6.87 +#if DBG
    6.88 +#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args)
    6.89 +#else
    6.90 +XXX
    6.91 +#define E1000_DBG(args...)
    6.92 +#endif
    6.93 +
    6.94 +#define E1000_ERR(args...) printk(KERN_ERR "e1000: " args)
    6.95 +
    6.96 +#define E1000_MAX_INTR 10
    6.97 +
    6.98 +/* Supported Rx Buffer Sizes */
    6.99 +#define E1000_RXBUFFER_2048  2048
   6.100 +#define E1000_RXBUFFER_4096  4096
   6.101 +#define E1000_RXBUFFER_8192  8192
   6.102 +#define E1000_RXBUFFER_16384 16384
   6.103 +
   6.104 +/* Flow Control High-Watermark: 43464 bytes */
   6.105 +#define E1000_FC_HIGH_THRESH 0xA9C8
   6.106 +
   6.107 +/* Flow Control Low-Watermark: 43456 bytes */
   6.108 +#define E1000_FC_LOW_THRESH 0xA9C0
   6.109 +
   6.110 +/* Flow Control Pause Time: 858 usec */
   6.111 +#define E1000_FC_PAUSE_TIME 0x0680
   6.112 +
   6.113 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
   6.114 +#define E1000_TX_QUEUE_WAKE	16
   6.115 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
   6.116 +#define E1000_RX_BUFFER_WRITE	16
   6.117 +
   6.118 +#define E1000_JUMBO_PBA      0x00000028
   6.119 +#define E1000_DEFAULT_PBA    0x00000030
   6.120 +
   6.121 +#define AUTO_ALL_MODES       0
   6.122 +#define E1000_EEPROM_APME    4
   6.123 +
   6.124 +/* only works for sizes that are powers of 2 */
   6.125 +#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
   6.126 +
   6.127 +/* wrapper around a pointer to a socket buffer,
   6.128 + * so a DMA handle can be stored along with the buffer */
   6.129 +struct e1000_buffer {
   6.130 +	struct sk_buff *skb;
   6.131 +	uint64_t dma;
   6.132 +	unsigned long length;
   6.133 +	unsigned long time_stamp;
   6.134 +};
   6.135 +
   6.136 +struct e1000_desc_ring {
   6.137 +	/* pointer to the descriptor ring memory */
   6.138 +	void *desc;
   6.139 +	/* physical address of the descriptor ring */
   6.140 +	dma_addr_t dma;
   6.141 +	/* length of descriptor ring in bytes */
   6.142 +	unsigned int size;
   6.143 +	/* number of descriptors in the ring */
   6.144 +	unsigned int count;
   6.145 +	/* next descriptor to associate a buffer with */
   6.146 +	unsigned int next_to_use;
   6.147 +	/* next descriptor to check for DD status bit */
   6.148 +	unsigned int next_to_clean;
   6.149 +	/* array of buffer information structs */
   6.150 +	struct e1000_buffer *buffer_info;
   6.151 +};
   6.152 +
   6.153 +#define E1000_DESC_UNUSED(R) \
   6.154 +((((R)->next_to_clean + (R)->count) - ((R)->next_to_use + 1)) % ((R)->count))
   6.155 +
   6.156 +#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
   6.157 +#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
   6.158 +#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
   6.159 +#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
   6.160 +
   6.161 +/* board specific private data structure */
   6.162 +
   6.163 +struct e1000_adapter {
   6.164 +	struct timer_list watchdog_timer;
   6.165 +	struct timer_list phy_info_timer;
   6.166 +	struct vlan_group *vlgrp;
   6.167 +	char *id_string;
   6.168 +	uint32_t bd_number;
   6.169 +	uint32_t rx_buffer_len;
   6.170 +	uint32_t part_num;
   6.171 +	uint32_t wol;
   6.172 +	uint16_t link_speed;
   6.173 +	uint16_t link_duplex;
   6.174 +	spinlock_t stats_lock;
   6.175 +	atomic_t irq_sem;
   6.176 +	struct tq_struct tx_timeout_task;
   6.177 +
   6.178 +	struct timer_list blink_timer;
   6.179 +	unsigned long led_status;
   6.180 +
   6.181 +	/* TX */
   6.182 +	struct e1000_desc_ring tx_ring;
   6.183 +	uint32_t txd_cmd;
   6.184 +	uint32_t tx_int_delay;
   6.185 +	uint32_t tx_abs_int_delay;
   6.186 +	int max_data_per_txd;
   6.187 +
   6.188 +	/* RX */
   6.189 +	struct e1000_desc_ring rx_ring;
   6.190 +	uint64_t hw_csum_err;
   6.191 +	uint64_t hw_csum_good;
   6.192 +	uint32_t rx_int_delay;
   6.193 +	uint32_t rx_abs_int_delay;
   6.194 +	boolean_t rx_csum;
   6.195 +
   6.196 +	/* OS defined structs */
   6.197 +	struct net_device *netdev;
   6.198 +	struct pci_dev *pdev;
   6.199 +	struct net_device_stats net_stats;
   6.200 +
   6.201 +	/* structs defined in e1000_hw.h */
   6.202 +	struct e1000_hw hw;
   6.203 +	struct e1000_hw_stats stats;
   6.204 +	struct e1000_phy_info phy_info;
   6.205 +	struct e1000_phy_stats phy_stats;
   6.206 +
   6.207 +
   6.208 +
   6.209 +	uint32_t pci_state[16];
   6.210 +	char ifname[IFNAMSIZ];
   6.211 +};
   6.212 +#endif /* _E1000_H_ */
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_ethtool.c	Sat Feb 08 17:39:26 2003 +0000
     7.3 @@ -0,0 +1,611 @@
     7.4 +/*******************************************************************************
     7.5 +
     7.6 +  
     7.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     7.8 +  
     7.9 +  This program is free software; you can redistribute it and/or modify it 
    7.10 +  under the terms of the GNU General Public License as published by the Free 
    7.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    7.12 +  any later version.
    7.13 +  
    7.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    7.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    7.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    7.17 +  more details.
    7.18 +  
    7.19 +  You should have received a copy of the GNU General Public License along with
    7.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    7.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    7.22 +  
    7.23 +  The full GNU General Public License is included in this distribution in the
    7.24 +  file called LICENSE.
    7.25 +  
    7.26 +  Contact Information:
    7.27 +  Linux NICS <linux.nics@intel.com>
    7.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    7.29 +
    7.30 +*******************************************************************************/
    7.31 +
    7.32 +/* ethtool support for e1000 */
    7.33 +
    7.34 +#include "e1000.h"
    7.35 +
    7.36 +#include <asm/uaccess.h>
    7.37 +
    7.38 +extern char e1000_driver_name[];
    7.39 +extern char e1000_driver_version[];
    7.40 +
    7.41 +extern int e1000_up(struct e1000_adapter *adapter);
    7.42 +extern void e1000_down(struct e1000_adapter *adapter);
    7.43 +extern void e1000_reset(struct e1000_adapter *adapter);
    7.44 +
    7.45 +static char e1000_gstrings_stats[][ETH_GSTRING_LEN] = {
    7.46 +	"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
    7.47 +	"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
    7.48 +	"rx_length_errors", "rx_over_errors", "rx_crc_errors",
    7.49 +	"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
    7.50 +	"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
    7.51 +	"tx_heartbeat_errors", "tx_window_errors",
    7.52 +};
    7.53 +#define E1000_STATS_LEN	sizeof(e1000_gstrings_stats) / ETH_GSTRING_LEN
    7.54 +
    7.55 +static void
    7.56 +e1000_ethtool_gset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
    7.57 +{
    7.58 +	struct e1000_hw *hw = &adapter->hw;
    7.59 +
    7.60 +	if(hw->media_type == e1000_media_type_copper) {
    7.61 +
    7.62 +		ecmd->supported = (SUPPORTED_10baseT_Half |
    7.63 +		                   SUPPORTED_10baseT_Full |
    7.64 +		                   SUPPORTED_100baseT_Half |
    7.65 +		                   SUPPORTED_100baseT_Full |
    7.66 +		                   SUPPORTED_1000baseT_Full|
    7.67 +		                   SUPPORTED_Autoneg |
    7.68 +		                   SUPPORTED_TP);
    7.69 +
    7.70 +		ecmd->advertising = ADVERTISED_TP;
    7.71 +
    7.72 +		if(hw->autoneg == 1) {
    7.73 +			ecmd->advertising |= ADVERTISED_Autoneg;
    7.74 +
    7.75 +			/* the e1000 autoneg seems to match ethtool nicely */
    7.76 +
    7.77 +			ecmd->advertising |= hw->autoneg_advertised;
    7.78 +		}
    7.79 +
    7.80 +		ecmd->port = PORT_TP;
    7.81 +		ecmd->phy_address = hw->phy_addr;
    7.82 +
    7.83 +		if(hw->mac_type == e1000_82543)
    7.84 +			ecmd->transceiver = XCVR_EXTERNAL;
    7.85 +		else
    7.86 +			ecmd->transceiver = XCVR_INTERNAL;
    7.87 +
    7.88 +	} else {
    7.89 +		ecmd->supported   = (SUPPORTED_1000baseT_Full |
    7.90 +				     SUPPORTED_FIBRE |
    7.91 +				     SUPPORTED_Autoneg);
    7.92 +
    7.93 +		ecmd->advertising = (SUPPORTED_1000baseT_Full |
    7.94 +				     SUPPORTED_FIBRE |
    7.95 +				     SUPPORTED_Autoneg);
    7.96 +
    7.97 +		ecmd->port = PORT_FIBRE;
    7.98 +
    7.99 +		if(hw->mac_type >= e1000_82545)
   7.100 +			ecmd->transceiver = XCVR_INTERNAL;
   7.101 +		else
   7.102 +			ecmd->transceiver = XCVR_EXTERNAL;
   7.103 +	}
   7.104 +
   7.105 +	if(netif_carrier_ok(adapter->netdev)) {
   7.106 +
   7.107 +		e1000_get_speed_and_duplex(hw, &adapter->link_speed,
   7.108 +		                                   &adapter->link_duplex);
   7.109 +		ecmd->speed = adapter->link_speed;
   7.110 +
   7.111 +		/* unfortunatly FULL_DUPLEX != DUPLEX_FULL
   7.112 +		 *          and HALF_DUPLEX != DUPLEX_HALF */
   7.113 +
   7.114 +		if(adapter->link_duplex == FULL_DUPLEX)
   7.115 +			ecmd->duplex = DUPLEX_FULL;
   7.116 +		else
   7.117 +			ecmd->duplex = DUPLEX_HALF;
   7.118 +	} else {
   7.119 +		ecmd->speed = -1;
   7.120 +		ecmd->duplex = -1;
   7.121 +	}
   7.122 +
   7.123 +	ecmd->autoneg = (hw->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
   7.124 +}
   7.125 +
   7.126 +static int
   7.127 +e1000_ethtool_sset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
   7.128 +{
   7.129 +	struct e1000_hw *hw = &adapter->hw;
   7.130 +
   7.131 +	if(ecmd->autoneg == AUTONEG_ENABLE) {
   7.132 +		hw->autoneg = 1;
   7.133 +		hw->autoneg_advertised = 0x002F;
   7.134 +		ecmd->advertising = 0x002F;
   7.135 +	} else {
   7.136 +		hw->autoneg = 0;
   7.137 +		switch(ecmd->speed + ecmd->duplex) {
   7.138 +		case SPEED_10 + DUPLEX_HALF:
   7.139 +			hw->forced_speed_duplex = e1000_10_half;
   7.140 +			break;
   7.141 +		case SPEED_10 + DUPLEX_FULL:
   7.142 +			hw->forced_speed_duplex = e1000_10_full;
   7.143 +			break;
   7.144 +		case SPEED_100 + DUPLEX_HALF:
   7.145 +			hw->forced_speed_duplex = e1000_100_half;
   7.146 +			break;
   7.147 +		case SPEED_100 + DUPLEX_FULL:
   7.148 +			hw->forced_speed_duplex = e1000_100_full;
   7.149 +			break;
   7.150 +		case SPEED_1000 + DUPLEX_FULL:
   7.151 +			hw->autoneg = 1;
   7.152 +			hw->autoneg_advertised = ADVERTISE_1000_FULL;
   7.153 +			break;
   7.154 +		case SPEED_1000 + DUPLEX_HALF: /* not supported */
   7.155 +		default:
   7.156 +			return -EINVAL;
   7.157 +		}
   7.158 +	}
   7.159 +
   7.160 +	/* reset the link */
   7.161 +
   7.162 +	if(netif_running(adapter->netdev)) {
   7.163 +		e1000_down(adapter);
   7.164 +		e1000_up(adapter);
   7.165 +	} else
   7.166 +		e1000_reset(adapter);
   7.167 +
   7.168 +	return 0;
   7.169 +}
   7.170 +
   7.171 +static inline int
   7.172 +e1000_eeprom_size(struct e1000_hw *hw)
   7.173 +{
   7.174 +	if((hw->mac_type > e1000_82544) &&
   7.175 +	   (E1000_READ_REG(hw, EECD) & E1000_EECD_SIZE))
   7.176 +		return 512;
   7.177 +	else
   7.178 +		return 128;
   7.179 +}
   7.180 +
   7.181 +static void
   7.182 +e1000_ethtool_gdrvinfo(struct e1000_adapter *adapter,
   7.183 +                       struct ethtool_drvinfo *drvinfo)
   7.184 +{
   7.185 +	strncpy(drvinfo->driver,  e1000_driver_name, 32);
   7.186 +	strncpy(drvinfo->version, e1000_driver_version, 32);
   7.187 +	strncpy(drvinfo->fw_version, "N/A", 32);
   7.188 +	strncpy(drvinfo->bus_info, adapter->pdev->slot_name, 32);
   7.189 +	drvinfo->n_stats = E1000_STATS_LEN;
   7.190 +#define E1000_REGS_LEN 32
   7.191 +	drvinfo->regdump_len  = E1000_REGS_LEN * sizeof(uint32_t);
   7.192 +	drvinfo->eedump_len  = e1000_eeprom_size(&adapter->hw);
   7.193 +}
   7.194 +
   7.195 +static void
   7.196 +e1000_ethtool_gregs(struct e1000_adapter *adapter,
   7.197 +                    struct ethtool_regs *regs, uint32_t *regs_buff)
   7.198 +{
   7.199 +	struct e1000_hw *hw = &adapter->hw;
   7.200 +
   7.201 +	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
   7.202 +
   7.203 +	regs_buff[0]  = E1000_READ_REG(hw, CTRL);
   7.204 +	regs_buff[1]  = E1000_READ_REG(hw, STATUS);
   7.205 +
   7.206 +	regs_buff[2]  = E1000_READ_REG(hw, RCTL);
   7.207 +	regs_buff[3]  = E1000_READ_REG(hw, RDLEN);
   7.208 +	regs_buff[4]  = E1000_READ_REG(hw, RDH);
   7.209 +	regs_buff[5]  = E1000_READ_REG(hw, RDT);
   7.210 +	regs_buff[6]  = E1000_READ_REG(hw, RDTR);
   7.211 +
   7.212 +	regs_buff[7]  = E1000_READ_REG(hw, TCTL);
   7.213 +	regs_buff[8]  = E1000_READ_REG(hw, TDLEN);
   7.214 +	regs_buff[9]  = E1000_READ_REG(hw, TDH);
   7.215 +	regs_buff[10] = E1000_READ_REG(hw, TDT);
   7.216 +	regs_buff[11] = E1000_READ_REG(hw, TIDV);
   7.217 +
   7.218 +	return;
   7.219 +}
   7.220 +
   7.221 +static int
   7.222 +e1000_ethtool_geeprom(struct e1000_adapter *adapter,
   7.223 +                      struct ethtool_eeprom *eeprom, uint16_t *eeprom_buff)
   7.224 +{
   7.225 +	struct e1000_hw *hw = &adapter->hw;
   7.226 +	int max_len, first_word, last_word;
   7.227 +	int ret_val = 0;
   7.228 +	int i;
   7.229 +
   7.230 +	if(eeprom->len == 0) {
   7.231 +		ret_val = -EINVAL;
   7.232 +		goto geeprom_error;
   7.233 +	}
   7.234 +
   7.235 +	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
   7.236 +
   7.237 +	max_len = e1000_eeprom_size(hw);
   7.238 +
   7.239 +	if(eeprom->offset > eeprom->offset + eeprom->len) {
   7.240 +		ret_val = -EINVAL;
   7.241 +		goto geeprom_error;
   7.242 +	}
   7.243 +
   7.244 +	if((eeprom->offset + eeprom->len) > max_len)
   7.245 +		eeprom->len = (max_len - eeprom->offset);
   7.246 +
   7.247 +	first_word = eeprom->offset >> 1;
   7.248 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
   7.249 +
   7.250 +	for(i = 0; i <= (last_word - first_word); i++)
   7.251 +		e1000_read_eeprom(hw, first_word + i, &eeprom_buff[i]);
   7.252 +
   7.253 +geeprom_error:
   7.254 +	return ret_val;
   7.255 +}
   7.256 +
   7.257 +static int
   7.258 +e1000_ethtool_seeprom(struct e1000_adapter *adapter,
   7.259 +                      struct ethtool_eeprom *eeprom, void *user_data)
   7.260 +{
   7.261 +	struct e1000_hw *hw = &adapter->hw;
   7.262 +	uint16_t *eeprom_buff;
   7.263 +	int max_len, first_word, last_word;
   7.264 +	void *ptr;
   7.265 +	int i;
   7.266 +
   7.267 +	if(eeprom->len == 0)
   7.268 +		return -EOPNOTSUPP;
   7.269 +
   7.270 +	if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
   7.271 +		return -EFAULT;
   7.272 +
   7.273 +	max_len = e1000_eeprom_size(hw);
   7.274 +
   7.275 +	if((eeprom->offset + eeprom->len) > max_len)
   7.276 +		eeprom->len = (max_len - eeprom->offset);
   7.277 +
   7.278 +	first_word = eeprom->offset >> 1;
   7.279 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
   7.280 +	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
   7.281 +	if(eeprom_buff == NULL)
   7.282 +		return -ENOMEM;
   7.283 +
   7.284 +	ptr = (void *)eeprom_buff;
   7.285 +
   7.286 +	if(eeprom->offset & 1) {
   7.287 +		/* need read/modify/write of first changed EEPROM word */
   7.288 +		/* only the second byte of the word is being modified */
   7.289 +		e1000_read_eeprom(hw, first_word, &eeprom_buff[0]);
   7.290 +		ptr++;
   7.291 +	}
   7.292 +	if((eeprom->offset + eeprom->len) & 1) {
   7.293 +		/* need read/modify/write of last changed EEPROM word */
   7.294 +		/* only the first byte of the word is being modified */
   7.295 +		e1000_read_eeprom(hw, last_word,
   7.296 +		                  &eeprom_buff[last_word - first_word]);
   7.297 +	}
   7.298 +	if(copy_from_user(ptr, user_data, eeprom->len)) {
   7.299 +		kfree(eeprom_buff);
   7.300 +		return -EFAULT;
   7.301 +	}
   7.302 +
   7.303 +	for(i = 0; i <= (last_word - first_word); i++)
   7.304 +		e1000_write_eeprom(hw, first_word + i, eeprom_buff[i]);
   7.305 +
   7.306 +	/* Update the checksum over the first part of the EEPROM if needed */
   7.307 +	if(first_word <= EEPROM_CHECKSUM_REG)
   7.308 +		e1000_update_eeprom_checksum(hw);
   7.309 +
   7.310 +	kfree(eeprom_buff);
   7.311 +
   7.312 +	return 0;
   7.313 +}
   7.314 +
   7.315 +static void
   7.316 +e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
   7.317 +{
   7.318 +	struct e1000_hw *hw = &adapter->hw;
   7.319 +
   7.320 +	switch(adapter->hw.device_id) {
   7.321 +	case E1000_DEV_ID_82542:
   7.322 +	case E1000_DEV_ID_82543GC_FIBER:
   7.323 +	case E1000_DEV_ID_82543GC_COPPER:
   7.324 +	case E1000_DEV_ID_82544EI_FIBER:
   7.325 +		wol->supported = 0;
   7.326 +		wol->wolopts   = 0;
   7.327 +		return;
   7.328 +
   7.329 +	case E1000_DEV_ID_82546EB_FIBER:
   7.330 +		/* Wake events only supported on port A for dual fiber */
   7.331 +		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
   7.332 +			wol->supported = 0;
   7.333 +			wol->wolopts   = 0;
   7.334 +			return;
   7.335 +		}
   7.336 +		/* Fall Through */
   7.337 +
   7.338 +	default:
   7.339 +		wol->supported = WAKE_UCAST | WAKE_MCAST
   7.340 +			         | WAKE_BCAST | WAKE_MAGIC;
   7.341 +
   7.342 +		wol->wolopts = 0;
   7.343 +		if(adapter->wol & E1000_WUFC_EX)
   7.344 +			wol->wolopts |= WAKE_UCAST;
   7.345 +		if(adapter->wol & E1000_WUFC_MC)
   7.346 +			wol->wolopts |= WAKE_MCAST;
   7.347 +		if(adapter->wol & E1000_WUFC_BC)
   7.348 +			wol->wolopts |= WAKE_BCAST;
   7.349 +		if(adapter->wol & E1000_WUFC_MAG)
   7.350 +			wol->wolopts |= WAKE_MAGIC;
   7.351 +		return;
   7.352 +	}
   7.353 +}
   7.354 +
   7.355 +static int
   7.356 +e1000_ethtool_swol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
   7.357 +{
   7.358 +	struct e1000_hw *hw = &adapter->hw;
   7.359 +
   7.360 +	switch(adapter->hw.device_id) {
   7.361 +	case E1000_DEV_ID_82542:
   7.362 +	case E1000_DEV_ID_82543GC_FIBER:
   7.363 +	case E1000_DEV_ID_82543GC_COPPER:
   7.364 +	case E1000_DEV_ID_82544EI_FIBER:
   7.365 +		return wol->wolopts ? -EOPNOTSUPP : 0;
   7.366 +
   7.367 +	case E1000_DEV_ID_82546EB_FIBER:
   7.368 +		/* Wake events only supported on port A for dual fiber */
   7.369 +		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
   7.370 +			return wol->wolopts ? -EOPNOTSUPP : 0;
   7.371 +		/* Fall Through */
   7.372 +
   7.373 +	default:
   7.374 +		if(wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY))
   7.375 +			return -EOPNOTSUPP;
   7.376 +
   7.377 +		adapter->wol = 0;
   7.378 +
   7.379 +		if(wol->wolopts & WAKE_UCAST)
   7.380 +			adapter->wol |= E1000_WUFC_EX;
   7.381 +		if(wol->wolopts & WAKE_MCAST)
   7.382 +			adapter->wol |= E1000_WUFC_MC;
   7.383 +		if(wol->wolopts & WAKE_BCAST)
   7.384 +			adapter->wol |= E1000_WUFC_BC;
   7.385 +		if(wol->wolopts & WAKE_MAGIC)
   7.386 +			adapter->wol |= E1000_WUFC_MAG;
   7.387 +	}
   7.388 +
   7.389 +	return 0;
   7.390 +}
   7.391 +
   7.392 +
   7.393 +/* toggle LED 4 times per second = 2 "blinks" per second */
   7.394 +#define E1000_ID_INTERVAL	(HZ/4)
   7.395 +
   7.396 +/* bit defines for adapter->led_status */
   7.397 +#define E1000_LED_ON		0
   7.398 +
   7.399 +static void
   7.400 +e1000_led_blink_callback(unsigned long data)
   7.401 +{
   7.402 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
   7.403 +
   7.404 +	if(test_and_change_bit(E1000_LED_ON, &adapter->led_status))
   7.405 +		e1000_led_off(&adapter->hw);
   7.406 +	else
   7.407 +		e1000_led_on(&adapter->hw);
   7.408 +
   7.409 +	mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
   7.410 +}
   7.411 +
   7.412 +static int
   7.413 +e1000_ethtool_led_blink(struct e1000_adapter *adapter, struct ethtool_value *id)
   7.414 +{
   7.415 +	if(!adapter->blink_timer.function) {
   7.416 +		init_timer(&adapter->blink_timer);
   7.417 +		adapter->blink_timer.function = e1000_led_blink_callback;
   7.418 +		adapter->blink_timer.data = (unsigned long) adapter;
   7.419 +	}
   7.420 +
   7.421 +	e1000_setup_led(&adapter->hw);
   7.422 +	mod_timer(&adapter->blink_timer, jiffies);
   7.423 +
   7.424 +	set_current_state(TASK_INTERRUPTIBLE);
   7.425 +	if(id->data)
   7.426 +		schedule_timeout(id->data * HZ);
   7.427 +	else
   7.428 +		schedule_timeout(MAX_SCHEDULE_TIMEOUT);
   7.429 +
   7.430 +	del_timer_sync(&adapter->blink_timer);
   7.431 +	e1000_led_off(&adapter->hw);
   7.432 +	clear_bit(E1000_LED_ON, &adapter->led_status);
   7.433 +	e1000_cleanup_led(&adapter->hw);
   7.434 +
   7.435 +	return 0;
   7.436 +}
   7.437 +
   7.438 +int
   7.439 +e1000_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr)
   7.440 +{
   7.441 +	struct e1000_adapter *adapter = netdev->priv;
   7.442 +	void *addr = ifr->ifr_data;
   7.443 +	uint32_t cmd;
   7.444 +
   7.445 +	if(get_user(cmd, (uint32_t *) addr))
   7.446 +		return -EFAULT;
   7.447 +
   7.448 +	switch(cmd) {
   7.449 +	case ETHTOOL_GSET: {
   7.450 +		struct ethtool_cmd ecmd = {ETHTOOL_GSET};
   7.451 +		e1000_ethtool_gset(adapter, &ecmd);
   7.452 +		if(copy_to_user(addr, &ecmd, sizeof(ecmd)))
   7.453 +			return -EFAULT;
   7.454 +		return 0;
   7.455 +	}
   7.456 +	case ETHTOOL_SSET: {
   7.457 +		struct ethtool_cmd ecmd;
   7.458 +		if(!capable(CAP_NET_ADMIN))
   7.459 +			return -EPERM;
   7.460 +		if(copy_from_user(&ecmd, addr, sizeof(ecmd)))
   7.461 +			return -EFAULT;
   7.462 +		return e1000_ethtool_sset(adapter, &ecmd);
   7.463 +	}
   7.464 +	case ETHTOOL_GDRVINFO: {
   7.465 +		struct ethtool_drvinfo drvinfo = {ETHTOOL_GDRVINFO};
   7.466 +		e1000_ethtool_gdrvinfo(adapter, &drvinfo);
   7.467 +		if(copy_to_user(addr, &drvinfo, sizeof(drvinfo)))
   7.468 +			return -EFAULT;
   7.469 +		return 0;
   7.470 +	}
   7.471 +	case ETHTOOL_GSTRINGS: {
   7.472 +		struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
   7.473 +		char *strings = NULL;
   7.474 +
   7.475 +		if(copy_from_user(&gstrings, addr, sizeof(gstrings)))
   7.476 +			return -EFAULT;
   7.477 +		switch(gstrings.string_set) {
   7.478 +		case ETH_SS_STATS:
   7.479 +			gstrings.len = E1000_STATS_LEN;
   7.480 +			strings = *e1000_gstrings_stats;
   7.481 +			break;
   7.482 +		default:
   7.483 +			return -EOPNOTSUPP;
   7.484 +		}
   7.485 +		if(copy_to_user(addr, &gstrings, sizeof(gstrings)))
   7.486 +			return -EFAULT;
   7.487 +		addr += offsetof(struct ethtool_gstrings, data);
   7.488 +		if(copy_to_user(addr, strings,
   7.489 +		   gstrings.len * ETH_GSTRING_LEN))
   7.490 +			return -EFAULT;
   7.491 +		return 0;
   7.492 +	}
   7.493 +	case ETHTOOL_GREGS: {
   7.494 +		struct ethtool_regs regs = {ETHTOOL_GREGS};
   7.495 +		uint32_t regs_buff[E1000_REGS_LEN];
   7.496 +
   7.497 +		if(copy_from_user(&regs, addr, sizeof(regs)))
   7.498 +			return -EFAULT;
   7.499 +		e1000_ethtool_gregs(adapter, &regs, regs_buff);
   7.500 +		if(copy_to_user(addr, &regs, sizeof(regs)))
   7.501 +			return -EFAULT;
   7.502 +
   7.503 +		addr += offsetof(struct ethtool_regs, data);
   7.504 +		if(copy_to_user(addr, regs_buff, regs.len))
   7.505 +			return -EFAULT;
   7.506 +
   7.507 +		return 0;
   7.508 +	}
   7.509 +	case ETHTOOL_NWAY_RST: {
   7.510 +		if(!capable(CAP_NET_ADMIN))
   7.511 +			return -EPERM;
   7.512 +		if(netif_running(netdev)) {
   7.513 +			e1000_down(adapter);
   7.514 +			e1000_up(adapter);
   7.515 +		}
   7.516 +		return 0;
   7.517 +	}
   7.518 +	case ETHTOOL_PHYS_ID: {
   7.519 +		struct ethtool_value id;
   7.520 +		if(copy_from_user(&id, addr, sizeof(id)))
   7.521 +			return -EFAULT;
   7.522 +		return e1000_ethtool_led_blink(adapter, &id);
   7.523 +	}
   7.524 +	case ETHTOOL_GLINK: {
   7.525 +		struct ethtool_value link = {ETHTOOL_GLINK};
   7.526 +		link.data = netif_carrier_ok(netdev);
   7.527 +		if(copy_to_user(addr, &link, sizeof(link)))
   7.528 +			return -EFAULT;
   7.529 +		return 0;
   7.530 +	}
   7.531 +	case ETHTOOL_GWOL: {
   7.532 +		struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
   7.533 +		e1000_ethtool_gwol(adapter, &wol);
   7.534 +		if(copy_to_user(addr, &wol, sizeof(wol)) != 0)
   7.535 +			return -EFAULT;
   7.536 +		return 0;
   7.537 +	}
   7.538 +	case ETHTOOL_SWOL: {
   7.539 +		struct ethtool_wolinfo wol;
   7.540 +		if(!capable(CAP_NET_ADMIN))
   7.541 +			return -EPERM;
   7.542 +		if(copy_from_user(&wol, addr, sizeof(wol)) != 0)
   7.543 +			return -EFAULT;
   7.544 +		return e1000_ethtool_swol(adapter, &wol);
   7.545 +	}
   7.546 +	case ETHTOOL_GEEPROM: {
   7.547 +		struct ethtool_eeprom eeprom = {ETHTOOL_GEEPROM};
   7.548 +		uint16_t *eeprom_buff;
   7.549 +		void *ptr;
   7.550 +		int max_len, err = 0;
   7.551 +
   7.552 +		max_len = e1000_eeprom_size(&adapter->hw);
   7.553 +
   7.554 +		eeprom_buff = kmalloc(max_len, GFP_KERNEL);
   7.555 +
   7.556 +		if(eeprom_buff == NULL)
   7.557 +			return -ENOMEM;
   7.558 +
   7.559 +		if(copy_from_user(&eeprom, addr, sizeof(eeprom))) {
   7.560 +			err = -EFAULT;
   7.561 +			goto err_geeprom_ioctl;
   7.562 +		}
   7.563 +
   7.564 +		if((err = e1000_ethtool_geeprom(adapter, &eeprom,
   7.565 +						eeprom_buff)))
   7.566 +			goto err_geeprom_ioctl;
   7.567 +
   7.568 +		if(copy_to_user(addr, &eeprom, sizeof(eeprom))) {
   7.569 +			err = -EFAULT;
   7.570 +			goto err_geeprom_ioctl;
   7.571 +		}
   7.572 +
   7.573 +		addr += offsetof(struct ethtool_eeprom, data);
   7.574 +		ptr = ((void *)eeprom_buff) + (eeprom.offset & 1);
   7.575 +
   7.576 +		if(copy_to_user(addr, ptr, eeprom.len))
   7.577 +			err = -EFAULT;
   7.578 +
   7.579 +err_geeprom_ioctl:
   7.580 +		kfree(eeprom_buff);
   7.581 +		return err;
   7.582 +	}
   7.583 +	case ETHTOOL_SEEPROM: {
   7.584 +		struct ethtool_eeprom eeprom;
   7.585 +
   7.586 +		if(!capable(CAP_NET_ADMIN))
   7.587 +			return -EPERM;
   7.588 +
   7.589 +		if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
   7.590 +			return -EFAULT;
   7.591 +
   7.592 +		addr += offsetof(struct ethtool_eeprom, data);
   7.593 +		return e1000_ethtool_seeprom(adapter, &eeprom, addr);
   7.594 +	}
   7.595 +	case ETHTOOL_GSTATS: {
   7.596 +		struct {
   7.597 +			struct ethtool_stats cmd;
   7.598 +			uint64_t data[E1000_STATS_LEN];
   7.599 +		} stats = { {ETHTOOL_GSTATS, E1000_STATS_LEN} };
   7.600 +		int i;
   7.601 +
   7.602 +		for(i = 0; i < E1000_STATS_LEN; i++)
   7.603 +			stats.data[i] =
   7.604 +				((unsigned long *)&adapter->net_stats)[i];
   7.605 +		if(copy_to_user(addr, &stats, sizeof(stats)))
   7.606 +			return -EFAULT;
   7.607 +		return 0;
   7.608 +	}
   7.609 +	default:
   7.610 +		return -EOPNOTSUPP;
   7.611 +	}
   7.612 +}
   7.613 +
   7.614 +
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_hw.c	Sat Feb 08 17:39:26 2003 +0000
     8.3 @@ -0,0 +1,3610 @@
     8.4 +/*******************************************************************************
     8.5 +
     8.6 +  
     8.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     8.8 +  
     8.9 +  This program is free software; you can redistribute it and/or modify it 
    8.10 +  under the terms of the GNU General Public License as published by the Free 
    8.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    8.12 +  any later version.
    8.13 +  
    8.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    8.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    8.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    8.17 +  more details.
    8.18 +  
    8.19 +  You should have received a copy of the GNU General Public License along with
    8.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    8.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    8.22 +  
    8.23 +  The full GNU General Public License is included in this distribution in the
    8.24 +  file called LICENSE.
    8.25 +  
    8.26 +  Contact Information:
    8.27 +  Linux NICS <linux.nics@intel.com>
    8.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    8.29 +
    8.30 +*******************************************************************************/
    8.31 +
    8.32 +/* e1000_hw.c
    8.33 + * Shared functions for accessing and configuring the MAC
    8.34 + */
    8.35 +
    8.36 +#include "e1000_hw.h"
    8.37 +
    8.38 +static int32_t e1000_setup_fiber_link(struct e1000_hw *hw);
    8.39 +static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
    8.40 +static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
    8.41 +static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
    8.42 +static int32_t e1000_force_mac_fc(struct e1000_hw *hw);
    8.43 +static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
    8.44 +static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
    8.45 +static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count);
    8.46 +static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
    8.47 +static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
    8.48 +static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
    8.49 +static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
    8.50 +static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count);
    8.51 +static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw);
    8.52 +static void e1000_setup_eeprom(struct e1000_hw *hw);
    8.53 +static void e1000_clock_eeprom(struct e1000_hw *hw);
    8.54 +static void e1000_cleanup_eeprom(struct e1000_hw *hw);
    8.55 +static void e1000_standby_eeprom(struct e1000_hw *hw);
    8.56 +static int32_t e1000_id_led_init(struct e1000_hw * hw);
    8.57 +
    8.58 +/******************************************************************************
    8.59 + * Set the mac type member in the hw struct.
    8.60 + * 
    8.61 + * hw - Struct containing variables accessed by shared code
    8.62 + *****************************************************************************/
    8.63 +int32_t
    8.64 +e1000_set_mac_type(struct e1000_hw *hw)
    8.65 +{
    8.66 +    DEBUGFUNC("e1000_set_mac_type");
    8.67 +
    8.68 +    switch (hw->device_id) {
    8.69 +    case E1000_DEV_ID_82542:
    8.70 +        switch (hw->revision_id) {
    8.71 +        case E1000_82542_2_0_REV_ID:
    8.72 +            hw->mac_type = e1000_82542_rev2_0;
    8.73 +            break;
    8.74 +        case E1000_82542_2_1_REV_ID:
    8.75 +            hw->mac_type = e1000_82542_rev2_1;
    8.76 +            break;
    8.77 +        default:
    8.78 +            /* Invalid 82542 revision ID */
    8.79 +            return -E1000_ERR_MAC_TYPE;
    8.80 +        }
    8.81 +        break;
    8.82 +    case E1000_DEV_ID_82543GC_FIBER:
    8.83 +    case E1000_DEV_ID_82543GC_COPPER:
    8.84 +        hw->mac_type = e1000_82543;
    8.85 +        break;
    8.86 +    case E1000_DEV_ID_82544EI_COPPER:
    8.87 +    case E1000_DEV_ID_82544EI_FIBER:
    8.88 +    case E1000_DEV_ID_82544GC_COPPER:
    8.89 +    case E1000_DEV_ID_82544GC_LOM:
    8.90 +        hw->mac_type = e1000_82544;
    8.91 +        break;
    8.92 +    case E1000_DEV_ID_82540EM:
    8.93 +    case E1000_DEV_ID_82540EM_LOM:
    8.94 +    case E1000_DEV_ID_82540EP:
    8.95 +    case E1000_DEV_ID_82540EP_LOM:
    8.96 +    case E1000_DEV_ID_82540EP_LP:
    8.97 +        hw->mac_type = e1000_82540;
    8.98 +        break;
    8.99 +    case E1000_DEV_ID_82545EM_COPPER:
   8.100 +    case E1000_DEV_ID_82545EM_FIBER:
   8.101 +        hw->mac_type = e1000_82545;
   8.102 +        break;
   8.103 +    case E1000_DEV_ID_82546EB_COPPER:
   8.104 +    case E1000_DEV_ID_82546EB_FIBER:
   8.105 +        hw->mac_type = e1000_82546;
   8.106 +        break;
   8.107 +    default:
   8.108 +        /* Should never have loaded on this device */
   8.109 +        return -E1000_ERR_MAC_TYPE;
   8.110 +    }
   8.111 +    return E1000_SUCCESS;
   8.112 +}
   8.113 +/******************************************************************************
   8.114 + * Reset the transmit and receive units; mask and clear all interrupts.
   8.115 + *
   8.116 + * hw - Struct containing variables accessed by shared code
   8.117 + *****************************************************************************/
   8.118 +void
   8.119 +e1000_reset_hw(struct e1000_hw *hw)
   8.120 +{
   8.121 +    uint32_t ctrl;
   8.122 +    uint32_t ctrl_ext;
   8.123 +    uint32_t icr;
   8.124 +    uint32_t manc;
   8.125 +
   8.126 +    DEBUGFUNC("e1000_reset_hw");
   8.127 +    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
   8.128 +    if(hw->mac_type == e1000_82542_rev2_0) {
   8.129 +        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
   8.130 +        e1000_pci_clear_mwi(hw);
   8.131 +    }
   8.132 +
   8.133 +    /* Clear interrupt mask to stop board from generating interrupts */
   8.134 +    DEBUGOUT("Masking off all interrupts\n");
   8.135 +    E1000_WRITE_REG(hw, IMC, 0xffffffff);
   8.136 +
   8.137 +    /* Disable the Transmit and Receive units.  Then delay to allow
   8.138 +     * any pending transactions to complete before we hit the MAC with
   8.139 +     * the global reset.
   8.140 +     */
   8.141 +    E1000_WRITE_REG(hw, RCTL, 0);
   8.142 +    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
   8.143 +    E1000_WRITE_FLUSH(hw);
   8.144 +
   8.145 +    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
   8.146 +    hw->tbi_compatibility_on = FALSE;
   8.147 +
   8.148 +    /* Delay to allow any outstanding PCI transactions to complete before
   8.149 +     * resetting the device
   8.150 +     */ 
   8.151 +    DEBUGOUT("Before delay\n");
   8.152 +    msec_delay(10);
   8.153 +
   8.154 +    /* Issue a global reset to the MAC.  This will reset the chip's
   8.155 +     * transmit, receive, DMA, and link units.  It will not effect
   8.156 +     * the current PCI configuration.  The global reset bit is self-
   8.157 +     * clearing, and should clear within a microsecond.
   8.158 +     */
   8.159 +    DEBUGOUT("Issuing a global reset to MAC\n");
   8.160 +    ctrl = E1000_READ_REG(hw, CTRL);
   8.161 +
   8.162 +    if(hw->mac_type > e1000_82543)
   8.163 +        E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
   8.164 +    else
   8.165 +        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
   8.166 +
   8.167 +    /* Force a reload from the EEPROM if necessary */
   8.168 +    if(hw->mac_type < e1000_82540) {
   8.169 +        /* Wait for reset to complete */
   8.170 +        udelay(10);
   8.171 +        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
   8.172 +        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
   8.173 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
   8.174 +        E1000_WRITE_FLUSH(hw);
   8.175 +        /* Wait for EEPROM reload */
   8.176 +        msec_delay(2);
   8.177 +    } else {
   8.178 +        /* Wait for EEPROM reload (it happens automatically) */
   8.179 +        msec_delay(4);
   8.180 +        /* Dissable HW ARPs on ASF enabled adapters */
   8.181 +        manc = E1000_READ_REG(hw, MANC);
   8.182 +        manc &= ~(E1000_MANC_ARP_EN);
   8.183 +        E1000_WRITE_REG(hw, MANC, manc);
   8.184 +    }
   8.185 +    
   8.186 +    /* Clear interrupt mask to stop board from generating interrupts */
   8.187 +    DEBUGOUT("Masking off all interrupts\n");
   8.188 +    E1000_WRITE_REG(hw, IMC, 0xffffffff);
   8.189 +
   8.190 +    /* Clear any pending interrupt events. */
   8.191 +    icr = E1000_READ_REG(hw, ICR);
   8.192 +
   8.193 +    /* If MWI was previously enabled, reenable it. */
   8.194 +    if(hw->mac_type == e1000_82542_rev2_0) {
   8.195 +        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
   8.196 +            e1000_pci_set_mwi(hw);
   8.197 +    }
   8.198 +}
   8.199 +
   8.200 +/******************************************************************************
   8.201 + * Performs basic configuration of the adapter.
   8.202 + *
   8.203 + * hw - Struct containing variables accessed by shared code
   8.204 + * 
   8.205 + * Assumes that the controller has previously been reset and is in a 
   8.206 + * post-reset uninitialized state. Initializes the receive address registers,
   8.207 + * multicast table, and VLAN filter table. Calls routines to setup link
   8.208 + * configuration and flow control settings. Clears all on-chip counters. Leaves
   8.209 + * the transmit and receive units disabled and uninitialized.
   8.210 + *****************************************************************************/
   8.211 +int32_t
   8.212 +e1000_init_hw(struct e1000_hw *hw)
   8.213 +{
   8.214 +    uint32_t ctrl, status;
   8.215 +    uint32_t i;
   8.216 +    int32_t ret_val;
   8.217 +    uint16_t pcix_cmd_word;
   8.218 +    uint16_t pcix_stat_hi_word;
   8.219 +    uint16_t cmd_mmrbc;
   8.220 +    uint16_t stat_mmrbc;
   8.221 +
   8.222 +    DEBUGFUNC("e1000_init_hw");
   8.223 +
   8.224 +    /* Initialize Identification LED */
   8.225 +    ret_val = e1000_id_led_init(hw);
   8.226 +    if(ret_val < 0) {
   8.227 +        DEBUGOUT("Error Initializing Identification LED\n");
   8.228 +        return ret_val;
   8.229 +    }
   8.230 +    
   8.231 +    /* Set the Media Type and exit with error if it is not valid. */
   8.232 +    if(hw->mac_type != e1000_82543) {
   8.233 +        /* tbi_compatibility is only valid on 82543 */
   8.234 +        hw->tbi_compatibility_en = FALSE;
   8.235 +    }
   8.236 +
   8.237 +    if(hw->mac_type >= e1000_82543) {
   8.238 +        status = E1000_READ_REG(hw, STATUS);
   8.239 +        if(status & E1000_STATUS_TBIMODE) {
   8.240 +            hw->media_type = e1000_media_type_fiber;
   8.241 +            /* tbi_compatibility not valid on fiber */
   8.242 +            hw->tbi_compatibility_en = FALSE;
   8.243 +        } else {
   8.244 +            hw->media_type = e1000_media_type_copper;
   8.245 +        }
   8.246 +    } else {
   8.247 +        /* This is an 82542 (fiber only) */
   8.248 +        hw->media_type = e1000_media_type_fiber;
   8.249 +    }
   8.250 +
   8.251 +    /* Disabling VLAN filtering. */
   8.252 +    DEBUGOUT("Initializing the IEEE VLAN\n");
   8.253 +    E1000_WRITE_REG(hw, VET, 0);
   8.254 +
   8.255 +    e1000_clear_vfta(hw);
   8.256 +
   8.257 +    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
   8.258 +    if(hw->mac_type == e1000_82542_rev2_0) {
   8.259 +        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
   8.260 +        e1000_pci_clear_mwi(hw);
   8.261 +        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
   8.262 +        E1000_WRITE_FLUSH(hw);
   8.263 +        msec_delay(5);
   8.264 +    }
   8.265 +
   8.266 +    /* Setup the receive address. This involves initializing all of the Receive
   8.267 +     * Address Registers (RARs 0 - 15).
   8.268 +     */
   8.269 +    e1000_init_rx_addrs(hw);
   8.270 +
   8.271 +    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
   8.272 +    if(hw->mac_type == e1000_82542_rev2_0) {
   8.273 +        E1000_WRITE_REG(hw, RCTL, 0);
   8.274 +        E1000_WRITE_FLUSH(hw);
   8.275 +        msec_delay(1);
   8.276 +        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
   8.277 +            e1000_pci_set_mwi(hw);
   8.278 +    }
   8.279 +
   8.280 +    /* Zero out the Multicast HASH table */
   8.281 +    DEBUGOUT("Zeroing the MTA\n");
   8.282 +    for(i = 0; i < E1000_MC_TBL_SIZE; i++)
   8.283 +        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
   8.284 +
   8.285 +    /* Set the PCI priority bit correctly in the CTRL register.  This
   8.286 +     * determines if the adapter gives priority to receives, or if it
   8.287 +     * gives equal priority to transmits and receives.
   8.288 +     */
   8.289 +    if(hw->dma_fairness) {
   8.290 +        ctrl = E1000_READ_REG(hw, CTRL);
   8.291 +        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
   8.292 +    }
   8.293 +
   8.294 +    /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
   8.295 +    if(hw->bus_type == e1000_bus_type_pcix) {
   8.296 +        e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
   8.297 +        e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
   8.298 +        cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
   8.299 +            PCIX_COMMAND_MMRBC_SHIFT;
   8.300 +        stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
   8.301 +            PCIX_STATUS_HI_MMRBC_SHIFT;
   8.302 +        if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
   8.303 +            stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
   8.304 +        if(cmd_mmrbc > stat_mmrbc) {
   8.305 +            pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
   8.306 +            pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
   8.307 +            e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
   8.308 +        }
   8.309 +    }
   8.310 +
   8.311 +    /* Call a subroutine to configure the link and setup flow control. */
   8.312 +    ret_val = e1000_setup_link(hw);
   8.313 +
   8.314 +    /* Set the transmit descriptor write-back policy */
   8.315 +    if(hw->mac_type > e1000_82544) {
   8.316 +        ctrl = E1000_READ_REG(hw, TXDCTL);
   8.317 +        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
   8.318 +        E1000_WRITE_REG(hw, TXDCTL, ctrl);
   8.319 +    }
   8.320 +
   8.321 +    /* Clear all of the statistics registers (clear on read).  It is
   8.322 +     * important that we do this after we have tried to establish link
   8.323 +     * because the symbol error count will increment wildly if there
   8.324 +     * is no link.
   8.325 +     */
   8.326 +    e1000_clear_hw_cntrs(hw);
   8.327 +
   8.328 +    return ret_val;
   8.329 +}
   8.330 +
   8.331 +/******************************************************************************
   8.332 + * Configures flow control and link settings.
   8.333 + * 
   8.334 + * hw - Struct containing variables accessed by shared code
   8.335 + * 
   8.336 + * Determines which flow control settings to use. Calls the apropriate media-
   8.337 + * specific link configuration function. Configures the flow control settings.
   8.338 + * Assuming the adapter has a valid link partner, a valid link should be
   8.339 + * established. Assumes the hardware has previously been reset and the 
   8.340 + * transmitter and receiver are not enabled.
   8.341 + *****************************************************************************/
   8.342 +int32_t
   8.343 +e1000_setup_link(struct e1000_hw *hw)
   8.344 +{
   8.345 +    uint32_t ctrl_ext;
   8.346 +    int32_t ret_val;
   8.347 +    uint16_t eeprom_data;
   8.348 +
   8.349 +    DEBUGFUNC("e1000_setup_link");
   8.350 +
   8.351 +    /* Read and store word 0x0F of the EEPROM. This word contains bits
   8.352 +     * that determine the hardware's default PAUSE (flow control) mode,
   8.353 +     * a bit that determines whether the HW defaults to enabling or
   8.354 +     * disabling auto-negotiation, and the direction of the
   8.355 +     * SW defined pins. If there is no SW over-ride of the flow
   8.356 +     * control setting, then the variable hw->fc will
   8.357 +     * be initialized based on a value in the EEPROM.
   8.358 +     */
   8.359 +    if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
   8.360 +        DEBUGOUT("EEPROM Read Error\n");
   8.361 +        return -E1000_ERR_EEPROM;
   8.362 +    }
   8.363 +
   8.364 +    if(hw->fc == e1000_fc_default) {
   8.365 +        if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
   8.366 +            hw->fc = e1000_fc_none;
   8.367 +        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
   8.368 +                EEPROM_WORD0F_ASM_DIR)
   8.369 +            hw->fc = e1000_fc_tx_pause;
   8.370 +        else
   8.371 +            hw->fc = e1000_fc_full;
   8.372 +    }
   8.373 +
   8.374 +    /* We want to save off the original Flow Control configuration just
   8.375 +     * in case we get disconnected and then reconnected into a different
   8.376 +     * hub or switch with different Flow Control capabilities.
   8.377 +     */
   8.378 +    if(hw->mac_type == e1000_82542_rev2_0)
   8.379 +        hw->fc &= (~e1000_fc_tx_pause);
   8.380 +
   8.381 +    if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
   8.382 +        hw->fc &= (~e1000_fc_rx_pause);
   8.383 +
   8.384 +    hw->original_fc = hw->fc;
   8.385 +
   8.386 +    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
   8.387 +
   8.388 +    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
   8.389 +     * polarity value for the SW controlled pins, and setup the
   8.390 +     * Extended Device Control reg with that info.
   8.391 +     * This is needed because one of the SW controlled pins is used for
   8.392 +     * signal detection.  So this should be done before e1000_setup_pcs_link()
   8.393 +     * or e1000_phy_setup() is called.
   8.394 +     */
   8.395 +    if(hw->mac_type == e1000_82543) {
   8.396 +        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
   8.397 +                    SWDPIO__EXT_SHIFT);
   8.398 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
   8.399 +    }
   8.400 +
   8.401 +    /* Call the necessary subroutine to configure the link. */
   8.402 +    ret_val = (hw->media_type == e1000_media_type_fiber) ?
   8.403 +              e1000_setup_fiber_link(hw) :
   8.404 +              e1000_setup_copper_link(hw);
   8.405 +
   8.406 +    /* Initialize the flow control address, type, and PAUSE timer
   8.407 +     * registers to their default values.  This is done even if flow
   8.408 +     * control is disabled, because it does not hurt anything to
   8.409 +     * initialize these registers.
   8.410 +     */
   8.411 +    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
   8.412 +
   8.413 +    E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
   8.414 +    E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
   8.415 +    E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
   8.416 +    E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
   8.417 +
   8.418 +    /* Set the flow control receive threshold registers.  Normally,
   8.419 +     * these registers will be set to a default threshold that may be
   8.420 +     * adjusted later by the driver's runtime code.  However, if the
   8.421 +     * ability to transmit pause frames in not enabled, then these
   8.422 +     * registers will be set to 0. 
   8.423 +     */
   8.424 +    if(!(hw->fc & e1000_fc_tx_pause)) {
   8.425 +        E1000_WRITE_REG(hw, FCRTL, 0);
   8.426 +        E1000_WRITE_REG(hw, FCRTH, 0);
   8.427 +    } else {
   8.428 +        /* We need to set up the Receive Threshold high and low water marks
   8.429 +         * as well as (optionally) enabling the transmission of XON frames.
   8.430 +         */
   8.431 +        if(hw->fc_send_xon) {
   8.432 +            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
   8.433 +            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
   8.434 +        } else {
   8.435 +            E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
   8.436 +            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
   8.437 +        }
   8.438 +    }
   8.439 +    return ret_val;
   8.440 +}
   8.441 +
   8.442 +/******************************************************************************
   8.443 + * Sets up link for a fiber based adapter
   8.444 + *
   8.445 + * hw - Struct containing variables accessed by shared code
   8.446 + *
   8.447 + * Manipulates Physical Coding Sublayer functions in order to configure
   8.448 + * link. Assumes the hardware has been previously reset and the transmitter
   8.449 + * and receiver are not enabled.
   8.450 + *****************************************************************************/
   8.451 +static int32_t 
   8.452 +e1000_setup_fiber_link(struct e1000_hw *hw)
   8.453 +{
   8.454 +    uint32_t ctrl;
   8.455 +    uint32_t status;
   8.456 +    uint32_t txcw = 0;
   8.457 +    uint32_t i;
   8.458 +    uint32_t signal;
   8.459 +    int32_t ret_val;
   8.460 +
   8.461 +    DEBUGFUNC("e1000_setup_fiber_link");
   8.462 +
   8.463 +    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
   8.464 +     * set when the optics detect a signal. On older adapters, it will be 
   8.465 +     * cleared when there is a signal
   8.466 +     */
   8.467 +    ctrl = E1000_READ_REG(hw, CTRL);
   8.468 +    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
   8.469 +    else signal = 0;
   8.470 +   
   8.471 +    /* Take the link out of reset */
   8.472 +    ctrl &= ~(E1000_CTRL_LRST);
   8.473 +    
   8.474 +    e1000_config_collision_dist(hw);
   8.475 +
   8.476 +    /* Check for a software override of the flow control settings, and setup
   8.477 +     * the device accordingly.  If auto-negotiation is enabled, then software
   8.478 +     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
   8.479 +     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
   8.480 +     * auto-negotiation is disabled, then software will have to manually 
   8.481 +     * configure the two flow control enable bits in the CTRL register.
   8.482 +     *
   8.483 +     * The possible values of the "fc" parameter are:
   8.484 +     *      0:  Flow control is completely disabled
   8.485 +     *      1:  Rx flow control is enabled (we can receive pause frames, but 
   8.486 +     *          not send pause frames).
   8.487 +     *      2:  Tx flow control is enabled (we can send pause frames but we do
   8.488 +     *          not support receiving pause frames).
   8.489 +     *      3:  Both Rx and TX flow control (symmetric) are enabled.
   8.490 +     */
   8.491 +    switch (hw->fc) {
   8.492 +    case e1000_fc_none:
   8.493 +        /* Flow control is completely disabled by a software over-ride. */
   8.494 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
   8.495 +        break;
   8.496 +    case e1000_fc_rx_pause:
   8.497 +        /* RX Flow control is enabled and TX Flow control is disabled by a 
   8.498 +         * software over-ride. Since there really isn't a way to advertise 
   8.499 +         * that we are capable of RX Pause ONLY, we will advertise that we
   8.500 +         * support both symmetric and asymmetric RX PAUSE. Later, we will
   8.501 +         *  disable the adapter's ability to send PAUSE frames.
   8.502 +         */
   8.503 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
   8.504 +        break;
   8.505 +    case e1000_fc_tx_pause:
   8.506 +        /* TX Flow control is enabled, and RX Flow control is disabled, by a 
   8.507 +         * software over-ride.
   8.508 +         */
   8.509 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
   8.510 +        break;
   8.511 +    case e1000_fc_full:
   8.512 +        /* Flow control (both RX and TX) is enabled by a software over-ride. */
   8.513 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
   8.514 +        break;
   8.515 +    default:
   8.516 +        DEBUGOUT("Flow control param set incorrectly\n");
   8.517 +        return -E1000_ERR_CONFIG;
   8.518 +        break;
   8.519 +    }
   8.520 +
   8.521 +    /* Since auto-negotiation is enabled, take the link out of reset (the link
   8.522 +     * will be in reset, because we previously reset the chip). This will
   8.523 +     * restart auto-negotiation.  If auto-neogtiation is successful then the
   8.524 +     * link-up status bit will be set and the flow control enable bits (RFCE
   8.525 +     * and TFCE) will be set according to their negotiated value.
   8.526 +     */
   8.527 +    DEBUGOUT("Auto-negotiation enabled\n");
   8.528 +
   8.529 +    E1000_WRITE_REG(hw, TXCW, txcw);
   8.530 +    E1000_WRITE_REG(hw, CTRL, ctrl);
   8.531 +    E1000_WRITE_FLUSH(hw);
   8.532 +
   8.533 +    hw->txcw = txcw;
   8.534 +    msec_delay(1);
   8.535 +
   8.536 +    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
   8.537 +     * indication in the Device Status Register.  Time-out if a link isn't 
   8.538 +     * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
   8.539 +     * less than 500 milliseconds even if the other end is doing it in SW).
   8.540 +     */
   8.541 +    if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
   8.542 +        DEBUGOUT("Looking for Link\n");
   8.543 +        for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
   8.544 +            msec_delay(10);
   8.545 +            status = E1000_READ_REG(hw, STATUS);
   8.546 +            if(status & E1000_STATUS_LU) break;
   8.547 +        }
   8.548 +        if(i == (LINK_UP_TIMEOUT / 10)) {
   8.549 +            /* AutoNeg failed to achieve a link, so we'll call 
   8.550 +             * e1000_check_for_link. This routine will force the link up if we
   8.551 +             * detect a signal. This will allow us to communicate with
   8.552 +             * non-autonegotiating link partners.
   8.553 +             */
   8.554 +            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
   8.555 +            hw->autoneg_failed = 1;
   8.556 +            ret_val = e1000_check_for_link(hw);
   8.557 +            if(ret_val < 0) {
   8.558 +                DEBUGOUT("Error while checking for link\n");
   8.559 +                return ret_val;
   8.560 +            }
   8.561 +            hw->autoneg_failed = 0;
   8.562 +        } else {
   8.563 +            hw->autoneg_failed = 0;
   8.564 +            DEBUGOUT("Valid Link Found\n");
   8.565 +        }
   8.566 +    } else {
   8.567 +        DEBUGOUT("No Signal Detected\n");
   8.568 +    }
   8.569 +    return 0;
   8.570 +}
   8.571 +
   8.572 +/******************************************************************************
   8.573 +* Detects which PHY is present and the speed and duplex
   8.574 +*
   8.575 +* hw - Struct containing variables accessed by shared code
   8.576 +******************************************************************************/
   8.577 +static int32_t 
   8.578 +e1000_setup_copper_link(struct e1000_hw *hw)
   8.579 +{
   8.580 +    uint32_t ctrl;
   8.581 +    int32_t ret_val;
   8.582 +    uint16_t i;
   8.583 +    uint16_t phy_data;
   8.584 +
   8.585 +    DEBUGFUNC("e1000_setup_copper_link");
   8.586 +
   8.587 +    ctrl = E1000_READ_REG(hw, CTRL);
   8.588 +    /* With 82543, we need to force speed and duplex on the MAC equal to what
   8.589 +     * the PHY speed and duplex configuration is. In addition, we need to
   8.590 +     * perform a hardware reset on the PHY to take it out of reset.
   8.591 +     */
   8.592 +    if(hw->mac_type > e1000_82543) {
   8.593 +        ctrl |= E1000_CTRL_SLU;
   8.594 +        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
   8.595 +        E1000_WRITE_REG(hw, CTRL, ctrl);
   8.596 +    } else {
   8.597 +        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
   8.598 +        E1000_WRITE_REG(hw, CTRL, ctrl);
   8.599 +        e1000_phy_hw_reset(hw);
   8.600 +    }
   8.601 +
   8.602 +    /* Make sure we have a valid PHY */
   8.603 +    ret_val = e1000_detect_gig_phy(hw);
   8.604 +    if(ret_val < 0) {
   8.605 +        DEBUGOUT("Error, did not detect valid phy.\n");
   8.606 +        return ret_val;
   8.607 +    }
   8.608 +    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
   8.609 +
   8.610 +    /* Enable CRS on TX. This must be set for half-duplex operation. */
   8.611 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
   8.612 +        DEBUGOUT("PHY Read Error\n");
   8.613 +        return -E1000_ERR_PHY;
   8.614 +    }
   8.615 +    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
   8.616 +
   8.617 +    /* Options:
   8.618 +     *   MDI/MDI-X = 0 (default)
   8.619 +     *   0 - Auto for all speeds
   8.620 +     *   1 - MDI mode
   8.621 +     *   2 - MDI-X mode
   8.622 +     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
   8.623 +     */
   8.624 +    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
   8.625 +
   8.626 +    switch (hw->mdix) {
   8.627 +    case 1:
   8.628 +        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
   8.629 +        break;
   8.630 +    case 2:
   8.631 +        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
   8.632 +        break;
   8.633 +    case 3:
   8.634 +        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
   8.635 +        break;
   8.636 +    case 0:
   8.637 +    default:
   8.638 +        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
   8.639 +        break;
   8.640 +    }
   8.641 +
   8.642 +    /* Options:
   8.643 +     *   disable_polarity_correction = 0 (default)
   8.644 +     *       Automatic Correction for Reversed Cable Polarity
   8.645 +     *   0 - Disabled
   8.646 +     *   1 - Enabled
   8.647 +     */
   8.648 +    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
   8.649 +    if(hw->disable_polarity_correction == 1)
   8.650 +        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
   8.651 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
   8.652 +        DEBUGOUT("PHY Write Error\n");
   8.653 +        return -E1000_ERR_PHY;
   8.654 +    }
   8.655 +
   8.656 +    /* Force TX_CLK in the Extended PHY Specific Control Register
   8.657 +     * to 25MHz clock.
   8.658 +     */
   8.659 +    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
   8.660 +        DEBUGOUT("PHY Read Error\n");
   8.661 +        return -E1000_ERR_PHY;
   8.662 +    }
   8.663 +    phy_data |= M88E1000_EPSCR_TX_CLK_25;
   8.664 +
   8.665 +    if (hw->phy_revision < M88E1011_I_REV_4) {
   8.666 +        /* Configure Master and Slave downshift values */
   8.667 +        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
   8.668 +                      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
   8.669 +        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
   8.670 +                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
   8.671 +        if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
   8.672 +            DEBUGOUT("PHY Write Error\n");
   8.673 +            return -E1000_ERR_PHY;
   8.674 +        }
   8.675 +    }
   8.676 +
   8.677 +    /* SW Reset the PHY so all changes take effect */
   8.678 +    ret_val = e1000_phy_reset(hw);
   8.679 +    if(ret_val < 0) {
   8.680 +        DEBUGOUT("Error Resetting the PHY\n");
   8.681 +        return ret_val;
   8.682 +    }
   8.683 +    
   8.684 +    /* Options:
   8.685 +     *   autoneg = 1 (default)
   8.686 +     *      PHY will advertise value(s) parsed from
   8.687 +     *      autoneg_advertised and fc
   8.688 +     *   autoneg = 0
   8.689 +     *      PHY will be set to 10H, 10F, 100H, or 100F
   8.690 +     *      depending on value parsed from forced_speed_duplex.
   8.691 +     */
   8.692 +
   8.693 +    /* Is autoneg enabled?  This is enabled by default or by software override.
   8.694 +     * If so, call e1000_phy_setup_autoneg routine to parse the
   8.695 +     * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
   8.696 +     * user should have provided a speed/duplex override.  If so, then call
   8.697 +     * e1000_phy_force_speed_duplex to parse and set this up.
   8.698 +     */
   8.699 +    if(hw->autoneg) {
   8.700 +        /* Perform some bounds checking on the hw->autoneg_advertised
   8.701 +         * parameter.  If this variable is zero, then set it to the default.
   8.702 +         */
   8.703 +        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
   8.704 +
   8.705 +        /* If autoneg_advertised is zero, we assume it was not defaulted
   8.706 +         * by the calling code so we set to advertise full capability.
   8.707 +         */
   8.708 +        if(hw->autoneg_advertised == 0)
   8.709 +            hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
   8.710 +
   8.711 +        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
   8.712 +        ret_val = e1000_phy_setup_autoneg(hw);
   8.713 +        if(ret_val < 0) {
   8.714 +            DEBUGOUT("Error Setting up Auto-Negotiation\n");
   8.715 +            return ret_val;
   8.716 +        }
   8.717 +        DEBUGOUT("Restarting Auto-Neg\n");
   8.718 +
   8.719 +        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
   8.720 +         * the Auto Neg Restart bit in the PHY control register.
   8.721 +         */
   8.722 +        if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
   8.723 +            DEBUGOUT("PHY Read Error\n");
   8.724 +            return -E1000_ERR_PHY;
   8.725 +        }
   8.726 +        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
   8.727 +        if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
   8.728 +            DEBUGOUT("PHY Write Error\n");
   8.729 +            return -E1000_ERR_PHY;
   8.730 +        }
   8.731 +
   8.732 +        /* Does the user want to wait for Auto-Neg to complete here, or
   8.733 +         * check at a later time (for example, callback routine).
   8.734 +         */
   8.735 +        if(hw->wait_autoneg_complete) {
   8.736 +            ret_val = e1000_wait_autoneg(hw);
   8.737 +            if(ret_val < 0) {
   8.738 +                DEBUGOUT("Error while waiting for autoneg to complete\n");
   8.739 +                return ret_val;
   8.740 +            }
   8.741 +        }
   8.742 +    } else {
   8.743 +        DEBUGOUT("Forcing speed and duplex\n");
   8.744 +        ret_val = e1000_phy_force_speed_duplex(hw);
   8.745 +        if(ret_val < 0) {
   8.746 +            DEBUGOUT("Error Forcing Speed and Duplex\n");
   8.747 +            return ret_val;
   8.748 +        }
   8.749 +    }
   8.750 +
   8.751 +    /* Check link status. Wait up to 100 microseconds for link to become
   8.752 +     * valid.
   8.753 +     */
   8.754 +    for(i = 0; i < 10; i++) {
   8.755 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
   8.756 +            DEBUGOUT("PHY Read Error\n");
   8.757 +            return -E1000_ERR_PHY;
   8.758 +        }
   8.759 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
   8.760 +            DEBUGOUT("PHY Read Error\n");
   8.761 +            return -E1000_ERR_PHY;
   8.762 +        }
   8.763 +        if(phy_data & MII_SR_LINK_STATUS) {
   8.764 +            /* We have link, so we need to finish the config process:
   8.765 +             *   1) Set up the MAC to the current PHY speed/duplex
   8.766 +             *      if we are on 82543.  If we
   8.767 +             *      are on newer silicon, we only need to configure
   8.768 +             *      collision distance in the Transmit Control Register.
   8.769 +             *   2) Set up flow control on the MAC to that established with
   8.770 +             *      the link partner.
   8.771 +             */
   8.772 +            if(hw->mac_type >= e1000_82544) {
   8.773 +                e1000_config_collision_dist(hw);
   8.774 +            } else {
   8.775 +                ret_val = e1000_config_mac_to_phy(hw);
   8.776 +                if(ret_val < 0) {
   8.777 +                    DEBUGOUT("Error configuring MAC to PHY settings\n");
   8.778 +                    return ret_val;
   8.779 +                  }
   8.780 +            }
   8.781 +            ret_val = e1000_config_fc_after_link_up(hw);
   8.782 +            if(ret_val < 0) {
   8.783 +                DEBUGOUT("Error Configuring Flow Control\n");
   8.784 +                return ret_val;
   8.785 +            }
   8.786 +            DEBUGOUT("Valid link established!!!\n");
   8.787 +            return 0;
   8.788 +        }
   8.789 +        udelay(10);
   8.790 +    }
   8.791 +
   8.792 +    DEBUGOUT("Unable to establish link!!!\n");
   8.793 +    return 0;
   8.794 +}
   8.795 +
   8.796 +/******************************************************************************
   8.797 +* Configures PHY autoneg and flow control advertisement settings
   8.798 +*
   8.799 +* hw - Struct containing variables accessed by shared code
   8.800 +******************************************************************************/
   8.801 +int32_t
   8.802 +e1000_phy_setup_autoneg(struct e1000_hw *hw)
   8.803 +{
   8.804 +    uint16_t mii_autoneg_adv_reg;
   8.805 +    uint16_t mii_1000t_ctrl_reg;
   8.806 +
   8.807 +    DEBUGFUNC("e1000_phy_setup_autoneg");
   8.808 +
   8.809 +    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
   8.810 +    if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
   8.811 +        DEBUGOUT("PHY Read Error\n");
   8.812 +        return -E1000_ERR_PHY;
   8.813 +    }
   8.814 +
   8.815 +    /* Read the MII 1000Base-T Control Register (Address 9). */
   8.816 +    if(e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
   8.817 +        DEBUGOUT("PHY Read Error\n");
   8.818 +        return -E1000_ERR_PHY;
   8.819 +    }
   8.820 +
   8.821 +    /* Need to parse both autoneg_advertised and fc and set up
   8.822 +     * the appropriate PHY registers.  First we will parse for
   8.823 +     * autoneg_advertised software override.  Since we can advertise
   8.824 +     * a plethora of combinations, we need to check each bit
   8.825 +     * individually.
   8.826 +     */
   8.827 +
   8.828 +    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
   8.829 +     * Advertisement Register (Address 4) and the 1000 mb speed bits in
   8.830 +     * the  1000Base-T Control Register (Address 9).
   8.831 +     */
   8.832 +    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
   8.833 +    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
   8.834 +
   8.835 +    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
   8.836 +
   8.837 +    /* Do we want to advertise 10 Mb Half Duplex? */
   8.838 +    if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
   8.839 +        DEBUGOUT("Advertise 10mb Half duplex\n");
   8.840 +        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
   8.841 +    }
   8.842 +
   8.843 +    /* Do we want to advertise 10 Mb Full Duplex? */
   8.844 +    if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
   8.845 +        DEBUGOUT("Advertise 10mb Full duplex\n");
   8.846 +        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
   8.847 +    }
   8.848 +
   8.849 +    /* Do we want to advertise 100 Mb Half Duplex? */
   8.850 +    if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
   8.851 +        DEBUGOUT("Advertise 100mb Half duplex\n");
   8.852 +        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
   8.853 +    }
   8.854 +
   8.855 +    /* Do we want to advertise 100 Mb Full Duplex? */
   8.856 +    if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
   8.857 +        DEBUGOUT("Advertise 100mb Full duplex\n");
   8.858 +        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
   8.859 +    }
   8.860 +
   8.861 +    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
   8.862 +    if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
   8.863 +        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
   8.864 +    }
   8.865 +
   8.866 +    /* Do we want to advertise 1000 Mb Full Duplex? */
   8.867 +    if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
   8.868 +        DEBUGOUT("Advertise 1000mb Full duplex\n");
   8.869 +        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
   8.870 +    }
   8.871 +
   8.872 +    /* Check for a software override of the flow control settings, and
   8.873 +     * setup the PHY advertisement registers accordingly.  If
   8.874 +     * auto-negotiation is enabled, then software will have to set the
   8.875 +     * "PAUSE" bits to the correct value in the Auto-Negotiation
   8.876 +     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
   8.877 +     *
   8.878 +     * The possible values of the "fc" parameter are:
   8.879 +     *      0:  Flow control is completely disabled
   8.880 +     *      1:  Rx flow control is enabled (we can receive pause frames
   8.881 +     *          but not send pause frames).
   8.882 +     *      2:  Tx flow control is enabled (we can send pause frames
   8.883 +     *          but we do not support receiving pause frames).
   8.884 +     *      3:  Both Rx and TX flow control (symmetric) are enabled.
   8.885 +     *  other:  No software override.  The flow control configuration
   8.886 +     *          in the EEPROM is used.
   8.887 +     */
   8.888 +    switch (hw->fc) {
   8.889 +    case e1000_fc_none: /* 0 */
   8.890 +        /* Flow control (RX & TX) is completely disabled by a
   8.891 +         * software over-ride.
   8.892 +         */
   8.893 +        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
   8.894 +        break;
   8.895 +    case e1000_fc_rx_pause: /* 1 */
   8.896 +        /* RX Flow control is enabled, and TX Flow control is
   8.897 +         * disabled, by a software over-ride.
   8.898 +         */
   8.899 +        /* Since there really isn't a way to advertise that we are
   8.900 +         * capable of RX Pause ONLY, we will advertise that we
   8.901 +         * support both symmetric and asymmetric RX PAUSE.  Later
   8.902 +         * (in e1000_config_fc_after_link_up) we will disable the
   8.903 +         *hw's ability to send PAUSE frames.
   8.904 +         */
   8.905 +        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
   8.906 +        break;
   8.907 +    case e1000_fc_tx_pause: /* 2 */
   8.908 +        /* TX Flow control is enabled, and RX Flow control is
   8.909 +         * disabled, by a software over-ride.
   8.910 +         */
   8.911 +        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
   8.912 +        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
   8.913 +        break;
   8.914 +    case e1000_fc_full: /* 3 */
   8.915 +        /* Flow control (both RX and TX) is enabled by a software
   8.916 +         * over-ride.
   8.917 +         */
   8.918 +        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
   8.919 +        break;
   8.920 +    default:
   8.921 +        DEBUGOUT("Flow control param set incorrectly\n");
   8.922 +        return -E1000_ERR_CONFIG;
   8.923 +    }
   8.924 +
   8.925 +    if(e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
   8.926 +        DEBUGOUT("PHY Write Error\n");
   8.927 +        return -E1000_ERR_PHY;
   8.928 +    }
   8.929 +
   8.930 +    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
   8.931 +
   8.932 +    if(e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
   8.933 +        DEBUGOUT("PHY Write Error\n");
   8.934 +        return -E1000_ERR_PHY;
   8.935 +    }
   8.936 +    return 0;
   8.937 +}
   8.938 +
   8.939 +/******************************************************************************
   8.940 +* Force PHY speed and duplex settings to hw->forced_speed_duplex
   8.941 +*
   8.942 +* hw - Struct containing variables accessed by shared code
   8.943 +******************************************************************************/
   8.944 +static int32_t
   8.945 +e1000_phy_force_speed_duplex(struct e1000_hw *hw)
   8.946 +{
   8.947 +    uint32_t ctrl;
   8.948 +    int32_t ret_val;
   8.949 +    uint16_t mii_ctrl_reg;
   8.950 +    uint16_t mii_status_reg;
   8.951 +    uint16_t phy_data;
   8.952 +    uint16_t i;
   8.953 +
   8.954 +    DEBUGFUNC("e1000_phy_force_speed_duplex");
   8.955 +
   8.956 +    /* Turn off Flow control if we are forcing speed and duplex. */
   8.957 +    hw->fc = e1000_fc_none;
   8.958 +
   8.959 +    DEBUGOUT1("hw->fc = %d\n", hw->fc);
   8.960 +
   8.961 +    /* Read the Device Control Register. */
   8.962 +    ctrl = E1000_READ_REG(hw, CTRL);
   8.963 +
   8.964 +    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
   8.965 +    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
   8.966 +    ctrl &= ~(DEVICE_SPEED_MASK);
   8.967 +
   8.968 +    /* Clear the Auto Speed Detect Enable bit. */
   8.969 +    ctrl &= ~E1000_CTRL_ASDE;
   8.970 +
   8.971 +    /* Read the MII Control Register. */
   8.972 +    if(e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
   8.973 +        DEBUGOUT("PHY Read Error\n");
   8.974 +        return -E1000_ERR_PHY;
   8.975 +    }
   8.976 +
   8.977 +    /* We need to disable autoneg in order to force link and duplex. */
   8.978 +
   8.979 +    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
   8.980 +
   8.981 +    /* Are we forcing Full or Half Duplex? */
   8.982 +    if(hw->forced_speed_duplex == e1000_100_full ||
   8.983 +       hw->forced_speed_duplex == e1000_10_full) {
   8.984 +        /* We want to force full duplex so we SET the full duplex bits in the
   8.985 +         * Device and MII Control Registers.
   8.986 +         */
   8.987 +        ctrl |= E1000_CTRL_FD;
   8.988 +        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
   8.989 +        DEBUGOUT("Full Duplex\n");
   8.990 +    } else {
   8.991 +        /* We want to force half duplex so we CLEAR the full duplex bits in
   8.992 +         * the Device and MII Control Registers.
   8.993 +         */
   8.994 +        ctrl &= ~E1000_CTRL_FD;
   8.995 +        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
   8.996 +        DEBUGOUT("Half Duplex\n");
   8.997 +    }
   8.998 +
   8.999 +    /* Are we forcing 100Mbps??? */
  8.1000 +    if(hw->forced_speed_duplex == e1000_100_full ||
  8.1001 +       hw->forced_speed_duplex == e1000_100_half) {
  8.1002 +        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
  8.1003 +        ctrl |= E1000_CTRL_SPD_100;
  8.1004 +        mii_ctrl_reg |= MII_CR_SPEED_100;
  8.1005 +        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
  8.1006 +        DEBUGOUT("Forcing 100mb ");
  8.1007 +    } else {
  8.1008 +        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
  8.1009 +        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
  8.1010 +        mii_ctrl_reg |= MII_CR_SPEED_10;
  8.1011 +        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
  8.1012 +        DEBUGOUT("Forcing 10mb ");
  8.1013 +    }
  8.1014 +
  8.1015 +    e1000_config_collision_dist(hw);
  8.1016 +
  8.1017 +    /* Write the configured values back to the Device Control Reg. */
  8.1018 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1019 +
  8.1020 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
  8.1021 +        DEBUGOUT("PHY Read Error\n");
  8.1022 +        return -E1000_ERR_PHY;
  8.1023 +    }
  8.1024 +
  8.1025 +    /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
  8.1026 +     * forced whenever speed are duplex are forced.
  8.1027 +     */
  8.1028 +    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  8.1029 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
  8.1030 +        DEBUGOUT("PHY Write Error\n");
  8.1031 +        return -E1000_ERR_PHY;
  8.1032 +    }
  8.1033 +    DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
  8.1034 +
  8.1035 +    /* Need to reset the PHY or these changes will be ignored */
  8.1036 +    mii_ctrl_reg |= MII_CR_RESET;
  8.1037 +
  8.1038 +    /* Write back the modified PHY MII control register. */
  8.1039 +    if(e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
  8.1040 +        DEBUGOUT("PHY Write Error\n");
  8.1041 +        return -E1000_ERR_PHY;
  8.1042 +    }
  8.1043 +    udelay(1);
  8.1044 +
  8.1045 +    /* The wait_autoneg_complete flag may be a little misleading here.
  8.1046 +     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
  8.1047 +     * But we do want to delay for a period while forcing only so we
  8.1048 +     * don't generate false No Link messages.  So we will wait here
  8.1049 +     * only if the user has set wait_autoneg_complete to 1, which is
  8.1050 +     * the default.
  8.1051 +     */
  8.1052 +    if(hw->wait_autoneg_complete) {
  8.1053 +        /* We will wait for autoneg to complete. */
  8.1054 +        DEBUGOUT("Waiting for forced speed/duplex link.\n");
  8.1055 +        mii_status_reg = 0;
  8.1056 +
  8.1057 +        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
  8.1058 +        for(i = PHY_FORCE_TIME; i > 0; i--) {
  8.1059 +            /* Read the MII Status Register and wait for Auto-Neg Complete bit
  8.1060 +             * to be set.
  8.1061 +             */
  8.1062 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1063 +                DEBUGOUT("PHY Read Error\n");
  8.1064 +                return -E1000_ERR_PHY;
  8.1065 +            }
  8.1066 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1067 +                DEBUGOUT("PHY Read Error\n");
  8.1068 +                return -E1000_ERR_PHY;
  8.1069 +            }
  8.1070 +            if(mii_status_reg & MII_SR_LINK_STATUS) break;
  8.1071 +            msec_delay(100);
  8.1072 +        }
  8.1073 +        if(i == 0) { /* We didn't get link */
  8.1074 +            /* Reset the DSP and wait again for link. */
  8.1075 +            
  8.1076 +            ret_val = e1000_phy_reset_dsp(hw);
  8.1077 +            if(ret_val < 0) {
  8.1078 +                DEBUGOUT("Error Resetting PHY DSP\n");
  8.1079 +                return ret_val;
  8.1080 +            }
  8.1081 +        }
  8.1082 +        /* This loop will early-out if the link condition has been met.  */
  8.1083 +        for(i = PHY_FORCE_TIME; i > 0; i--) {
  8.1084 +            if(mii_status_reg & MII_SR_LINK_STATUS) break;
  8.1085 +            msec_delay(100);
  8.1086 +            /* Read the MII Status Register and wait for Auto-Neg Complete bit
  8.1087 +             * to be set.
  8.1088 +             */
  8.1089 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1090 +                DEBUGOUT("PHY Read Error\n");
  8.1091 +                return -E1000_ERR_PHY;
  8.1092 +            }
  8.1093 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1094 +                DEBUGOUT("PHY Read Error\n");
  8.1095 +                return -E1000_ERR_PHY;
  8.1096 +            }
  8.1097 +        }
  8.1098 +    }
  8.1099 +    
  8.1100 +    /* Because we reset the PHY above, we need to re-force TX_CLK in the
  8.1101 +     * Extended PHY Specific Control Register to 25MHz clock.  This value
  8.1102 +     * defaults back to a 2.5MHz clock when the PHY is reset.
  8.1103 +     */
  8.1104 +    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
  8.1105 +        DEBUGOUT("PHY Read Error\n");
  8.1106 +        return -E1000_ERR_PHY;
  8.1107 +    }
  8.1108 +    phy_data |= M88E1000_EPSCR_TX_CLK_25;
  8.1109 +    if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
  8.1110 +        DEBUGOUT("PHY Write Error\n");
  8.1111 +        return -E1000_ERR_PHY;
  8.1112 +    }
  8.1113 +
  8.1114 +    /* In addition, because of the s/w reset above, we need to enable CRS on
  8.1115 +     * TX.  This must be set for both full and half duplex operation.
  8.1116 +     */
  8.1117 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
  8.1118 +        DEBUGOUT("PHY Read Error\n");
  8.1119 +        return -E1000_ERR_PHY;
  8.1120 +    }
  8.1121 +    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  8.1122 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
  8.1123 +        DEBUGOUT("PHY Write Error\n");
  8.1124 +        return -E1000_ERR_PHY;
  8.1125 +    }
  8.1126 +    return 0;
  8.1127 +}
  8.1128 +
  8.1129 +/******************************************************************************
  8.1130 +* Sets the collision distance in the Transmit Control register
  8.1131 +*
  8.1132 +* hw - Struct containing variables accessed by shared code
  8.1133 +*
  8.1134 +* Link should have been established previously. Reads the speed and duplex
  8.1135 +* information from the Device Status register.
  8.1136 +******************************************************************************/
  8.1137 +void
  8.1138 +e1000_config_collision_dist(struct e1000_hw *hw)
  8.1139 +{
  8.1140 +    uint32_t tctl;
  8.1141 +
  8.1142 +    tctl = E1000_READ_REG(hw, TCTL);
  8.1143 +
  8.1144 +    tctl &= ~E1000_TCTL_COLD;
  8.1145 +    tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
  8.1146 +
  8.1147 +    E1000_WRITE_REG(hw, TCTL, tctl);
  8.1148 +    E1000_WRITE_FLUSH(hw);
  8.1149 +}
  8.1150 +
  8.1151 +/******************************************************************************
  8.1152 +* Sets MAC speed and duplex settings to reflect the those in the PHY
  8.1153 +*
  8.1154 +* hw - Struct containing variables accessed by shared code
  8.1155 +* mii_reg - data to write to the MII control register
  8.1156 +*
  8.1157 +* The contents of the PHY register containing the needed information need to
  8.1158 +* be passed in.
  8.1159 +******************************************************************************/
  8.1160 +static int32_t
  8.1161 +e1000_config_mac_to_phy(struct e1000_hw *hw)
  8.1162 +{
  8.1163 +    uint32_t ctrl;
  8.1164 +    uint16_t phy_data;
  8.1165 +
  8.1166 +    DEBUGFUNC("e1000_config_mac_to_phy");
  8.1167 +
  8.1168 +    /* Read the Device Control Register and set the bits to Force Speed
  8.1169 +     * and Duplex.
  8.1170 +     */
  8.1171 +    ctrl = E1000_READ_REG(hw, CTRL);
  8.1172 +    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  8.1173 +    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
  8.1174 +
  8.1175 +    /* Set up duplex in the Device Control and Transmit Control
  8.1176 +     * registers depending on negotiated values.
  8.1177 +     */
  8.1178 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  8.1179 +        DEBUGOUT("PHY Read Error\n");
  8.1180 +        return -E1000_ERR_PHY;
  8.1181 +    }
  8.1182 +    if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
  8.1183 +    else ctrl &= ~E1000_CTRL_FD;
  8.1184 +
  8.1185 +    e1000_config_collision_dist(hw);
  8.1186 +
  8.1187 +    /* Set up speed in the Device Control register depending on
  8.1188 +     * negotiated values.
  8.1189 +     */
  8.1190 +    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  8.1191 +        ctrl |= E1000_CTRL_SPD_1000;
  8.1192 +    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  8.1193 +        ctrl |= E1000_CTRL_SPD_100;
  8.1194 +    /* Write the configured values back to the Device Control Reg. */
  8.1195 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1196 +    return 0;
  8.1197 +}
  8.1198 +
  8.1199 +/******************************************************************************
  8.1200 + * Forces the MAC's flow control settings.
  8.1201 + * 
  8.1202 + * hw - Struct containing variables accessed by shared code
  8.1203 + *
  8.1204 + * Sets the TFCE and RFCE bits in the device control register to reflect
  8.1205 + * the adapter settings. TFCE and RFCE need to be explicitly set by
  8.1206 + * software when a Copper PHY is used because autonegotiation is managed
  8.1207 + * by the PHY rather than the MAC. Software must also configure these
  8.1208 + * bits when link is forced on a fiber connection.
  8.1209 + *****************************************************************************/
  8.1210 +static int32_t
  8.1211 +e1000_force_mac_fc(struct e1000_hw *hw)
  8.1212 +{
  8.1213 +    uint32_t ctrl;
  8.1214 +
  8.1215 +    DEBUGFUNC("e1000_force_mac_fc");
  8.1216 +
  8.1217 +    /* Get the current configuration of the Device Control Register */
  8.1218 +    ctrl = E1000_READ_REG(hw, CTRL);
  8.1219 +
  8.1220 +    /* Because we didn't get link via the internal auto-negotiation
  8.1221 +     * mechanism (we either forced link or we got link via PHY
  8.1222 +     * auto-neg), we have to manually enable/disable transmit an
  8.1223 +     * receive flow control.
  8.1224 +     *
  8.1225 +     * The "Case" statement below enables/disable flow control
  8.1226 +     * according to the "hw->fc" parameter.
  8.1227 +     *
  8.1228 +     * The possible values of the "fc" parameter are:
  8.1229 +     *      0:  Flow control is completely disabled
  8.1230 +     *      1:  Rx flow control is enabled (we can receive pause
  8.1231 +     *          frames but not send pause frames).
  8.1232 +     *      2:  Tx flow control is enabled (we can send pause frames
  8.1233 +     *          frames but we do not receive pause frames).
  8.1234 +     *      3:  Both Rx and TX flow control (symmetric) is enabled.
  8.1235 +     *  other:  No other values should be possible at this point.
  8.1236 +     */
  8.1237 +
  8.1238 +    switch (hw->fc) {
  8.1239 +    case e1000_fc_none:
  8.1240 +        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  8.1241 +        break;
  8.1242 +    case e1000_fc_rx_pause:
  8.1243 +        ctrl &= (~E1000_CTRL_TFCE);
  8.1244 +        ctrl |= E1000_CTRL_RFCE;
  8.1245 +        break;
  8.1246 +    case e1000_fc_tx_pause:
  8.1247 +        ctrl &= (~E1000_CTRL_RFCE);
  8.1248 +        ctrl |= E1000_CTRL_TFCE;
  8.1249 +        break;
  8.1250 +    case e1000_fc_full:
  8.1251 +        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  8.1252 +        break;
  8.1253 +    default:
  8.1254 +        DEBUGOUT("Flow control param set incorrectly\n");
  8.1255 +        return -E1000_ERR_CONFIG;
  8.1256 +    }
  8.1257 +
  8.1258 +    /* Disable TX Flow Control for 82542 (rev 2.0) */
  8.1259 +    if(hw->mac_type == e1000_82542_rev2_0)
  8.1260 +        ctrl &= (~E1000_CTRL_TFCE);
  8.1261 +
  8.1262 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1263 +    return 0;
  8.1264 +}
  8.1265 +
  8.1266 +/******************************************************************************
  8.1267 + * Configures flow control settings after link is established
  8.1268 + * 
  8.1269 + * hw - Struct containing variables accessed by shared code
  8.1270 + *
  8.1271 + * Should be called immediately after a valid link has been established.
  8.1272 + * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  8.1273 + * and autonegotiation is enabled, the MAC flow control settings will be set
  8.1274 + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  8.1275 + * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  8.1276 + *****************************************************************************/
  8.1277 +int32_t
  8.1278 +e1000_config_fc_after_link_up(struct e1000_hw *hw)
  8.1279 +{
  8.1280 +    int32_t ret_val;
  8.1281 +    uint16_t mii_status_reg;
  8.1282 +    uint16_t mii_nway_adv_reg;
  8.1283 +    uint16_t mii_nway_lp_ability_reg;
  8.1284 +    uint16_t speed;
  8.1285 +    uint16_t duplex;
  8.1286 +
  8.1287 +    DEBUGFUNC("e1000_config_fc_after_link_up");
  8.1288 +
  8.1289 +    /* Check for the case where we have fiber media and auto-neg failed
  8.1290 +     * so we had to force link.  In this case, we need to force the
  8.1291 +     * configuration of the MAC to match the "fc" parameter.
  8.1292 +     */
  8.1293 +    if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
  8.1294 +       ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
  8.1295 +        ret_val = e1000_force_mac_fc(hw);
  8.1296 +        if(ret_val < 0) {
  8.1297 +            DEBUGOUT("Error forcing flow control settings\n");
  8.1298 +            return ret_val;
  8.1299 +        }
  8.1300 +    }
  8.1301 +
  8.1302 +    /* Check for the case where we have copper media and auto-neg is
  8.1303 +     * enabled.  In this case, we need to check and see if Auto-Neg
  8.1304 +     * has completed, and if so, how the PHY and link partner has
  8.1305 +     * flow control configured.
  8.1306 +     */
  8.1307 +    if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
  8.1308 +        /* Read the MII Status Register and check to see if AutoNeg
  8.1309 +         * has completed.  We read this twice because this reg has
  8.1310 +         * some "sticky" (latched) bits.
  8.1311 +         */
  8.1312 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1313 +            DEBUGOUT("PHY Read Error \n");
  8.1314 +            return -E1000_ERR_PHY;
  8.1315 +        }
  8.1316 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  8.1317 +            DEBUGOUT("PHY Read Error \n");
  8.1318 +            return -E1000_ERR_PHY;
  8.1319 +        }
  8.1320 +
  8.1321 +        if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  8.1322 +            /* The AutoNeg process has completed, so we now need to
  8.1323 +             * read both the Auto Negotiation Advertisement Register
  8.1324 +             * (Address 4) and the Auto_Negotiation Base Page Ability
  8.1325 +             * Register (Address 5) to determine how flow control was
  8.1326 +             * negotiated.
  8.1327 +             */
  8.1328 +            if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  8.1329 +                DEBUGOUT("PHY Read Error\n");
  8.1330 +                return -E1000_ERR_PHY;
  8.1331 +            }
  8.1332 +            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
  8.1333 +                DEBUGOUT("PHY Read Error\n");
  8.1334 +                return -E1000_ERR_PHY;
  8.1335 +            }
  8.1336 +
  8.1337 +            /* Two bits in the Auto Negotiation Advertisement Register
  8.1338 +             * (Address 4) and two bits in the Auto Negotiation Base
  8.1339 +             * Page Ability Register (Address 5) determine flow control
  8.1340 +             * for both the PHY and the link partner.  The following
  8.1341 +             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  8.1342 +             * 1999, describes these PAUSE resolution bits and how flow
  8.1343 +             * control is determined based upon these settings.
  8.1344 +             * NOTE:  DC = Don't Care
  8.1345 +             *
  8.1346 +             *   LOCAL DEVICE  |   LINK PARTNER
  8.1347 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  8.1348 +             *-------|---------|-------|---------|--------------------
  8.1349 +             *   0   |    0    |  DC   |   DC    | e1000_fc_none
  8.1350 +             *   0   |    1    |   0   |   DC    | e1000_fc_none
  8.1351 +             *   0   |    1    |   1   |    0    | e1000_fc_none
  8.1352 +             *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
  8.1353 +             *   1   |    0    |   0   |   DC    | e1000_fc_none
  8.1354 +             *   1   |   DC    |   1   |   DC    | e1000_fc_full
  8.1355 +             *   1   |    1    |   0   |    0    | e1000_fc_none
  8.1356 +             *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
  8.1357 +             *
  8.1358 +             */
  8.1359 +            /* Are both PAUSE bits set to 1?  If so, this implies
  8.1360 +             * Symmetric Flow Control is enabled at both ends.  The
  8.1361 +             * ASM_DIR bits are irrelevant per the spec.
  8.1362 +             *
  8.1363 +             * For Symmetric Flow Control:
  8.1364 +             *
  8.1365 +             *   LOCAL DEVICE  |   LINK PARTNER
  8.1366 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  8.1367 +             *-------|---------|-------|---------|--------------------
  8.1368 +             *   1   |   DC    |   1   |   DC    | e1000_fc_full
  8.1369 +             *
  8.1370 +             */
  8.1371 +            if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  8.1372 +               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  8.1373 +                /* Now we need to check if the user selected RX ONLY
  8.1374 +                 * of pause frames.  In this case, we had to advertise
  8.1375 +                 * FULL flow control because we could not advertise RX
  8.1376 +                 * ONLY. Hence, we must now check to see if we need to
  8.1377 +                 * turn OFF  the TRANSMISSION of PAUSE frames.
  8.1378 +                 */
  8.1379 +                if(hw->original_fc == e1000_fc_full) {
  8.1380 +                    hw->fc = e1000_fc_full;
  8.1381 +                    DEBUGOUT("Flow Control = FULL.\r\n");
  8.1382 +                } else {
  8.1383 +                    hw->fc = e1000_fc_rx_pause;
  8.1384 +                    DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
  8.1385 +                }
  8.1386 +            }
  8.1387 +            /* For receiving PAUSE frames ONLY.
  8.1388 +             *
  8.1389 +             *   LOCAL DEVICE  |   LINK PARTNER
  8.1390 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  8.1391 +             *-------|---------|-------|---------|--------------------
  8.1392 +             *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
  8.1393 +             *
  8.1394 +             */
  8.1395 +            else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  8.1396 +                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  8.1397 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  8.1398 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  8.1399 +                hw->fc = e1000_fc_tx_pause;
  8.1400 +                DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
  8.1401 +            }
  8.1402 +            /* For transmitting PAUSE frames ONLY.
  8.1403 +             *
  8.1404 +             *   LOCAL DEVICE  |   LINK PARTNER
  8.1405 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  8.1406 +             *-------|---------|-------|---------|--------------------
  8.1407 +             *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
  8.1408 +             *
  8.1409 +             */
  8.1410 +            else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  8.1411 +                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  8.1412 +                    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  8.1413 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
  8.1414 +                hw->fc = e1000_fc_rx_pause;
  8.1415 +                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
  8.1416 +            }
  8.1417 +            /* Per the IEEE spec, at this point flow control should be
  8.1418 +             * disabled.  However, we want to consider that we could
  8.1419 +             * be connected to a legacy switch that doesn't advertise
  8.1420 +             * desired flow control, but can be forced on the link
  8.1421 +             * partner.  So if we advertised no flow control, that is
  8.1422 +             * what we will resolve to.  If we advertised some kind of
  8.1423 +             * receive capability (Rx Pause Only or Full Flow Control)
  8.1424 +             * and the link partner advertised none, we will configure
  8.1425 +             * ourselves to enable Rx Flow Control only.  We can do
  8.1426 +             * this safely for two reasons:  If the link partner really
  8.1427 +             * didn't want flow control enabled, and we enable Rx, no
  8.1428 +             * harm done since we won't be receiving any PAUSE frames
  8.1429 +             * anyway.  If the intent on the link partner was to have
  8.1430 +             * flow control enabled, then by us enabling RX only, we
  8.1431 +             * can at least receive pause frames and process them.
  8.1432 +             * This is a good idea because in most cases, since we are
  8.1433 +             * predominantly a server NIC, more times than not we will
  8.1434 +             * be asked to delay transmission of packets than asking
  8.1435 +             * our link partner to pause transmission of frames.
  8.1436 +             */
  8.1437 +            else if(hw->original_fc == e1000_fc_none ||
  8.1438 +                    hw->original_fc == e1000_fc_tx_pause) {
  8.1439 +                hw->fc = e1000_fc_none;
  8.1440 +                DEBUGOUT("Flow Control = NONE.\r\n");
  8.1441 +            } else {
  8.1442 +                hw->fc = e1000_fc_rx_pause;
  8.1443 +                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
  8.1444 +            }
  8.1445 +
  8.1446 +            /* Now we need to do one last check...  If we auto-
  8.1447 +             * negotiated to HALF DUPLEX, flow control should not be
  8.1448 +             * enabled per IEEE 802.3 spec.
  8.1449 +             */
  8.1450 +            e1000_get_speed_and_duplex(hw, &speed, &duplex);
  8.1451 +
  8.1452 +            if(duplex == HALF_DUPLEX)
  8.1453 +                hw->fc = e1000_fc_none;
  8.1454 +
  8.1455 +            /* Now we call a subroutine to actually force the MAC
  8.1456 +             * controller to use the correct flow control settings.
  8.1457 +             */
  8.1458 +            ret_val = e1000_force_mac_fc(hw);
  8.1459 +            if(ret_val < 0) {
  8.1460 +                DEBUGOUT("Error forcing flow control settings\n");
  8.1461 +                return ret_val;
  8.1462 +             }
  8.1463 +        } else {
  8.1464 +            DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
  8.1465 +        }
  8.1466 +    }
  8.1467 +    return 0;
  8.1468 +}
  8.1469 +
  8.1470 +/******************************************************************************
  8.1471 + * Checks to see if the link status of the hardware has changed.
  8.1472 + *
  8.1473 + * hw - Struct containing variables accessed by shared code
  8.1474 + *
  8.1475 + * Called by any function that needs to check the link status of the adapter.
  8.1476 + *****************************************************************************/
  8.1477 +int32_t
  8.1478 +e1000_check_for_link(struct e1000_hw *hw)
  8.1479 +{
  8.1480 +    uint32_t rxcw;
  8.1481 +    uint32_t ctrl;
  8.1482 +    uint32_t status;
  8.1483 +    uint32_t rctl;
  8.1484 +    uint32_t signal;
  8.1485 +    int32_t ret_val;
  8.1486 +    uint16_t phy_data;
  8.1487 +    uint16_t lp_capability;
  8.1488 +
  8.1489 +    DEBUGFUNC("e1000_check_for_link");
  8.1490 +    
  8.1491 +    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
  8.1492 +     * set when the optics detect a signal. On older adapters, it will be 
  8.1493 +     * cleared when there is a signal
  8.1494 +     */
  8.1495 +    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
  8.1496 +    else signal = 0;
  8.1497 +
  8.1498 +    ctrl = E1000_READ_REG(hw, CTRL);
  8.1499 +    status = E1000_READ_REG(hw, STATUS);
  8.1500 +    rxcw = E1000_READ_REG(hw, RXCW);
  8.1501 +
  8.1502 +    /* If we have a copper PHY then we only want to go out to the PHY
  8.1503 +     * registers to see if Auto-Neg has completed and/or if our link
  8.1504 +     * status has changed.  The get_link_status flag will be set if we
  8.1505 +     * receive a Link Status Change interrupt or we have Rx Sequence
  8.1506 +     * Errors.
  8.1507 +     */
  8.1508 +    if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  8.1509 +        /* First we want to see if the MII Status Register reports
  8.1510 +         * link.  If so, then we want to get the current speed/duplex
  8.1511 +         * of the PHY.
  8.1512 +         * Read the register twice since the link bit is sticky.
  8.1513 +         */
  8.1514 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  8.1515 +            DEBUGOUT("PHY Read Error\n");
  8.1516 +            return -E1000_ERR_PHY;
  8.1517 +        }
  8.1518 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  8.1519 +            DEBUGOUT("PHY Read Error\n");
  8.1520 +            return -E1000_ERR_PHY;
  8.1521 +        }
  8.1522 +
  8.1523 +        if(phy_data & MII_SR_LINK_STATUS) {
  8.1524 +            hw->get_link_status = FALSE;
  8.1525 +        } else {
  8.1526 +            /* No link detected */
  8.1527 +            return 0;
  8.1528 +        }
  8.1529 +
  8.1530 +        /* If we are forcing speed/duplex, then we simply return since
  8.1531 +         * we have already determined whether we have link or not.
  8.1532 +         */
  8.1533 +        if(!hw->autoneg) return -E1000_ERR_CONFIG;
  8.1534 +
  8.1535 +        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
  8.1536 +         * have Si on board that is 82544 or newer, Auto
  8.1537 +         * Speed Detection takes care of MAC speed/duplex
  8.1538 +         * configuration.  So we only need to configure Collision
  8.1539 +         * Distance in the MAC.  Otherwise, we need to force
  8.1540 +         * speed/duplex on the MAC to the current PHY speed/duplex
  8.1541 +         * settings.
  8.1542 +         */
  8.1543 +        if(hw->mac_type >= e1000_82544)
  8.1544 +            e1000_config_collision_dist(hw);
  8.1545 +        else {
  8.1546 +            ret_val = e1000_config_mac_to_phy(hw);
  8.1547 +            if(ret_val < 0) {
  8.1548 +                DEBUGOUT("Error configuring MAC to PHY settings\n");
  8.1549 +                return ret_val;
  8.1550 +            }
  8.1551 +        }
  8.1552 +
  8.1553 +        /* Configure Flow Control now that Auto-Neg has completed. First, we 
  8.1554 +         * need to restore the desired flow control settings because we may
  8.1555 +         * have had to re-autoneg with a different link partner.
  8.1556 +         */
  8.1557 +        ret_val = e1000_config_fc_after_link_up(hw);
  8.1558 +        if(ret_val < 0) {
  8.1559 +            DEBUGOUT("Error configuring flow control\n");
  8.1560 +            return ret_val;
  8.1561 +        }
  8.1562 +
  8.1563 +        /* At this point we know that we are on copper and we have
  8.1564 +         * auto-negotiated link.  These are conditions for checking the link
  8.1565 +         * parter capability register.  We use the link partner capability to
  8.1566 +         * determine if TBI Compatibility needs to be turned on or off.  If
  8.1567 +         * the link partner advertises any speed in addition to Gigabit, then
  8.1568 +         * we assume that they are GMII-based, and TBI compatibility is not
  8.1569 +         * needed. If no other speeds are advertised, we assume the link
  8.1570 +         * partner is TBI-based, and we turn on TBI Compatibility.
  8.1571 +         */
  8.1572 +        if(hw->tbi_compatibility_en) {
  8.1573 +            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  8.1574 +                DEBUGOUT("PHY Read Error\n");
  8.1575 +                return -E1000_ERR_PHY;
  8.1576 +            }
  8.1577 +            if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  8.1578 +                                NWAY_LPAR_10T_FD_CAPS |
  8.1579 +                                NWAY_LPAR_100TX_HD_CAPS |
  8.1580 +                                NWAY_LPAR_100TX_FD_CAPS |
  8.1581 +                                NWAY_LPAR_100T4_CAPS)) {
  8.1582 +                /* If our link partner advertises anything in addition to 
  8.1583 +                 * gigabit, we do not need to enable TBI compatibility.
  8.1584 +                 */
  8.1585 +                if(hw->tbi_compatibility_on) {
  8.1586 +                    /* If we previously were in the mode, turn it off. */
  8.1587 +                    rctl = E1000_READ_REG(hw, RCTL);
  8.1588 +                    rctl &= ~E1000_RCTL_SBP;
  8.1589 +                    E1000_WRITE_REG(hw, RCTL, rctl);
  8.1590 +                    hw->tbi_compatibility_on = FALSE;
  8.1591 +                }
  8.1592 +            } else {
  8.1593 +                /* If TBI compatibility is was previously off, turn it on. For
  8.1594 +                 * compatibility with a TBI link partner, we will store bad
  8.1595 +                 * packets. Some frames have an additional byte on the end and
  8.1596 +                 * will look like CRC errors to to the hardware.
  8.1597 +                 */
  8.1598 +                if(!hw->tbi_compatibility_on) {
  8.1599 +                    hw->tbi_compatibility_on = TRUE;
  8.1600 +                    rctl = E1000_READ_REG(hw, RCTL);
  8.1601 +                    rctl |= E1000_RCTL_SBP;
  8.1602 +                    E1000_WRITE_REG(hw, RCTL, rctl);
  8.1603 +                }
  8.1604 +            }
  8.1605 +        }
  8.1606 +    }
  8.1607 +    /* If we don't have link (auto-negotiation failed or link partner cannot
  8.1608 +     * auto-negotiate), the cable is plugged in (we have signal), and our
  8.1609 +     * link partner is not trying to auto-negotiate with us (we are receiving
  8.1610 +     * idles or data), we need to force link up. We also need to give
  8.1611 +     * auto-negotiation time to complete, in case the cable was just plugged
  8.1612 +     * in. The autoneg_failed flag does this.
  8.1613 +     */
  8.1614 +    else if((hw->media_type == e1000_media_type_fiber) &&
  8.1615 +            (!(status & E1000_STATUS_LU)) &&
  8.1616 +            ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  8.1617 +            (!(rxcw & E1000_RXCW_C))) {
  8.1618 +        if(hw->autoneg_failed == 0) {
  8.1619 +            hw->autoneg_failed = 1;
  8.1620 +            return 0;
  8.1621 +        }
  8.1622 +        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  8.1623 +
  8.1624 +        /* Disable auto-negotiation in the TXCW register */
  8.1625 +        E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  8.1626 +
  8.1627 +        /* Force link-up and also force full-duplex. */
  8.1628 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.1629 +        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  8.1630 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1631 +
  8.1632 +        /* Configure Flow Control after forcing link up. */
  8.1633 +        ret_val = e1000_config_fc_after_link_up(hw);
  8.1634 +        if(ret_val < 0) {
  8.1635 +            DEBUGOUT("Error configuring flow control\n");
  8.1636 +            return ret_val;
  8.1637 +        }
  8.1638 +    }
  8.1639 +    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  8.1640 +     * auto-negotiation in the TXCW register and disable forced link in the
  8.1641 +     * Device Control register in an attempt to auto-negotiate with our link
  8.1642 +     * partner.
  8.1643 +     */
  8.1644 +    else if((hw->media_type == e1000_media_type_fiber) &&
  8.1645 +              (ctrl & E1000_CTRL_SLU) &&
  8.1646 +              (rxcw & E1000_RXCW_C)) {
  8.1647 +        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  8.1648 +        E1000_WRITE_REG(hw, TXCW, hw->txcw);
  8.1649 +        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  8.1650 +    }
  8.1651 +    return 0;
  8.1652 +}
  8.1653 +
  8.1654 +/******************************************************************************
  8.1655 + * Detects the current speed and duplex settings of the hardware.
  8.1656 + *
  8.1657 + * hw - Struct containing variables accessed by shared code
  8.1658 + * speed - Speed of the connection
  8.1659 + * duplex - Duplex setting of the connection
  8.1660 + *****************************************************************************/
  8.1661 +void
  8.1662 +e1000_get_speed_and_duplex(struct e1000_hw *hw,
  8.1663 +                           uint16_t *speed,
  8.1664 +                           uint16_t *duplex)
  8.1665 +{
  8.1666 +    uint32_t status;
  8.1667 +
  8.1668 +    DEBUGFUNC("e1000_get_speed_and_duplex");
  8.1669 +
  8.1670 +    if(hw->mac_type >= e1000_82543) {
  8.1671 +        status = E1000_READ_REG(hw, STATUS);
  8.1672 +        if(status & E1000_STATUS_SPEED_1000) {
  8.1673 +            *speed = SPEED_1000;
  8.1674 +            DEBUGOUT("1000 Mbs, ");
  8.1675 +        } else if(status & E1000_STATUS_SPEED_100) {
  8.1676 +            *speed = SPEED_100;
  8.1677 +            DEBUGOUT("100 Mbs, ");
  8.1678 +        } else {
  8.1679 +            *speed = SPEED_10;
  8.1680 +            DEBUGOUT("10 Mbs, ");
  8.1681 +        }
  8.1682 +
  8.1683 +        if(status & E1000_STATUS_FD) {
  8.1684 +            *duplex = FULL_DUPLEX;
  8.1685 +            DEBUGOUT("Full Duplex\r\n");
  8.1686 +        } else {
  8.1687 +            *duplex = HALF_DUPLEX;
  8.1688 +            DEBUGOUT(" Half Duplex\r\n");
  8.1689 +        }
  8.1690 +    } else {
  8.1691 +        DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  8.1692 +        *speed = SPEED_1000;
  8.1693 +        *duplex = FULL_DUPLEX;
  8.1694 +    }
  8.1695 +}
  8.1696 +
  8.1697 +/******************************************************************************
  8.1698 +* Blocks until autoneg completes or times out (~4.5 seconds)
  8.1699 +*
  8.1700 +* hw - Struct containing variables accessed by shared code
  8.1701 +******************************************************************************/
  8.1702 +int32_t
  8.1703 +e1000_wait_autoneg(struct e1000_hw *hw)
  8.1704 +{
  8.1705 +    uint16_t i;
  8.1706 +    uint16_t phy_data;
  8.1707 +
  8.1708 +    DEBUGFUNC("e1000_wait_autoneg");
  8.1709 +    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  8.1710 +
  8.1711 +    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
  8.1712 +    for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  8.1713 +        /* Read the MII Status Register and wait for Auto-Neg
  8.1714 +         * Complete bit to be set.
  8.1715 +         */
  8.1716 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  8.1717 +            DEBUGOUT("PHY Read Error\n");
  8.1718 +            return -E1000_ERR_PHY;
  8.1719 +        }
  8.1720 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  8.1721 +            DEBUGOUT("PHY Read Error\n");
  8.1722 +            return -E1000_ERR_PHY;
  8.1723 +        }
  8.1724 +        if(phy_data & MII_SR_AUTONEG_COMPLETE) {
  8.1725 +            return 0;
  8.1726 +        }
  8.1727 +        msec_delay(100);
  8.1728 +    }
  8.1729 +    return 0;
  8.1730 +}
  8.1731 +
  8.1732 +/******************************************************************************
  8.1733 +* Raises the Management Data Clock
  8.1734 +*
  8.1735 +* hw - Struct containing variables accessed by shared code
  8.1736 +* ctrl - Device control register's current value
  8.1737 +******************************************************************************/
  8.1738 +static void
  8.1739 +e1000_raise_mdi_clk(struct e1000_hw *hw,
  8.1740 +                    uint32_t *ctrl)
  8.1741 +{
  8.1742 +    /* Raise the clock input to the Management Data Clock (by setting the MDC
  8.1743 +     * bit), and then delay 2 microseconds.
  8.1744 +     */
  8.1745 +    E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  8.1746 +    E1000_WRITE_FLUSH(hw);
  8.1747 +    udelay(2);
  8.1748 +}
  8.1749 +
  8.1750 +/******************************************************************************
  8.1751 +* Lowers the Management Data Clock
  8.1752 +*
  8.1753 +* hw - Struct containing variables accessed by shared code
  8.1754 +* ctrl - Device control register's current value
  8.1755 +******************************************************************************/
  8.1756 +static void
  8.1757 +e1000_lower_mdi_clk(struct e1000_hw *hw,
  8.1758 +                    uint32_t *ctrl)
  8.1759 +{
  8.1760 +    /* Lower the clock input to the Management Data Clock (by clearing the MDC
  8.1761 +     * bit), and then delay 2 microseconds.
  8.1762 +     */
  8.1763 +    E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  8.1764 +    E1000_WRITE_FLUSH(hw);
  8.1765 +    udelay(2);
  8.1766 +}
  8.1767 +
  8.1768 +/******************************************************************************
  8.1769 +* Shifts data bits out to the PHY
  8.1770 +*
  8.1771 +* hw - Struct containing variables accessed by shared code
  8.1772 +* data - Data to send out to the PHY
  8.1773 +* count - Number of bits to shift out
  8.1774 +*
  8.1775 +* Bits are shifted out in MSB to LSB order.
  8.1776 +******************************************************************************/
  8.1777 +static void
  8.1778 +e1000_shift_out_mdi_bits(struct e1000_hw *hw,
  8.1779 +                         uint32_t data,
  8.1780 +                         uint16_t count)
  8.1781 +{
  8.1782 +    uint32_t ctrl;
  8.1783 +    uint32_t mask;
  8.1784 +
  8.1785 +    /* We need to shift "count" number of bits out to the PHY. So, the value
  8.1786 +     * in the "data" parameter will be shifted out to the PHY one bit at a 
  8.1787 +     * time. In order to do this, "data" must be broken down into bits.
  8.1788 +     */
  8.1789 +    mask = 0x01;
  8.1790 +    mask <<= (count - 1);
  8.1791 +
  8.1792 +    ctrl = E1000_READ_REG(hw, CTRL);
  8.1793 +
  8.1794 +    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  8.1795 +    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  8.1796 +
  8.1797 +    while(mask) {
  8.1798 +        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  8.1799 +         * then raising and lowering the Management Data Clock. A "0" is
  8.1800 +         * shifted out to the PHY by setting the MDIO bit to "0" and then
  8.1801 +         * raising and lowering the clock.
  8.1802 +         */
  8.1803 +        if(data & mask) ctrl |= E1000_CTRL_MDIO;
  8.1804 +        else ctrl &= ~E1000_CTRL_MDIO;
  8.1805 +
  8.1806 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1807 +        E1000_WRITE_FLUSH(hw);
  8.1808 +
  8.1809 +        udelay(2);
  8.1810 +
  8.1811 +        e1000_raise_mdi_clk(hw, &ctrl);
  8.1812 +        e1000_lower_mdi_clk(hw, &ctrl);
  8.1813 +
  8.1814 +        mask = mask >> 1;
  8.1815 +    }
  8.1816 +}
  8.1817 +
  8.1818 +/******************************************************************************
  8.1819 +* Shifts data bits in from the PHY
  8.1820 +*
  8.1821 +* hw - Struct containing variables accessed by shared code
  8.1822 +*
  8.1823 +* Bits are shifted in in MSB to LSB order. 
  8.1824 +******************************************************************************/
  8.1825 +static uint16_t
  8.1826 +e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  8.1827 +{
  8.1828 +    uint32_t ctrl;
  8.1829 +    uint16_t data = 0;
  8.1830 +    uint8_t i;
  8.1831 +
  8.1832 +    /* In order to read a register from the PHY, we need to shift in a total
  8.1833 +     * of 18 bits from the PHY. The first two bit (turnaround) times are used
  8.1834 +     * to avoid contention on the MDIO pin when a read operation is performed.
  8.1835 +     * These two bits are ignored by us and thrown away. Bits are "shifted in"
  8.1836 +     * by raising the input to the Management Data Clock (setting the MDC bit),
  8.1837 +     * and then reading the value of the MDIO bit.
  8.1838 +     */ 
  8.1839 +    ctrl = E1000_READ_REG(hw, CTRL);
  8.1840 +
  8.1841 +    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  8.1842 +    ctrl &= ~E1000_CTRL_MDIO_DIR;
  8.1843 +    ctrl &= ~E1000_CTRL_MDIO;
  8.1844 +
  8.1845 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  8.1846 +    E1000_WRITE_FLUSH(hw);
  8.1847 +
  8.1848 +    /* Raise and Lower the clock before reading in the data. This accounts for
  8.1849 +     * the turnaround bits. The first clock occurred when we clocked out the
  8.1850 +     * last bit of the Register Address.
  8.1851 +     */
  8.1852 +    e1000_raise_mdi_clk(hw, &ctrl);
  8.1853 +    e1000_lower_mdi_clk(hw, &ctrl);
  8.1854 +
  8.1855 +    for(data = 0, i = 0; i < 16; i++) {
  8.1856 +        data = data << 1;
  8.1857 +        e1000_raise_mdi_clk(hw, &ctrl);
  8.1858 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.1859 +        /* Check to see if we shifted in a "1". */
  8.1860 +        if(ctrl & E1000_CTRL_MDIO) data |= 1;
  8.1861 +        e1000_lower_mdi_clk(hw, &ctrl);
  8.1862 +    }
  8.1863 +
  8.1864 +    e1000_raise_mdi_clk(hw, &ctrl);
  8.1865 +    e1000_lower_mdi_clk(hw, &ctrl);
  8.1866 +
  8.1867 +    return data;
  8.1868 +}
  8.1869 +
  8.1870 +/*****************************************************************************
  8.1871 +* Reads the value from a PHY register
  8.1872 +*
  8.1873 +* hw - Struct containing variables accessed by shared code
  8.1874 +* reg_addr - address of the PHY register to read
  8.1875 +******************************************************************************/
  8.1876 +int32_t
  8.1877 +e1000_read_phy_reg(struct e1000_hw *hw,
  8.1878 +                   uint32_t reg_addr,
  8.1879 +                   uint16_t *phy_data)
  8.1880 +{
  8.1881 +    uint32_t i;
  8.1882 +    uint32_t mdic = 0;
  8.1883 +    const uint32_t phy_addr = 1;
  8.1884 +
  8.1885 +    DEBUGFUNC("e1000_read_phy_reg");
  8.1886 +
  8.1887 +    if(reg_addr > MAX_PHY_REG_ADDRESS) {
  8.1888 +        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
  8.1889 +        return -E1000_ERR_PARAM;
  8.1890 +    }
  8.1891 +
  8.1892 +    if(hw->mac_type > e1000_82543) {
  8.1893 +        /* Set up Op-code, Phy Address, and register address in the MDI
  8.1894 +         * Control register.  The MAC will take care of interfacing with the
  8.1895 +         * PHY to retrieve the desired data.
  8.1896 +         */
  8.1897 +        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  8.1898 +                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
  8.1899 +                (E1000_MDIC_OP_READ));
  8.1900 +
  8.1901 +        E1000_WRITE_REG(hw, MDIC, mdic);
  8.1902 +
  8.1903 +        /* Poll the ready bit to see if the MDI read completed */
  8.1904 +        for(i = 0; i < 64; i++) {
  8.1905 +            udelay(10);
  8.1906 +            mdic = E1000_READ_REG(hw, MDIC);
  8.1907 +            if(mdic & E1000_MDIC_READY) break;
  8.1908 +        }
  8.1909 +        if(!(mdic & E1000_MDIC_READY)) {
  8.1910 +            DEBUGOUT("MDI Read did not complete\n");
  8.1911 +            return -E1000_ERR_PHY;
  8.1912 +        }
  8.1913 +        if(mdic & E1000_MDIC_ERROR) {
  8.1914 +            DEBUGOUT("MDI Error\n");
  8.1915 +            return -E1000_ERR_PHY;
  8.1916 +        }
  8.1917 +        *phy_data = (uint16_t) mdic;
  8.1918 +    } else {
  8.1919 +        /* We must first send a preamble through the MDIO pin to signal the
  8.1920 +         * beginning of an MII instruction.  This is done by sending 32
  8.1921 +         * consecutive "1" bits.
  8.1922 +         */
  8.1923 +        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  8.1924 +
  8.1925 +        /* Now combine the next few fields that are required for a read
  8.1926 +         * operation.  We use this method instead of calling the
  8.1927 +         * e1000_shift_out_mdi_bits routine five different times. The format of
  8.1928 +         * a MII read instruction consists of a shift out of 14 bits and is
  8.1929 +         * defined as follows:
  8.1930 +         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  8.1931 +         * followed by a shift in of 18 bits.  This first two bits shifted in
  8.1932 +         * are TurnAround bits used to avoid contention on the MDIO pin when a
  8.1933 +         * READ operation is performed.  These two bits are thrown away
  8.1934 +         * followed by a shift in of 16 bits which contains the desired data.
  8.1935 +         */
  8.1936 +        mdic = ((reg_addr) | (phy_addr << 5) | 
  8.1937 +                (PHY_OP_READ << 10) | (PHY_SOF << 12));
  8.1938 +
  8.1939 +        e1000_shift_out_mdi_bits(hw, mdic, 14);
  8.1940 +
  8.1941 +        /* Now that we've shifted out the read command to the MII, we need to
  8.1942 +         * "shift in" the 16-bit value (18 total bits) of the requested PHY
  8.1943 +         * register address.
  8.1944 +         */
  8.1945 +        *phy_data = e1000_shift_in_mdi_bits(hw);
  8.1946 +    }
  8.1947 +    return 0;
  8.1948 +}
  8.1949 +
  8.1950 +/******************************************************************************
  8.1951 +* Writes a value to a PHY register
  8.1952 +*
  8.1953 +* hw - Struct containing variables accessed by shared code
  8.1954 +* reg_addr - address of the PHY register to write
  8.1955 +* data - data to write to the PHY
  8.1956 +******************************************************************************/
  8.1957 +int32_t
  8.1958 +e1000_write_phy_reg(struct e1000_hw *hw,
  8.1959 +                    uint32_t reg_addr,
  8.1960 +                    uint16_t phy_data)
  8.1961 +{
  8.1962 +    uint32_t i;
  8.1963 +    uint32_t mdic = 0;
  8.1964 +    const uint32_t phy_addr = 1;
  8.1965 +
  8.1966 +    DEBUGFUNC("e1000_write_phy_reg");
  8.1967 +
  8.1968 +    if(reg_addr > MAX_PHY_REG_ADDRESS) {
  8.1969 +        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
  8.1970 +        return -E1000_ERR_PARAM;
  8.1971 +    }
  8.1972 +
  8.1973 +    if(hw->mac_type > e1000_82543) {
  8.1974 +        /* Set up Op-code, Phy Address, register address, and data intended
  8.1975 +         * for the PHY register in the MDI Control register.  The MAC will take
  8.1976 +         * care of interfacing with the PHY to send the desired data.
  8.1977 +         */
  8.1978 +        mdic = (((uint32_t) phy_data) |
  8.1979 +                (reg_addr << E1000_MDIC_REG_SHIFT) |
  8.1980 +                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
  8.1981 +                (E1000_MDIC_OP_WRITE));
  8.1982 +
  8.1983 +        E1000_WRITE_REG(hw, MDIC, mdic);
  8.1984 +
  8.1985 +        /* Poll the ready bit to see if the MDI read completed */
  8.1986 +        for(i = 0; i < 64; i++) {
  8.1987 +            udelay(10);
  8.1988 +            mdic = E1000_READ_REG(hw, MDIC);
  8.1989 +            if(mdic & E1000_MDIC_READY) break;
  8.1990 +        }
  8.1991 +        if(!(mdic & E1000_MDIC_READY)) {
  8.1992 +            DEBUGOUT("MDI Write did not complete\n");
  8.1993 +            return -E1000_ERR_PHY;
  8.1994 +        }
  8.1995 +    } else {
  8.1996 +        /* We'll need to use the SW defined pins to shift the write command
  8.1997 +         * out to the PHY. We first send a preamble to the PHY to signal the
  8.1998 +         * beginning of the MII instruction.  This is done by sending 32 
  8.1999 +         * consecutive "1" bits.
  8.2000 +         */
  8.2001 +        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  8.2002 +
  8.2003 +        /* Now combine the remaining required fields that will indicate a 
  8.2004 +         * write operation. We use this method instead of calling the
  8.2005 +         * e1000_shift_out_mdi_bits routine for each field in the command. The
  8.2006 +         * format of a MII write instruction is as follows:
  8.2007 +         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  8.2008 +         */
  8.2009 +        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  8.2010 +                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  8.2011 +        mdic <<= 16;
  8.2012 +        mdic |= (uint32_t) phy_data;
  8.2013 +
  8.2014 +        e1000_shift_out_mdi_bits(hw, mdic, 32);
  8.2015 +    }
  8.2016 +    return 0;
  8.2017 +}
  8.2018 +
  8.2019 +/******************************************************************************
  8.2020 +* Returns the PHY to the power-on reset state
  8.2021 +*
  8.2022 +* hw - Struct containing variables accessed by shared code
  8.2023 +******************************************************************************/
  8.2024 +void
  8.2025 +e1000_phy_hw_reset(struct e1000_hw *hw)
  8.2026 +{
  8.2027 +    uint32_t ctrl;
  8.2028 +    uint32_t ctrl_ext;
  8.2029 +
  8.2030 +    DEBUGFUNC("e1000_phy_hw_reset");
  8.2031 +
  8.2032 +    DEBUGOUT("Resetting Phy...\n");
  8.2033 +
  8.2034 +    if(hw->mac_type > e1000_82543) {
  8.2035 +        /* Read the device control register and assert the E1000_CTRL_PHY_RST
  8.2036 +         * bit. Then, take it out of reset.
  8.2037 +         */
  8.2038 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.2039 +        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  8.2040 +        E1000_WRITE_FLUSH(hw);
  8.2041 +        msec_delay(10);
  8.2042 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.2043 +        E1000_WRITE_FLUSH(hw);
  8.2044 +    } else {
  8.2045 +        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  8.2046 +         * bit to put the PHY into reset. Then, take it out of reset.
  8.2047 +         */
  8.2048 +        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  8.2049 +        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  8.2050 +        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  8.2051 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  8.2052 +        E1000_WRITE_FLUSH(hw);
  8.2053 +        msec_delay(10);
  8.2054 +        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  8.2055 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  8.2056 +        E1000_WRITE_FLUSH(hw);
  8.2057 +    }
  8.2058 +    udelay(150);
  8.2059 +}
  8.2060 +
  8.2061 +/******************************************************************************
  8.2062 +* Resets the PHY
  8.2063 +*
  8.2064 +* hw - Struct containing variables accessed by shared code
  8.2065 +*
  8.2066 +* Sets bit 15 of the MII Control regiser
  8.2067 +******************************************************************************/
  8.2068 +int32_t
  8.2069 +e1000_phy_reset(struct e1000_hw *hw)
  8.2070 +{
  8.2071 +    uint16_t phy_data;
  8.2072 +
  8.2073 +    DEBUGFUNC("e1000_phy_reset");
  8.2074 +
  8.2075 +    if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
  8.2076 +        DEBUGOUT("PHY Read Error\n");
  8.2077 +        return -E1000_ERR_PHY;
  8.2078 +    }
  8.2079 +    phy_data |= MII_CR_RESET;
  8.2080 +    if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
  8.2081 +        DEBUGOUT("PHY Write Error\n");
  8.2082 +        return -E1000_ERR_PHY;
  8.2083 +    }
  8.2084 +    udelay(1);
  8.2085 +    return 0;
  8.2086 +}
  8.2087 +
  8.2088 +/******************************************************************************
  8.2089 +* Probes the expected PHY address for known PHY IDs
  8.2090 +*
  8.2091 +* hw - Struct containing variables accessed by shared code
  8.2092 +******************************************************************************/
  8.2093 +int32_t
  8.2094 +e1000_detect_gig_phy(struct e1000_hw *hw)
  8.2095 +{
  8.2096 +    uint16_t phy_id_high, phy_id_low;
  8.2097 +    boolean_t match = FALSE;
  8.2098 +
  8.2099 +    DEBUGFUNC("e1000_detect_gig_phy");
  8.2100 +
  8.2101 +    /* Read the PHY ID Registers to identify which PHY is onboard. */
  8.2102 +    if(e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
  8.2103 +        DEBUGOUT("PHY Read Error\n");
  8.2104 +        return -E1000_ERR_PHY;
  8.2105 +    }
  8.2106 +    hw->phy_id = (uint32_t) (phy_id_high << 16);
  8.2107 +    udelay(2);
  8.2108 +    if(e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
  8.2109 +        DEBUGOUT("PHY Read Error\n");
  8.2110 +        return -E1000_ERR_PHY;
  8.2111 +    }
  8.2112 +    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  8.2113 +    hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  8.2114 +
  8.2115 +    switch(hw->mac_type) {
  8.2116 +    case e1000_82543:
  8.2117 +        if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
  8.2118 +        break;
  8.2119 +    case e1000_82544:
  8.2120 +        if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
  8.2121 +        break;
  8.2122 +    case e1000_82540:
  8.2123 +    case e1000_82545:
  8.2124 +    case e1000_82546:
  8.2125 +        if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
  8.2126 +        break;
  8.2127 +    default:
  8.2128 +        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
  8.2129 +        return -E1000_ERR_CONFIG;
  8.2130 +    }
  8.2131 +    if(match) {
  8.2132 +        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
  8.2133 +        return 0;
  8.2134 +    }
  8.2135 +    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
  8.2136 +    return -E1000_ERR_PHY;
  8.2137 +}
  8.2138 +
  8.2139 +/******************************************************************************
  8.2140 +* Resets the PHY's DSP
  8.2141 +*
  8.2142 +* hw - Struct containing variables accessed by shared code
  8.2143 +******************************************************************************/
  8.2144 +static int32_t
  8.2145 +e1000_phy_reset_dsp(struct e1000_hw *hw)
  8.2146 +{
  8.2147 +    int32_t ret_val = -E1000_ERR_PHY;
  8.2148 +    DEBUGFUNC("e1000_phy_reset_dsp");
  8.2149 +    
  8.2150 +    do {
  8.2151 +        if(e1000_write_phy_reg(hw, 29, 0x001d) < 0) break;
  8.2152 +        if(e1000_write_phy_reg(hw, 30, 0x00c1) < 0) break;
  8.2153 +        if(e1000_write_phy_reg(hw, 30, 0x0000) < 0) break;
  8.2154 +        ret_val = 0;
  8.2155 +    } while(0);
  8.2156 +
  8.2157 +    if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
  8.2158 +    return ret_val;
  8.2159 +}
  8.2160 +
  8.2161 +/******************************************************************************
  8.2162 +* Get PHY information from various PHY registers
  8.2163 +*
  8.2164 +* hw - Struct containing variables accessed by shared code
  8.2165 +* phy_info - PHY information structure
  8.2166 +******************************************************************************/
  8.2167 +int32_t
  8.2168 +e1000_phy_get_info(struct e1000_hw *hw,
  8.2169 +                   struct e1000_phy_info *phy_info)
  8.2170 +{
  8.2171 +    int32_t ret_val = -E1000_ERR_PHY;
  8.2172 +    uint16_t phy_data;
  8.2173 +
  8.2174 +    DEBUGFUNC("e1000_phy_get_info");
  8.2175 +
  8.2176 +    phy_info->cable_length = e1000_cable_length_undefined;
  8.2177 +    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
  8.2178 +    phy_info->cable_polarity = e1000_rev_polarity_undefined;
  8.2179 +    phy_info->polarity_correction = e1000_polarity_reversal_undefined;
  8.2180 +    phy_info->mdix_mode = e1000_auto_x_mode_undefined;
  8.2181 +    phy_info->local_rx = e1000_1000t_rx_status_undefined;
  8.2182 +    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
  8.2183 +
  8.2184 +    if(hw->media_type != e1000_media_type_copper) {
  8.2185 +        DEBUGOUT("PHY info is only valid for copper media\n");
  8.2186 +        return -E1000_ERR_CONFIG;
  8.2187 +    }
  8.2188 +
  8.2189 +    do {
  8.2190 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
  8.2191 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
  8.2192 +        if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
  8.2193 +            DEBUGOUT("PHY info is only valid if link is up\n");
  8.2194 +            return -E1000_ERR_CONFIG;
  8.2195 +        }
  8.2196 +
  8.2197 +        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
  8.2198 +            break;
  8.2199 +        phy_info->extended_10bt_distance =
  8.2200 +            (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
  8.2201 +            M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
  8.2202 +        phy_info->polarity_correction =
  8.2203 +            (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
  8.2204 +            M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
  8.2205 +
  8.2206 +        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
  8.2207 +            break;
  8.2208 +        phy_info->cable_polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
  8.2209 +            M88E1000_PSSR_REV_POLARITY_SHIFT;
  8.2210 +        phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
  8.2211 +            M88E1000_PSSR_MDIX_SHIFT;
  8.2212 +        if(phy_data & M88E1000_PSSR_1000MBS) {
  8.2213 +            /* Cable Length Estimation and Local/Remote Receiver Informatoion
  8.2214 +             * are only valid at 1000 Mbps
  8.2215 +             */
  8.2216 +            phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  8.2217 +                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
  8.2218 +            if(e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 
  8.2219 +                break;
  8.2220 +            phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  8.2221 +                SR_1000T_LOCAL_RX_STATUS_SHIFT;
  8.2222 +            phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  8.2223 +                SR_1000T_REMOTE_RX_STATUS_SHIFT;
  8.2224 +        }
  8.2225 +        ret_val = 0;
  8.2226 +    } while(0);
  8.2227 +
  8.2228 +    if(ret_val < 0) DEBUGOUT("PHY Read Error\n");
  8.2229 +    return ret_val;
  8.2230 +}
  8.2231 +
  8.2232 +int32_t
  8.2233 +e1000_validate_mdi_setting(struct e1000_hw *hw)
  8.2234 +{
  8.2235 +    DEBUGFUNC("e1000_validate_mdi_settings");
  8.2236 +
  8.2237 +    if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
  8.2238 +        DEBUGOUT("Invalid MDI setting detected\n");
  8.2239 +        hw->mdix = 1;
  8.2240 +        return -E1000_ERR_CONFIG;
  8.2241 +    }
  8.2242 +    return 0;
  8.2243 +}
  8.2244 +
  8.2245 +/******************************************************************************
  8.2246 + * Raises the EEPROM's clock input.
  8.2247 + *
  8.2248 + * hw - Struct containing variables accessed by shared code
  8.2249 + * eecd - EECD's current value
  8.2250 + *****************************************************************************/
  8.2251 +static void
  8.2252 +e1000_raise_ee_clk(struct e1000_hw *hw,
  8.2253 +                   uint32_t *eecd)
  8.2254 +{
  8.2255 +    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  8.2256 +     * wait <delay> microseconds.
  8.2257 +     */
  8.2258 +    *eecd = *eecd | E1000_EECD_SK;
  8.2259 +    E1000_WRITE_REG(hw, EECD, *eecd);
  8.2260 +    E1000_WRITE_FLUSH(hw);
  8.2261 +    udelay(50);
  8.2262 +}
  8.2263 +
  8.2264 +/******************************************************************************
  8.2265 + * Lowers the EEPROM's clock input.
  8.2266 + *
  8.2267 + * hw - Struct containing variables accessed by shared code 
  8.2268 + * eecd - EECD's current value
  8.2269 + *****************************************************************************/
  8.2270 +static void
  8.2271 +e1000_lower_ee_clk(struct e1000_hw *hw,
  8.2272 +                   uint32_t *eecd)
  8.2273 +{
  8.2274 +    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
  8.2275 +     * wait 50 microseconds. 
  8.2276 +     */
  8.2277 +    *eecd = *eecd & ~E1000_EECD_SK;
  8.2278 +    E1000_WRITE_REG(hw, EECD, *eecd);
  8.2279 +    E1000_WRITE_FLUSH(hw);
  8.2280 +    udelay(50);
  8.2281 +}
  8.2282 +
  8.2283 +/******************************************************************************
  8.2284 + * Shift data bits out to the EEPROM.
  8.2285 + *
  8.2286 + * hw - Struct containing variables accessed by shared code
  8.2287 + * data - data to send to the EEPROM
  8.2288 + * count - number of bits to shift out
  8.2289 + *****************************************************************************/
  8.2290 +static void
  8.2291 +e1000_shift_out_ee_bits(struct e1000_hw *hw,
  8.2292 +                        uint16_t data,
  8.2293 +                        uint16_t count)
  8.2294 +{
  8.2295 +    uint32_t eecd;
  8.2296 +    uint32_t mask;
  8.2297 +
  8.2298 +    /* We need to shift "count" bits out to the EEPROM. So, value in the
  8.2299 +     * "data" parameter will be shifted out to the EEPROM one bit at a time.
  8.2300 +     * In order to do this, "data" must be broken down into bits. 
  8.2301 +     */
  8.2302 +    mask = 0x01 << (count - 1);
  8.2303 +    eecd = E1000_READ_REG(hw, EECD);
  8.2304 +    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  8.2305 +    do {
  8.2306 +        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  8.2307 +         * and then raising and then lowering the clock (the SK bit controls
  8.2308 +         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
  8.2309 +         * by setting "DI" to "0" and then raising and then lowering the clock.
  8.2310 +         */
  8.2311 +        eecd &= ~E1000_EECD_DI;
  8.2312 +
  8.2313 +        if(data & mask)
  8.2314 +            eecd |= E1000_EECD_DI;
  8.2315 +
  8.2316 +        E1000_WRITE_REG(hw, EECD, eecd);
  8.2317 +        E1000_WRITE_FLUSH(hw);
  8.2318 +
  8.2319 +        udelay(50);
  8.2320 +
  8.2321 +        e1000_raise_ee_clk(hw, &eecd);
  8.2322 +        e1000_lower_ee_clk(hw, &eecd);
  8.2323 +
  8.2324 +        mask = mask >> 1;
  8.2325 +
  8.2326 +    } while(mask);
  8.2327 +
  8.2328 +    /* We leave the "DI" bit set to "0" when we leave this routine. */
  8.2329 +    eecd &= ~E1000_EECD_DI;
  8.2330 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2331 +}
  8.2332 +
  8.2333 +/******************************************************************************
  8.2334 + * Shift data bits in from the EEPROM
  8.2335 + *
  8.2336 + * hw - Struct containing variables accessed by shared code
  8.2337 + *****************************************************************************/
  8.2338 +static uint16_t
  8.2339 +e1000_shift_in_ee_bits(struct e1000_hw *hw)
  8.2340 +{
  8.2341 +    uint32_t eecd;
  8.2342 +    uint32_t i;
  8.2343 +    uint16_t data;
  8.2344 +
  8.2345 +    /* In order to read a register from the EEPROM, we need to shift 'count'
  8.2346 +     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  8.2347 +     * input to the EEPROM (setting the SK bit), and then reading the value of
  8.2348 +     * the "DO" bit.  During this "shifting in" process the "DI" bit should
  8.2349 +     * always be clear.
  8.2350 +     */
  8.2351 +
  8.2352 +    eecd = E1000_READ_REG(hw, EECD);
  8.2353 +
  8.2354 +    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  8.2355 +    data = 0;
  8.2356 +
  8.2357 +    for(i = 0; i < 16; i++) {
  8.2358 +        data = data << 1;
  8.2359 +        e1000_raise_ee_clk(hw, &eecd);
  8.2360 +
  8.2361 +        eecd = E1000_READ_REG(hw, EECD);
  8.2362 +
  8.2363 +        eecd &= ~(E1000_EECD_DI);
  8.2364 +        if(eecd & E1000_EECD_DO)
  8.2365 +            data |= 1;
  8.2366 +
  8.2367 +        e1000_lower_ee_clk(hw, &eecd);
  8.2368 +    }
  8.2369 +
  8.2370 +    return data;
  8.2371 +}
  8.2372 +
  8.2373 +/******************************************************************************
  8.2374 + * Prepares EEPROM for access
  8.2375 + *
  8.2376 + * hw - Struct containing variables accessed by shared code
  8.2377 + *
  8.2378 + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
  8.2379 + * function should be called before issuing a command to the EEPROM.
  8.2380 + *****************************************************************************/
  8.2381 +static void
  8.2382 +e1000_setup_eeprom(struct e1000_hw *hw)
  8.2383 +{
  8.2384 +    uint32_t eecd;
  8.2385 +
  8.2386 +    eecd = E1000_READ_REG(hw, EECD);
  8.2387 +
  8.2388 +    /* Clear SK and DI */
  8.2389 +    eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
  8.2390 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2391 +
  8.2392 +    /* Set CS */
  8.2393 +    eecd |= E1000_EECD_CS;
  8.2394 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2395 +}
  8.2396 +
  8.2397 +/******************************************************************************
  8.2398 + * Returns EEPROM to a "standby" state
  8.2399 + * 
  8.2400 + * hw - Struct containing variables accessed by shared code
  8.2401 + *****************************************************************************/
  8.2402 +static void
  8.2403 +e1000_standby_eeprom(struct e1000_hw *hw)
  8.2404 +{
  8.2405 +    uint32_t eecd;
  8.2406 +
  8.2407 +    eecd = E1000_READ_REG(hw, EECD);
  8.2408 +
  8.2409 +    /* Deselct EEPROM */
  8.2410 +    eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  8.2411 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2412 +    E1000_WRITE_FLUSH(hw);
  8.2413 +    udelay(50);
  8.2414 +
  8.2415 +    /* Clock high */
  8.2416 +    eecd |= E1000_EECD_SK;
  8.2417 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2418 +    E1000_WRITE_FLUSH(hw);
  8.2419 +    udelay(50);
  8.2420 +
  8.2421 +    /* Select EEPROM */
  8.2422 +    eecd |= E1000_EECD_CS;
  8.2423 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2424 +    E1000_WRITE_FLUSH(hw);
  8.2425 +    udelay(50);
  8.2426 +
  8.2427 +    /* Clock low */
  8.2428 +    eecd &= ~E1000_EECD_SK;
  8.2429 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2430 +    E1000_WRITE_FLUSH(hw);
  8.2431 +    udelay(50);
  8.2432 +}
  8.2433 +
  8.2434 +/******************************************************************************
  8.2435 + * Raises then lowers the EEPROM's clock pin
  8.2436 + *
  8.2437 + * hw - Struct containing variables accessed by shared code
  8.2438 + *****************************************************************************/
  8.2439 +static void
  8.2440 +e1000_clock_eeprom(struct e1000_hw *hw)
  8.2441 +{
  8.2442 +    uint32_t eecd;
  8.2443 +
  8.2444 +    eecd = E1000_READ_REG(hw, EECD);
  8.2445 +
  8.2446 +    /* Rising edge of clock */
  8.2447 +    eecd |= E1000_EECD_SK;
  8.2448 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2449 +    E1000_WRITE_FLUSH(hw);
  8.2450 +    udelay(50);
  8.2451 +
  8.2452 +    /* Falling edge of clock */
  8.2453 +    eecd &= ~E1000_EECD_SK;
  8.2454 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2455 +    E1000_WRITE_FLUSH(hw);
  8.2456 +    udelay(50);
  8.2457 +}
  8.2458 +
  8.2459 +/******************************************************************************
  8.2460 + * Terminates a command by lowering the EEPROM's chip select pin
  8.2461 + *
  8.2462 + * hw - Struct containing variables accessed by shared code
  8.2463 + *****************************************************************************/
  8.2464 +static void
  8.2465 +e1000_cleanup_eeprom(struct e1000_hw *hw)
  8.2466 +{
  8.2467 +    uint32_t eecd;
  8.2468 +
  8.2469 +    eecd = E1000_READ_REG(hw, EECD);
  8.2470 +
  8.2471 +    eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  8.2472 +
  8.2473 +    E1000_WRITE_REG(hw, EECD, eecd);
  8.2474 +
  8.2475 +    e1000_clock_eeprom(hw);
  8.2476 +}
  8.2477 +
  8.2478 +/******************************************************************************
  8.2479 + * Reads a 16 bit word from the EEPROM.
  8.2480 + *
  8.2481 + * hw - Struct containing variables accessed by shared code
  8.2482 + * offset - offset of  word in the EEPROM to read
  8.2483 + * data - word read from the EEPROM 
  8.2484 + *****************************************************************************/
  8.2485 +int32_t
  8.2486 +e1000_read_eeprom(struct e1000_hw *hw,
  8.2487 +                  uint16_t offset,
  8.2488 +                  uint16_t *data)
  8.2489 +{
  8.2490 +    uint32_t eecd;
  8.2491 +    uint32_t i = 0;
  8.2492 +    boolean_t large_eeprom = FALSE;
  8.2493 +
  8.2494 +    DEBUGFUNC("e1000_read_eeprom");
  8.2495 +
  8.2496 +    /* Request EEPROM Access */
  8.2497 +    if(hw->mac_type > e1000_82544) {
  8.2498 +        eecd = E1000_READ_REG(hw, EECD);
  8.2499 +        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
  8.2500 +        eecd |= E1000_EECD_REQ;
  8.2501 +        E1000_WRITE_REG(hw, EECD, eecd);
  8.2502 +        eecd = E1000_READ_REG(hw, EECD);
  8.2503 +        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
  8.2504 +            i++;
  8.2505 +            udelay(5);
  8.2506 +            eecd = E1000_READ_REG(hw, EECD);
  8.2507 +        }
  8.2508 +        if(!(eecd & E1000_EECD_GNT)) {
  8.2509 +            eecd &= ~E1000_EECD_REQ;
  8.2510 +            E1000_WRITE_REG(hw, EECD, eecd);
  8.2511 +            DEBUGOUT("Could not acquire EEPROM grant\n");
  8.2512 +            return -E1000_ERR_EEPROM;
  8.2513 +        }
  8.2514 +    }
  8.2515 +
  8.2516 +    /*  Prepare the EEPROM for reading  */
  8.2517 +    e1000_setup_eeprom(hw);
  8.2518 +
  8.2519 +    /*  Send the READ command (opcode + addr)  */
  8.2520 +    e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
  8.2521 +    if(large_eeprom) {
  8.2522 +        /* If we have a 256 word EEPROM, there are 8 address bits */
  8.2523 +        e1000_shift_out_ee_bits(hw, offset, 8);
  8.2524 +    } else {
  8.2525 +        /* If we have a 64 word EEPROM, there are 6 address bits */
  8.2526 +        e1000_shift_out_ee_bits(hw, offset, 6);
  8.2527 +    }
  8.2528 +
  8.2529 +    /* Read the data */
  8.2530 +    *data = e1000_shift_in_ee_bits(hw);
  8.2531 +
  8.2532 +    /* End this read operation */
  8.2533 +    e1000_standby_eeprom(hw);
  8.2534 +
  8.2535 +    /* Stop requesting EEPROM access */
  8.2536 +    if(hw->mac_type > e1000_82544) {
  8.2537 +        eecd = E1000_READ_REG(hw, EECD);
  8.2538 +        eecd &= ~E1000_EECD_REQ;
  8.2539 +        E1000_WRITE_REG(hw, EECD, eecd);
  8.2540 +    }
  8.2541 +
  8.2542 +    return 0;
  8.2543 +}
  8.2544 +
  8.2545 +/******************************************************************************
  8.2546 + * Verifies that the EEPROM has a valid checksum
  8.2547 + * 
  8.2548 + * hw - Struct containing variables accessed by shared code
  8.2549 + *
  8.2550 + * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  8.2551 + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  8.2552 + * valid.
  8.2553 + *****************************************************************************/
  8.2554 +int32_t
  8.2555 +e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  8.2556 +{
  8.2557 +    uint16_t checksum = 0;
  8.2558 +    uint16_t i, eeprom_data;
  8.2559 +
  8.2560 +    DEBUGFUNC("e1000_validate_eeprom_checksum");
  8.2561 +
  8.2562 +    for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
  8.2563 +        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
  8.2564 +            DEBUGOUT("EEPROM Read Error\n");
  8.2565 +            return -E1000_ERR_EEPROM;
  8.2566 +        }
  8.2567 +        checksum += eeprom_data;
  8.2568 +    }
  8.2569 +
  8.2570 +    if(checksum == (uint16_t) EEPROM_SUM) {
  8.2571 +        return 0;
  8.2572 +    } else {
  8.2573 +        DEBUGOUT("EEPROM Checksum Invalid\n");    
  8.2574 +        return -E1000_ERR_EEPROM;
  8.2575 +    }
  8.2576 +}
  8.2577 +
  8.2578 +/******************************************************************************
  8.2579 + * Calculates the EEPROM checksum and writes it to the EEPROM
  8.2580 + *
  8.2581 + * hw - Struct containing variables accessed by shared code
  8.2582 + *
  8.2583 + * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
  8.2584 + * Writes the difference to word offset 63 of the EEPROM.
  8.2585 + *****************************************************************************/
  8.2586 +int32_t
  8.2587 +e1000_update_eeprom_checksum(struct e1000_hw *hw)
  8.2588 +{
  8.2589 +    uint16_t checksum = 0;
  8.2590 +    uint16_t i, eeprom_data;
  8.2591 +
  8.2592 +    DEBUGFUNC("e1000_update_eeprom_checksum");
  8.2593 +
  8.2594 +    for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  8.2595 +        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
  8.2596 +            DEBUGOUT("EEPROM Read Error\n");
  8.2597 +            return -E1000_ERR_EEPROM;
  8.2598 +        }
  8.2599 +        checksum += eeprom_data;
  8.2600 +    }
  8.2601 +    checksum = (uint16_t) EEPROM_SUM - checksum;
  8.2602 +    if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum) < 0) {
  8.2603 +        DEBUGOUT("EEPROM Write Error\n");
  8.2604 +        return -E1000_ERR_EEPROM;
  8.2605 +    }
  8.2606 +    return 0;
  8.2607 +}
  8.2608 +
  8.2609 +/******************************************************************************
  8.2610 + * Writes a 16 bit word to a given offset in the EEPROM.
  8.2611 + *
  8.2612 + * hw - Struct containing variables accessed by shared code
  8.2613 + * offset - offset within the EEPROM to be written to
  8.2614 + * data - 16 bit word to be writen to the EEPROM
  8.2615 + *
  8.2616 + * If e1000_update_eeprom_checksum is not called after this function, the 
  8.2617 + * EEPROM will most likely contain an invalid checksum.
  8.2618 + *****************************************************************************/
  8.2619 +int32_t
  8.2620 +e1000_write_eeprom(struct e1000_hw *hw,
  8.2621 +                   uint16_t offset,
  8.2622 +                   uint16_t data)
  8.2623 +{
  8.2624 +    uint32_t eecd;
  8.2625 +    uint32_t i = 0;
  8.2626 +    int32_t status = 0;
  8.2627 +    boolean_t large_eeprom = FALSE;
  8.2628 +
  8.2629 +    DEBUGFUNC("e1000_write_eeprom");
  8.2630 +
  8.2631 +    /* Request EEPROM Access */
  8.2632 +    if(hw->mac_type > e1000_82544) {
  8.2633 +        eecd = E1000_READ_REG(hw, EECD);
  8.2634 +        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
  8.2635 +        eecd |= E1000_EECD_REQ;
  8.2636 +        E1000_WRITE_REG(hw, EECD, eecd);
  8.2637 +        eecd = E1000_READ_REG(hw, EECD);
  8.2638 +        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
  8.2639 +            i++;
  8.2640 +            udelay(5);
  8.2641 +            eecd = E1000_READ_REG(hw, EECD);
  8.2642 +        }
  8.2643 +        if(!(eecd & E1000_EECD_GNT)) {
  8.2644 +            eecd &= ~E1000_EECD_REQ;
  8.2645 +            E1000_WRITE_REG(hw, EECD, eecd);
  8.2646 +            DEBUGOUT("Could not acquire EEPROM grant\n");
  8.2647 +            return -E1000_ERR_EEPROM;
  8.2648 +        }
  8.2649 +    }
  8.2650 +
  8.2651 +    /* Prepare the EEPROM for writing  */
  8.2652 +    e1000_setup_eeprom(hw);
  8.2653 +
  8.2654 +    /* Send the 9-bit (or 11-bit on large EEPROM) EWEN (write enable) command
  8.2655 +     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This puts the EEPROM
  8.2656 +     * into write/erase mode. 
  8.2657 +     */
  8.2658 +    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
  8.2659 +    if(large_eeprom) 
  8.2660 +        e1000_shift_out_ee_bits(hw, 0, 6);
  8.2661 +    else
  8.2662 +        e1000_shift_out_ee_bits(hw, 0, 4);
  8.2663 +
  8.2664 +    /* Prepare the EEPROM */
  8.2665 +    e1000_standby_eeprom(hw);
  8.2666 +
  8.2667 +    /* Send the Write command (3-bit opcode + addr) */
  8.2668 +    e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
  8.2669 +    if(large_eeprom) 
  8.2670 +        /* If we have a 256 word EEPROM, there are 8 address bits */
  8.2671 +        e1000_shift_out_ee_bits(hw, offset, 8);
  8.2672 +    else
  8.2673 +        /* If we have a 64 word EEPROM, there are 6 address bits */
  8.2674 +        e1000_shift_out_ee_bits(hw, offset, 6);
  8.2675 +
  8.2676 +    /* Send the data */
  8.2677 +    e1000_shift_out_ee_bits(hw, data, 16);
  8.2678 +
  8.2679 +    /* Toggle the CS line.  This in effect tells to EEPROM to actually execute 
  8.2680 +     * the command in question.
  8.2681 +     */
  8.2682 +    e1000_standby_eeprom(hw);
  8.2683 +
  8.2684 +    /* Now read DO repeatedly until is high (equal to '1').  The EEEPROM will
  8.2685 +     * signal that the command has been completed by raising the DO signal.
  8.2686 +     * If DO does not go high in 10 milliseconds, then error out.
  8.2687 +     */
  8.2688 +    for(i = 0; i < 200; i++) {
  8.2689 +        eecd = E1000_READ_REG(hw, EECD);
  8.2690 +        if(eecd & E1000_EECD_DO) break;
  8.2691 +        udelay(50);
  8.2692 +    }
  8.2693 +    if(i == 200) {
  8.2694 +        DEBUGOUT("EEPROM Write did not complete\n");
  8.2695 +        status = -E1000_ERR_EEPROM;
  8.2696 +    }
  8.2697 +
  8.2698 +    /* Recover from write */
  8.2699 +    e1000_standby_eeprom(hw);
  8.2700 +
  8.2701 +    /* Send the 9-bit (or 11-bit on large EEPROM) EWDS (write disable) command
  8.2702 +     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This takes the EEPROM
  8.2703 +     * out of write/erase mode.
  8.2704 +     */
  8.2705 +    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
  8.2706 +    if(large_eeprom) 
  8.2707 +        e1000_shift_out_ee_bits(hw, 0, 6);
  8.2708 +    else
  8.2709 +        e1000_shift_out_ee_bits(hw, 0, 4);
  8.2710 +
  8.2711 +    /* Done with writing */
  8.2712 +    e1000_cleanup_eeprom(hw);
  8.2713 +
  8.2714 +    /* Stop requesting EEPROM access */
  8.2715 +    if(hw->mac_type > e1000_82544) {
  8.2716 +        eecd = E1000_READ_REG(hw, EECD);
  8.2717 +        eecd &= ~E1000_EECD_REQ;
  8.2718 +        E1000_WRITE_REG(hw, EECD, eecd);
  8.2719 +    }
  8.2720 +
  8.2721 +    return status;
  8.2722 +}
  8.2723 +
  8.2724 +/******************************************************************************
  8.2725 + * Reads the adapter's part number from the EEPROM
  8.2726 + *
  8.2727 + * hw - Struct containing variables accessed by shared code
  8.2728 + * part_num - Adapter's part number
  8.2729 + *****************************************************************************/
  8.2730 +int32_t
  8.2731 +e1000_read_part_num(struct e1000_hw *hw,
  8.2732 +                    uint32_t *part_num)
  8.2733 +{
  8.2734 +    uint16_t offset = EEPROM_PBA_BYTE_1;
  8.2735 +    uint16_t eeprom_data;
  8.2736 +
  8.2737 +    DEBUGFUNC("e1000_read_part_num");
  8.2738 +
  8.2739 +    /* Get word 0 from EEPROM */
  8.2740 +    if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
  8.2741 +        DEBUGOUT("EEPROM Read Error\n");
  8.2742 +        return -E1000_ERR_EEPROM;
  8.2743 +    }
  8.2744 +    /* Save word 0 in upper half of part_num */
  8.2745 +    *part_num = (uint32_t) (eeprom_data << 16);
  8.2746 +
  8.2747 +    /* Get word 1 from EEPROM */
  8.2748 +    if(e1000_read_eeprom(hw, ++offset, &eeprom_data) < 0) {
  8.2749 +        DEBUGOUT("EEPROM Read Error\n");
  8.2750 +        return -E1000_ERR_EEPROM;
  8.2751 +    }
  8.2752 +    /* Save word 1 in lower half of part_num */
  8.2753 +    *part_num |= eeprom_data;
  8.2754 +
  8.2755 +    return 0;
  8.2756 +}
  8.2757 +
  8.2758 +/******************************************************************************
  8.2759 + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  8.2760 + * second function of dual function devices
  8.2761 + *
  8.2762 + * hw - Struct containing variables accessed by shared code
  8.2763 + *****************************************************************************/
  8.2764 +int32_t
  8.2765 +e1000_read_mac_addr(struct e1000_hw * hw)
  8.2766 +{
  8.2767 +    uint16_t offset;
  8.2768 +    uint16_t eeprom_data, i;
  8.2769 +
  8.2770 +    DEBUGFUNC("e1000_read_mac_addr");
  8.2771 +
  8.2772 +    for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  8.2773 +        offset = i >> 1;
  8.2774 +        if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
  8.2775 +            DEBUGOUT("EEPROM Read Error\n");
  8.2776 +            return -E1000_ERR_EEPROM;
  8.2777 +        }
  8.2778 +        hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
  8.2779 +        hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
  8.2780 +    }
  8.2781 +    if((hw->mac_type == e1000_82546) &&
  8.2782 +       (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  8.2783 +        if(hw->perm_mac_addr[5] & 0x01)
  8.2784 +            hw->perm_mac_addr[5] &= ~(0x01);
  8.2785 +        else
  8.2786 +            hw->perm_mac_addr[5] |= 0x01;
  8.2787 +    }
  8.2788 +    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
  8.2789 +        hw->mac_addr[i] = hw->perm_mac_addr[i];
  8.2790 +    return 0;
  8.2791 +}
  8.2792 +
  8.2793 +/******************************************************************************
  8.2794 + * Initializes receive address filters.
  8.2795 + *
  8.2796 + * hw - Struct containing variables accessed by shared code 
  8.2797 + *
  8.2798 + * Places the MAC address in receive address register 0 and clears the rest
  8.2799 + * of the receive addresss registers. Clears the multicast table. Assumes
  8.2800 + * the receiver is in reset when the routine is called.
  8.2801 + *****************************************************************************/
  8.2802 +void
  8.2803 +e1000_init_rx_addrs(struct e1000_hw *hw)
  8.2804 +{
  8.2805 +    uint32_t i;
  8.2806 +    uint32_t addr_low;
  8.2807 +    uint32_t addr_high;
  8.2808 +
  8.2809 +    DEBUGFUNC("e1000_init_rx_addrs");
  8.2810 +
  8.2811 +    /* Setup the receive address. */
  8.2812 +    DEBUGOUT("Programming MAC Address into RAR[0]\n");
  8.2813 +    addr_low = (hw->mac_addr[0] |
  8.2814 +                (hw->mac_addr[1] << 8) |
  8.2815 +                (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
  8.2816 +
  8.2817 +    addr_high = (hw->mac_addr[4] |
  8.2818 +                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
  8.2819 +
  8.2820 +    E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  8.2821 +    E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  8.2822 +
  8.2823 +    /* Zero out the other 15 receive addresses. */
  8.2824 +    DEBUGOUT("Clearing RAR[1-15]\n");
  8.2825 +    for(i = 1; i < E1000_RAR_ENTRIES; i++) {
  8.2826 +        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  8.2827 +        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  8.2828 +    }
  8.2829 +}
  8.2830 +
  8.2831 +/******************************************************************************
  8.2832 + * Updates the MAC's list of multicast addresses.
  8.2833 + *
  8.2834 + * hw - Struct containing variables accessed by shared code
  8.2835 + * mc_addr_list - the list of new multicast addresses
  8.2836 + * mc_addr_count - number of addresses
  8.2837 + * pad - number of bytes between addresses in the list
  8.2838 + *
  8.2839 + * The given list replaces any existing list. Clears the last 15 receive
  8.2840 + * address registers and the multicast table. Uses receive address registers
  8.2841 + * for the first 15 multicast addresses, and hashes the rest into the 
  8.2842 + * multicast table.
  8.2843 + *****************************************************************************/
  8.2844 +void
  8.2845 +e1000_mc_addr_list_update(struct e1000_hw *hw,
  8.2846 +                          uint8_t *mc_addr_list,
  8.2847 +                          uint32_t mc_addr_count,
  8.2848 +                          uint32_t pad)
  8.2849 +{
  8.2850 +    uint32_t hash_value;
  8.2851 +    uint32_t i;
  8.2852 +    uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
  8.2853 +
  8.2854 +    DEBUGFUNC("e1000_mc_addr_list_update");
  8.2855 +
  8.2856 +    /* Set the new number of MC addresses that we are being requested to use. */
  8.2857 +    hw->num_mc_addrs = mc_addr_count;
  8.2858 +
  8.2859 +    /* Clear RAR[1-15] */
  8.2860 +    DEBUGOUT(" Clearing RAR[1-15]\n");
  8.2861 +    for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
  8.2862 +        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  8.2863 +        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  8.2864 +    }
  8.2865 +
  8.2866 +    /* Clear the MTA */
  8.2867 +    DEBUGOUT(" Clearing MTA\n");
  8.2868 +    for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
  8.2869 +        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  8.2870 +    }
  8.2871 +
  8.2872 +    /* Add the new addresses */
  8.2873 +    for(i = 0; i < mc_addr_count; i++) {
  8.2874 +        DEBUGOUT(" Adding the multicast addresses:\n");
  8.2875 +        DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
  8.2876 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
  8.2877 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
  8.2878 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
  8.2879 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
  8.2880 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
  8.2881 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
  8.2882 +
  8.2883 +        hash_value = e1000_hash_mc_addr(hw,
  8.2884 +                                        mc_addr_list +
  8.2885 +                                        (i * (ETH_LENGTH_OF_ADDRESS + pad)));
  8.2886 +
  8.2887 +        DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
  8.2888 +
  8.2889 +        /* Place this multicast address in the RAR if there is room, *
  8.2890 +         * else put it in the MTA            
  8.2891 +         */
  8.2892 +        if(rar_used_count < E1000_RAR_ENTRIES) {
  8.2893 +            e1000_rar_set(hw,
  8.2894 +                          mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
  8.2895 +                          rar_used_count);
  8.2896 +            rar_used_count++;
  8.2897 +        } else {
  8.2898 +            e1000_mta_set(hw, hash_value);
  8.2899 +        }
  8.2900 +    }
  8.2901 +    DEBUGOUT("MC Update Complete\n");
  8.2902 +}
  8.2903 +
  8.2904 +/******************************************************************************
  8.2905 + * Hashes an address to determine its location in the multicast table
  8.2906 + *
  8.2907 + * hw - Struct containing variables accessed by shared code
  8.2908 + * mc_addr - the multicast address to hash 
  8.2909 + *****************************************************************************/
  8.2910 +uint32_t
  8.2911 +e1000_hash_mc_addr(struct e1000_hw *hw,
  8.2912 +                   uint8_t *mc_addr)
  8.2913 +{
  8.2914 +    uint32_t hash_value = 0;
  8.2915 +
  8.2916 +    /* The portion of the address that is used for the hash table is
  8.2917 +     * determined by the mc_filter_type setting.  
  8.2918 +     */
  8.2919 +    switch (hw->mc_filter_type) {
  8.2920 +    /* [0] [1] [2] [3] [4] [5]
  8.2921 +     * 01  AA  00  12  34  56
  8.2922 +     * LSB                 MSB
  8.2923 +     */
  8.2924 +    case 0:
  8.2925 +        /* [47:36] i.e. 0x563 for above example address */
  8.2926 +        hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
  8.2927 +        break;
  8.2928 +    case 1:
  8.2929 +        /* [46:35] i.e. 0xAC6 for above example address */
  8.2930 +        hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
  8.2931 +        break;
  8.2932 +    case 2:
  8.2933 +        /* [45:34] i.e. 0x5D8 for above example address */
  8.2934 +        hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
  8.2935 +        break;
  8.2936 +    case 3:
  8.2937 +        /* [43:32] i.e. 0x634 for above example address */
  8.2938 +        hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
  8.2939 +        break;
  8.2940 +    }
  8.2941 +
  8.2942 +    hash_value &= 0xFFF;
  8.2943 +    return hash_value;
  8.2944 +}
  8.2945 +
  8.2946 +/******************************************************************************
  8.2947 + * Sets the bit in the multicast table corresponding to the hash value.
  8.2948 + *
  8.2949 + * hw - Struct containing variables accessed by shared code
  8.2950 + * hash_value - Multicast address hash value
  8.2951 + *****************************************************************************/
  8.2952 +void
  8.2953 +e1000_mta_set(struct e1000_hw *hw,
  8.2954 +              uint32_t hash_value)
  8.2955 +{
  8.2956 +    uint32_t hash_bit, hash_reg;
  8.2957 +    uint32_t mta;
  8.2958 +    uint32_t temp;
  8.2959 +
  8.2960 +    /* The MTA is a register array of 128 32-bit registers.  
  8.2961 +     * It is treated like an array of 4096 bits.  We want to set 
  8.2962 +     * bit BitArray[hash_value]. So we figure out what register
  8.2963 +     * the bit is in, read it, OR in the new bit, then write
  8.2964 +     * back the new value.  The register is determined by the 
  8.2965 +     * upper 7 bits of the hash value and the bit within that 
  8.2966 +     * register are determined by the lower 5 bits of the value.
  8.2967 +     */
  8.2968 +    hash_reg = (hash_value >> 5) & 0x7F;
  8.2969 +    hash_bit = hash_value & 0x1F;
  8.2970 +
  8.2971 +    mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
  8.2972 +
  8.2973 +    mta |= (1 << hash_bit);
  8.2974 +
  8.2975 +    /* If we are on an 82544 and we are trying to write an odd offset
  8.2976 +     * in the MTA, save off the previous entry before writing and
  8.2977 +     * restore the old value after writing.
  8.2978 +     */
  8.2979 +    if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
  8.2980 +        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
  8.2981 +        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
  8.2982 +        E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
  8.2983 +    } else {
  8.2984 +        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
  8.2985 +    }
  8.2986 +}
  8.2987 +
  8.2988 +/******************************************************************************
  8.2989 + * Puts an ethernet address into a receive address register.
  8.2990 + *
  8.2991 + * hw - Struct containing variables accessed by shared code
  8.2992 + * addr - Address to put into receive address register
  8.2993 + * index - Receive address register to write
  8.2994 + *****************************************************************************/
  8.2995 +void
  8.2996 +e1000_rar_set(struct e1000_hw *hw,
  8.2997 +              uint8_t *addr,
  8.2998 +              uint32_t index)
  8.2999 +{
  8.3000 +    uint32_t rar_low, rar_high;
  8.3001 +
  8.3002 +    /* HW expects these in little endian so we reverse the byte order
  8.3003 +     * from network order (big endian) to little endian              
  8.3004 +     */
  8.3005 +    rar_low = ((uint32_t) addr[0] |
  8.3006 +               ((uint32_t) addr[1] << 8) |
  8.3007 +               ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
  8.3008 +
  8.3009 +    rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
  8.3010 +
  8.3011 +    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
  8.3012 +    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
  8.3013 +}
  8.3014 +
  8.3015 +/******************************************************************************
  8.3016 + * Writes a value to the specified offset in the VLAN filter table.
  8.3017 + *
  8.3018 + * hw - Struct containing variables accessed by shared code
  8.3019 + * offset - Offset in VLAN filer table to write
  8.3020 + * value - Value to write into VLAN filter table
  8.3021 + *****************************************************************************/
  8.3022 +void
  8.3023 +e1000_write_vfta(struct e1000_hw *hw,
  8.3024 +                 uint32_t offset,
  8.3025 +                 uint32_t value)
  8.3026 +{
  8.3027 +    uint32_t temp;
  8.3028 +
  8.3029 +    if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
  8.3030 +        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
  8.3031 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
  8.3032 +        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
  8.3033 +    } else {
  8.3034 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
  8.3035 +    }
  8.3036 +}
  8.3037 +
  8.3038 +/******************************************************************************
  8.3039 + * Clears the VLAN filer table
  8.3040 + *
  8.3041 + * hw - Struct containing variables accessed by shared code
  8.3042 + *****************************************************************************/
  8.3043 +void
  8.3044 +e1000_clear_vfta(struct e1000_hw *hw)
  8.3045 +{
  8.3046 +    uint32_t offset;
  8.3047 +
  8.3048 +    for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  8.3049 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  8.3050 +}
  8.3051 +
  8.3052 +static int32_t
  8.3053 +e1000_id_led_init(struct e1000_hw * hw)
  8.3054 +{
  8.3055 +    uint32_t ledctl;
  8.3056 +    const uint32_t ledctl_mask = 0x000000FF;
  8.3057 +    const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
  8.3058 +    const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
  8.3059 +    uint16_t eeprom_data, i, temp;
  8.3060 +    const uint16_t led_mask = 0x0F;
  8.3061 +        
  8.3062 +    DEBUGFUNC("e1000_id_led_init");
  8.3063 +    
  8.3064 +    if(hw->mac_type < e1000_82540) {
  8.3065 +        /* Nothing to do */
  8.3066 +        return 0;
  8.3067 +    }
  8.3068 +    
  8.3069 +    ledctl = E1000_READ_REG(hw, LEDCTL);
  8.3070 +    hw->ledctl_default = ledctl;
  8.3071 +    hw->ledctl_mode1 = hw->ledctl_default;
  8.3072 +    hw->ledctl_mode2 = hw->ledctl_default;
  8.3073 +        
  8.3074 +    if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, &eeprom_data) < 0) {
  8.3075 +        DEBUGOUT("EEPROM Read Error\n");
  8.3076 +        return -E1000_ERR_EEPROM;
  8.3077 +    }
  8.3078 +    if((eeprom_data== ID_LED_RESERVED_0000) || 
  8.3079 +       (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
  8.3080 +    for(i = 0; i < 4; i++) {
  8.3081 +        temp = (eeprom_data >> (i << 2)) & led_mask;
  8.3082 +        switch(temp) {
  8.3083 +        case ID_LED_ON1_DEF2:
  8.3084 +        case ID_LED_ON1_ON2:
  8.3085 +        case ID_LED_ON1_OFF2:
  8.3086 +            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
  8.3087 +            hw->ledctl_mode1 |= ledctl_on << (i << 3);
  8.3088 +            break;
  8.3089 +        case ID_LED_OFF1_DEF2:
  8.3090 +        case ID_LED_OFF1_ON2:
  8.3091 +        case ID_LED_OFF1_OFF2:
  8.3092 +            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
  8.3093 +            hw->ledctl_mode1 |= ledctl_off << (i << 3);
  8.3094 +            break;
  8.3095 +        default:
  8.3096 +            /* Do nothing */
  8.3097 +            break;
  8.3098 +        }
  8.3099 +        switch(temp) {
  8.3100 +        case ID_LED_DEF1_ON2:
  8.3101 +        case ID_LED_ON1_ON2:
  8.3102 +        case ID_LED_OFF1_ON2:
  8.3103 +            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
  8.3104 +            hw->ledctl_mode2 |= ledctl_on << (i << 3);
  8.3105 +            break;
  8.3106 +        case ID_LED_DEF1_OFF2:
  8.3107 +        case ID_LED_ON1_OFF2:
  8.3108 +        case ID_LED_OFF1_OFF2:
  8.3109 +            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
  8.3110 +            hw->ledctl_mode2 |= ledctl_off << (i << 3);
  8.3111 +            break;
  8.3112 +        default:
  8.3113 +            /* Do nothing */
  8.3114 +            break;
  8.3115 +        }
  8.3116 +    }
  8.3117 +    return 0;
  8.3118 +}
  8.3119 +
  8.3120 +/******************************************************************************
  8.3121 + * Prepares SW controlable LED for use and saves the current state of the LED.
  8.3122 + *
  8.3123 + * hw - Struct containing variables accessed by shared code
  8.3124 + *****************************************************************************/
  8.3125 +int32_t
  8.3126 +e1000_setup_led(struct e1000_hw *hw)
  8.3127 +{
  8.3128 +    uint32_t ledctl;
  8.3129 + 
  8.3130 +    DEBUGFUNC("e1000_setup_led");
  8.3131 +   
  8.3132 +    switch(hw->device_id) {
  8.3133 +    case E1000_DEV_ID_82542:
  8.3134 +    case E1000_DEV_ID_82543GC_FIBER:
  8.3135 +    case E1000_DEV_ID_82543GC_COPPER:
  8.3136 +    case E1000_DEV_ID_82544EI_COPPER:
  8.3137 +    case E1000_DEV_ID_82544EI_FIBER:
  8.3138 +    case E1000_DEV_ID_82544GC_COPPER:
  8.3139 +    case E1000_DEV_ID_82544GC_LOM:
  8.3140 +        /* No setup necessary */
  8.3141 +        break;
  8.3142 +    case E1000_DEV_ID_82545EM_FIBER:
  8.3143 +    case E1000_DEV_ID_82546EB_FIBER:
  8.3144 +        ledctl = E1000_READ_REG(hw, LEDCTL);
  8.3145 +        /* Save current LEDCTL settings */
  8.3146 +        hw->ledctl_default = ledctl;
  8.3147 +        /* Turn off LED0 */
  8.3148 +        ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
  8.3149 +                    E1000_LEDCTL_LED0_BLINK | 
  8.3150 +                    E1000_LEDCTL_LED0_MODE_MASK);
  8.3151 +        ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
  8.3152 +        E1000_WRITE_REG(hw, LEDCTL, ledctl);
  8.3153 +        break;
  8.3154 +    case E1000_DEV_ID_82540EP:
  8.3155 +    case E1000_DEV_ID_82540EP_LOM:
  8.3156 +    case E1000_DEV_ID_82540EP_LP:
  8.3157 +    case E1000_DEV_ID_82540EM:
  8.3158 +    case E1000_DEV_ID_82540EM_LOM:
  8.3159 +    case E1000_DEV_ID_82545EM_COPPER:
  8.3160 +    case E1000_DEV_ID_82546EB_COPPER:
  8.3161 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  8.3162 +        break;
  8.3163 +    default:
  8.3164 +        DEBUGOUT("Invalid device ID\n");
  8.3165 +        return -E1000_ERR_CONFIG;
  8.3166 +    }
  8.3167 +    return 0;
  8.3168 +}
  8.3169 +
  8.3170 +/******************************************************************************
  8.3171 + * Restores the saved state of the SW controlable LED.
  8.3172 + *
  8.3173 + * hw - Struct containing variables accessed by shared code
  8.3174 + *****************************************************************************/
  8.3175 +int32_t
  8.3176 +e1000_cleanup_led(struct e1000_hw *hw)
  8.3177 +{
  8.3178 +    DEBUGFUNC("e1000_cleanup_led");
  8.3179 +
  8.3180 +    switch(hw->device_id) {
  8.3181 +    case E1000_DEV_ID_82542:
  8.3182 +    case E1000_DEV_ID_82543GC_FIBER:
  8.3183 +    case E1000_DEV_ID_82543GC_COPPER:
  8.3184 +    case E1000_DEV_ID_82544EI_COPPER:
  8.3185 +    case E1000_DEV_ID_82544EI_FIBER:
  8.3186 +    case E1000_DEV_ID_82544GC_COPPER:
  8.3187 +    case E1000_DEV_ID_82544GC_LOM:
  8.3188 +        /* No cleanup necessary */
  8.3189 +        break;
  8.3190 +    case E1000_DEV_ID_82540EP:
  8.3191 +    case E1000_DEV_ID_82540EP_LOM:
  8.3192 +    case E1000_DEV_ID_82540EP_LP:
  8.3193 +    case E1000_DEV_ID_82540EM:
  8.3194 +    case E1000_DEV_ID_82540EM_LOM:
  8.3195 +    case E1000_DEV_ID_82545EM_COPPER:
  8.3196 +    case E1000_DEV_ID_82545EM_FIBER:
  8.3197 +    case E1000_DEV_ID_82546EB_COPPER:
  8.3198 +    case E1000_DEV_ID_82546EB_FIBER:
  8.3199 +        /* Restore LEDCTL settings */
  8.3200 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
  8.3201 +        break;
  8.3202 +    default:
  8.3203 +        DEBUGOUT("Invalid device ID\n");
  8.3204 +        return -E1000_ERR_CONFIG;
  8.3205 +    }
  8.3206 +    return 0;
  8.3207 +}
  8.3208 +    
  8.3209 +/******************************************************************************
  8.3210 + * Turns on the software controllable LED
  8.3211 + *
  8.3212 + * hw - Struct containing variables accessed by shared code
  8.3213 + *****************************************************************************/
  8.3214 +int32_t
  8.3215 +e1000_led_on(struct e1000_hw *hw)
  8.3216 +{
  8.3217 +    uint32_t ctrl;
  8.3218 +
  8.3219 +    DEBUGFUNC("e1000_led_on");
  8.3220 +
  8.3221 +    switch(hw->device_id) {
  8.3222 +    case E1000_DEV_ID_82542:
  8.3223 +    case E1000_DEV_ID_82543GC_FIBER:
  8.3224 +    case E1000_DEV_ID_82543GC_COPPER:
  8.3225 +    case E1000_DEV_ID_82544EI_FIBER:
  8.3226 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.3227 +        /* Set SW Defineable Pin 0 to turn on the LED */
  8.3228 +        ctrl |= E1000_CTRL_SWDPIN0;
  8.3229 +        ctrl |= E1000_CTRL_SWDPIO0;
  8.3230 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.3231 +        break;
  8.3232 +    case E1000_DEV_ID_82544EI_COPPER:
  8.3233 +    case E1000_DEV_ID_82544GC_COPPER:
  8.3234 +    case E1000_DEV_ID_82544GC_LOM:
  8.3235 +    case E1000_DEV_ID_82545EM_FIBER:
  8.3236 +    case E1000_DEV_ID_82546EB_FIBER:
  8.3237 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.3238 +        /* Clear SW Defineable Pin 0 to turn on the LED */
  8.3239 +        ctrl &= ~E1000_CTRL_SWDPIN0;
  8.3240 +        ctrl |= E1000_CTRL_SWDPIO0;
  8.3241 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.3242 +        break;
  8.3243 +    case E1000_DEV_ID_82540EP:
  8.3244 +    case E1000_DEV_ID_82540EP_LOM:
  8.3245 +    case E1000_DEV_ID_82540EP_LP:
  8.3246 +    case E1000_DEV_ID_82540EM:
  8.3247 +    case E1000_DEV_ID_82540EM_LOM:
  8.3248 +    case E1000_DEV_ID_82545EM_COPPER:
  8.3249 +    case E1000_DEV_ID_82546EB_COPPER:
  8.3250 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
  8.3251 +        break;
  8.3252 +    default:
  8.3253 +        DEBUGOUT("Invalid device ID\n");
  8.3254 +        return -E1000_ERR_CONFIG;
  8.3255 +    }
  8.3256 +    return 0;
  8.3257 +}
  8.3258 +
  8.3259 +/******************************************************************************
  8.3260 + * Turns off the software controllable LED
  8.3261 + *
  8.3262 + * hw - Struct containing variables accessed by shared code
  8.3263 + *****************************************************************************/
  8.3264 +int32_t
  8.3265 +e1000_led_off(struct e1000_hw *hw)
  8.3266 +{
  8.3267 +    uint32_t ctrl;
  8.3268 +
  8.3269 +    DEBUGFUNC("e1000_led_off");
  8.3270 +
  8.3271 +    switch(hw->device_id) {
  8.3272 +    case E1000_DEV_ID_82542:
  8.3273 +    case E1000_DEV_ID_82543GC_FIBER:
  8.3274 +    case E1000_DEV_ID_82543GC_COPPER:
  8.3275 +    case E1000_DEV_ID_82544EI_FIBER:
  8.3276 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.3277 +        /* Clear SW Defineable Pin 0 to turn off the LED */
  8.3278 +        ctrl &= ~E1000_CTRL_SWDPIN0;
  8.3279 +        ctrl |= E1000_CTRL_SWDPIO0;
  8.3280 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.3281 +        break;
  8.3282 +    case E1000_DEV_ID_82544EI_COPPER:
  8.3283 +    case E1000_DEV_ID_82544GC_COPPER:
  8.3284 +    case E1000_DEV_ID_82544GC_LOM:
  8.3285 +    case E1000_DEV_ID_82545EM_FIBER:
  8.3286 +    case E1000_DEV_ID_82546EB_FIBER:
  8.3287 +        ctrl = E1000_READ_REG(hw, CTRL);
  8.3288 +        /* Set SW Defineable Pin 0 to turn off the LED */
  8.3289 +        ctrl |= E1000_CTRL_SWDPIN0;
  8.3290 +        ctrl |= E1000_CTRL_SWDPIO0;
  8.3291 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  8.3292 +        break;
  8.3293 +    case E1000_DEV_ID_82540EP:
  8.3294 +    case E1000_DEV_ID_82540EP_LOM:
  8.3295 +    case E1000_DEV_ID_82540EP_LP:
  8.3296 +    case E1000_DEV_ID_82540EM:
  8.3297 +    case E1000_DEV_ID_82540EM_LOM:
  8.3298 +    case E1000_DEV_ID_82545EM_COPPER:
  8.3299 +    case E1000_DEV_ID_82546EB_COPPER:
  8.3300 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  8.3301 +        break;
  8.3302 +    default:
  8.3303 +        DEBUGOUT("Invalid device ID\n");
  8.3304 +        return -E1000_ERR_CONFIG;
  8.3305 +    }
  8.3306 +    return 0;
  8.3307 +}
  8.3308 +
  8.3309 +/******************************************************************************
  8.3310 + * Clears all hardware statistics counters. 
  8.3311 + *
  8.3312 + * hw - Struct containing variables accessed by shared code
  8.3313 + *****************************************************************************/
  8.3314 +void
  8.3315 +e1000_clear_hw_cntrs(struct e1000_hw *hw)
  8.3316 +{
  8.3317 +    volatile uint32_t temp;
  8.3318 +
  8.3319 +    temp = E1000_READ_REG(hw, CRCERRS);
  8.3320 +    temp = E1000_READ_REG(hw, SYMERRS);
  8.3321 +    temp = E1000_READ_REG(hw, MPC);
  8.3322 +    temp = E1000_READ_REG(hw, SCC);
  8.3323 +    temp = E1000_READ_REG(hw, ECOL);
  8.3324 +    temp = E1000_READ_REG(hw, MCC);
  8.3325 +    temp = E1000_READ_REG(hw, LATECOL);
  8.3326 +    temp = E1000_READ_REG(hw, COLC);
  8.3327 +    temp = E1000_READ_REG(hw, DC);
  8.3328 +    temp = E1000_READ_REG(hw, SEC);
  8.3329 +    temp = E1000_READ_REG(hw, RLEC);
  8.3330 +    temp = E1000_READ_REG(hw, XONRXC);
  8.3331 +    temp = E1000_READ_REG(hw, XONTXC);
  8.3332 +    temp = E1000_READ_REG(hw, XOFFRXC);
  8.3333 +    temp = E1000_READ_REG(hw, XOFFTXC);
  8.3334 +    temp = E1000_READ_REG(hw, FCRUC);
  8.3335 +    temp = E1000_READ_REG(hw, PRC64);
  8.3336 +    temp = E1000_READ_REG(hw, PRC127);
  8.3337 +    temp = E1000_READ_REG(hw, PRC255);
  8.3338 +    temp = E1000_READ_REG(hw, PRC511);
  8.3339 +    temp = E1000_READ_REG(hw, PRC1023);
  8.3340 +    temp = E1000_READ_REG(hw, PRC1522);
  8.3341 +    temp = E1000_READ_REG(hw, GPRC);
  8.3342 +    temp = E1000_READ_REG(hw, BPRC);
  8.3343 +    temp = E1000_READ_REG(hw, MPRC);
  8.3344 +    temp = E1000_READ_REG(hw, GPTC);
  8.3345 +    temp = E1000_READ_REG(hw, GORCL);
  8.3346 +    temp = E1000_READ_REG(hw, GORCH);
  8.3347 +    temp = E1000_READ_REG(hw, GOTCL);
  8.3348 +    temp = E1000_READ_REG(hw, GOTCH);
  8.3349 +    temp = E1000_READ_REG(hw, RNBC);
  8.3350 +    temp = E1000_READ_REG(hw, RUC);
  8.3351 +    temp = E1000_READ_REG(hw, RFC);
  8.3352 +    temp = E1000_READ_REG(hw, ROC);
  8.3353 +    temp = E1000_READ_REG(hw, RJC);
  8.3354 +    temp = E1000_READ_REG(hw, TORL);
  8.3355 +    temp = E1000_READ_REG(hw, TORH);
  8.3356 +    temp = E1000_READ_REG(hw, TOTL);
  8.3357 +    temp = E1000_READ_REG(hw, TOTH);
  8.3358 +    temp = E1000_READ_REG(hw, TPR);
  8.3359 +    temp = E1000_READ_REG(hw, TPT);
  8.3360 +    temp = E1000_READ_REG(hw, PTC64);
  8.3361 +    temp = E1000_READ_REG(hw, PTC127);
  8.3362 +    temp = E1000_READ_REG(hw, PTC255);
  8.3363 +    temp = E1000_READ_REG(hw, PTC511);
  8.3364 +    temp = E1000_READ_REG(hw, PTC1023);
  8.3365 +    temp = E1000_READ_REG(hw, PTC1522);
  8.3366 +    temp = E1000_READ_REG(hw, MPTC);
  8.3367 +    temp = E1000_READ_REG(hw, BPTC);
  8.3368 +
  8.3369 +    if(hw->mac_type < e1000_82543) return;
  8.3370 +
  8.3371 +    temp = E1000_READ_REG(hw, ALGNERRC);
  8.3372 +    temp = E1000_READ_REG(hw, RXERRC);
  8.3373 +    temp = E1000_READ_REG(hw, TNCRS);
  8.3374 +    temp = E1000_READ_REG(hw, CEXTERR);
  8.3375 +    temp = E1000_READ_REG(hw, TSCTC);
  8.3376 +    temp = E1000_READ_REG(hw, TSCTFC);
  8.3377 +
  8.3378 +    if(hw->mac_type <= e1000_82544) return;
  8.3379 +
  8.3380 +    temp = E1000_READ_REG(hw, MGTPRC);
  8.3381 +    temp = E1000_READ_REG(hw, MGTPDC);
  8.3382 +    temp = E1000_READ_REG(hw, MGTPTC);
  8.3383 +}
  8.3384 +
  8.3385 +/******************************************************************************
  8.3386 + * Resets Adaptive IFS to its default state.
  8.3387 + *
  8.3388 + * hw - Struct containing variables accessed by shared code
  8.3389 + *
  8.3390 + * Call this after e1000_init_hw. You may override the IFS defaults by setting
  8.3391 + * hw->ifs_params_forced to TRUE. However, you must initialize hw->
  8.3392 + * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
  8.3393 + * before calling this function.
  8.3394 + *****************************************************************************/
  8.3395 +void
  8.3396 +e1000_reset_adaptive(struct e1000_hw *hw)
  8.3397 +{
  8.3398 +    DEBUGFUNC("e1000_reset_adaptive");
  8.3399 +
  8.3400 +    if(hw->adaptive_ifs) {
  8.3401 +        if(!hw->ifs_params_forced) {
  8.3402 +            hw->current_ifs_val = 0;
  8.3403 +            hw->ifs_min_val = IFS_MIN;
  8.3404 +            hw->ifs_max_val = IFS_MAX;
  8.3405 +            hw->ifs_step_size = IFS_STEP;
  8.3406 +            hw->ifs_ratio = IFS_RATIO;
  8.3407 +        }
  8.3408 +        hw->in_ifs_mode = FALSE;
  8.3409 +        E1000_WRITE_REG(hw, AIT, 0);
  8.3410 +    } else {
  8.3411 +        DEBUGOUT("Not in Adaptive IFS mode!\n");
  8.3412 +    }
  8.3413 +}
  8.3414 +
  8.3415 +/******************************************************************************
  8.3416 + * Called during the callback/watchdog routine to update IFS value based on
  8.3417 + * the ratio of transmits to collisions.
  8.3418 + *
  8.3419 + * hw - Struct containing variables accessed by shared code
  8.3420 + * tx_packets - Number of transmits since last callback
  8.3421 + * total_collisions - Number of collisions since last callback
  8.3422 + *****************************************************************************/
  8.3423 +void
  8.3424 +e1000_update_adaptive(struct e1000_hw *hw)
  8.3425 +{
  8.3426 +    DEBUGFUNC("e1000_update_adaptive");
  8.3427 +
  8.3428 +    if(hw->adaptive_ifs) {
  8.3429 +        if((hw->collision_delta * hw->ifs_ratio) > 
  8.3430 +           hw->tx_packet_delta) {
  8.3431 +            if(hw->tx_packet_delta > MIN_NUM_XMITS) {
  8.3432 +                hw->in_ifs_mode = TRUE;
  8.3433 +                if(hw->current_ifs_val < hw->ifs_max_val) {
  8.3434 +                    if(hw->current_ifs_val == 0)
  8.3435 +                        hw->current_ifs_val = hw->ifs_min_val;
  8.3436 +                    else
  8.3437 +                        hw->current_ifs_val += hw->ifs_step_size;
  8.3438 +                    E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
  8.3439 +                }
  8.3440 +            }
  8.3441 +        } else {
  8.3442 +            if((hw->in_ifs_mode == TRUE) && 
  8.3443 +               (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
  8.3444 +                hw->current_ifs_val = 0;
  8.3445 +                hw->in_ifs_mode = FALSE;
  8.3446 +                E1000_WRITE_REG(hw, AIT, 0);
  8.3447 +            }
  8.3448 +        }
  8.3449 +    } else {
  8.3450 +        DEBUGOUT("Not in Adaptive IFS mode!\n");
  8.3451 +    }
  8.3452 +}
  8.3453 +
  8.3454 +/******************************************************************************
  8.3455 + * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
  8.3456 + * 
  8.3457 + * hw - Struct containing variables accessed by shared code
  8.3458 + * frame_len - The length of the frame in question
  8.3459 + * mac_addr - The Ethernet destination address of the frame in question
  8.3460 + *****************************************************************************/
  8.3461 +void
  8.3462 +e1000_tbi_adjust_stats(struct e1000_hw *hw,
  8.3463 +                       struct e1000_hw_stats *stats,
  8.3464 +                       uint32_t frame_len,
  8.3465 +                       uint8_t *mac_addr)
  8.3466 +{
  8.3467 +    uint64_t carry_bit;
  8.3468 +
  8.3469 +    /* First adjust the frame length. */
  8.3470 +    frame_len--;
  8.3471 +    /* We need to adjust the statistics counters, since the hardware
  8.3472 +     * counters overcount this packet as a CRC error and undercount
  8.3473 +     * the packet as a good packet
  8.3474 +     */
  8.3475 +    /* This packet should not be counted as a CRC error.    */
  8.3476 +    stats->crcerrs--;
  8.3477 +    /* This packet does count as a Good Packet Received.    */
  8.3478 +    stats->gprc++;
  8.3479 +
  8.3480 +    /* Adjust the Good Octets received counters             */
  8.3481 +    carry_bit = 0x80000000 & stats->gorcl;
  8.3482 +    stats->gorcl += frame_len;
  8.3483 +    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
  8.3484 +     * Received Count) was one before the addition, 
  8.3485 +     * AND it is zero after, then we lost the carry out, 
  8.3486 +     * need to add one to Gorch (Good Octets Received Count High).
  8.3487 +     * This could be simplified if all environments supported 
  8.3488 +     * 64-bit integers.
  8.3489 +     */
  8.3490 +    if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
  8.3491 +        stats->gorch++;
  8.3492 +    /* Is this a broadcast or multicast?  Check broadcast first,
  8.3493 +     * since the test for a multicast frame will test positive on 
  8.3494 +     * a broadcast frame.
  8.3495 +     */
  8.3496 +    if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
  8.3497 +        /* Broadcast packet */
  8.3498 +        stats->bprc++;
  8.3499 +    else if(*mac_addr & 0x01)
  8.3500 +        /* Multicast packet */
  8.3501 +        stats->mprc++;
  8.3502 +
  8.3503 +    if(frame_len == hw->max_frame_size) {
  8.3504 +        /* In this case, the hardware has overcounted the number of
  8.3505 +         * oversize frames.
  8.3506 +         */
  8.3507 +        if(stats->roc > 0)
  8.3508 +            stats->roc--;
  8.3509 +    }
  8.3510 +
  8.3511 +    /* Adjust the bin counters when the extra byte put the frame in the
  8.3512 +     * wrong bin. Remember that the frame_len was adjusted above.
  8.3513 +     */
  8.3514 +    if(frame_len == 64) {
  8.3515 +        stats->prc64++;
  8.3516 +        stats->prc127--;
  8.3517 +    } else if(frame_len == 127) {
  8.3518 +        stats->prc127++;
  8.3519 +        stats->prc255--;
  8.3520 +    } else if(frame_len == 255) {
  8.3521 +        stats->prc255++;
  8.3522 +        stats->prc511--;
  8.3523 +    } else if(frame_len == 511) {
  8.3524 +        stats->prc511++;
  8.3525 +        stats->prc1023--;
  8.3526 +    } else if(frame_len == 1023) {
  8.3527 +        stats->prc1023++;
  8.3528 +        stats->prc1522--;
  8.3529 +    } else if(frame_len == 1522) {
  8.3530 +        stats->prc1522++;
  8.3531 +    }
  8.3532 +}
  8.3533 +
  8.3534 +/******************************************************************************
  8.3535 + * Gets the current PCI bus type, speed, and width of the hardware
  8.3536 + *
  8.3537 + * hw - Struct containing variables accessed by shared code
  8.3538 + *****************************************************************************/
  8.3539 +void
  8.3540 +e1000_get_bus_info(struct e1000_hw *hw)
  8.3541 +{
  8.3542 +    uint32_t status;
  8.3543 +
  8.3544 +    if(hw->mac_type < e1000_82543) {
  8.3545 +        hw->bus_type = e1000_bus_type_unknown;
  8.3546 +        hw->bus_speed = e1000_bus_speed_unknown;
  8.3547 +        hw->bus_width = e1000_bus_width_unknown;
  8.3548 +        return;
  8.3549 +    }
  8.3550 +
  8.3551 +    status = E1000_READ_REG(hw, STATUS);
  8.3552 +    hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  8.3553 +                   e1000_bus_type_pcix : e1000_bus_type_pci;
  8.3554 +    if(hw->bus_type == e1000_bus_type_pci) {
  8.3555 +        hw->bus_speed = (status & E1000_STATUS_PCI66) ?
  8.3556 +                        e1000_bus_speed_66 : e1000_bus_speed_33;
  8.3557 +    } else {
  8.3558 +        switch (status & E1000_STATUS_PCIX_SPEED) {
  8.3559 +        case E1000_STATUS_PCIX_SPEED_66:
  8.3560 +            hw->bus_speed = e1000_bus_speed_66;
  8.3561 +            break;
  8.3562 +        case E1000_STATUS_PCIX_SPEED_100:
  8.3563 +            hw->bus_speed = e1000_bus_speed_100;
  8.3564 +            break;
  8.3565 +        case E1000_STATUS_PCIX_SPEED_133:
  8.3566 +            hw->bus_speed = e1000_bus_speed_133;
  8.3567 +            break;
  8.3568 +        default:
  8.3569 +            hw->bus_speed = e1000_bus_speed_reserved;
  8.3570 +            break;
  8.3571 +        }
  8.3572 +    }
  8.3573 +    hw->bus_width = (status & E1000_STATUS_BUS64) ?
  8.3574 +                    e1000_bus_width_64 : e1000_bus_width_32;
  8.3575 +}
  8.3576 +/******************************************************************************
  8.3577 + * Reads a value from one of the devices registers using port I/O (as opposed
  8.3578 + * memory mapped I/O). Only 82544 and newer devices support port I/O.
  8.3579 + *
  8.3580 + * hw - Struct containing variables accessed by shared code
  8.3581 + * offset - offset to read from
  8.3582 + *****************************************************************************/
  8.3583 +uint32_t
  8.3584 +e1000_read_reg_io(struct e1000_hw *hw,
  8.3585 +                  uint32_t offset)
  8.3586 +{
  8.3587 +    uint32_t io_addr = hw->io_base;
  8.3588 +    uint32_t io_data = hw->io_base + 4;
  8.3589 +
  8.3590 +    e1000_io_write(hw, io_addr, offset);
  8.3591 +    return e1000_io_read(hw, io_data);
  8.3592 +}
  8.3593 +
  8.3594 +/******************************************************************************
  8.3595 + * Writes a value to one of the devices registers using port I/O (as opposed to
  8.3596 + * memory mapped I/O). Only 82544 and newer devices support port I/O.
  8.3597 + *
  8.3598 + * hw - Struct containing variables accessed by shared code
  8.3599 + * offset - offset to write to
  8.3600 + * value - value to write
  8.3601 + *****************************************************************************/
  8.3602 +void
  8.3603 +e1000_write_reg_io(struct e1000_hw *hw,
  8.3604 +                   uint32_t offset,
  8.3605 +                   uint32_t value)
  8.3606 +{
  8.3607 +    uint32_t io_addr = hw->io_base;
  8.3608 +    uint32_t io_data = hw->io_base + 4;
  8.3609 +
  8.3610 +    e1000_io_write(hw, io_addr, offset);
  8.3611 +    e1000_io_write(hw, io_data, value);
  8.3612 +}
  8.3613 +
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_hw.h	Sat Feb 08 17:39:26 2003 +0000
     9.3 @@ -0,0 +1,1789 @@
     9.4 +/*******************************************************************************
     9.5 +
     9.6 +  
     9.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     9.8 +  
     9.9 +  This program is free software; you can redistribute it and/or modify it 
    9.10 +  under the terms of the GNU General Public License as published by the Free 
    9.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    9.12 +  any later version.
    9.13 +  
    9.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    9.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    9.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    9.17 +  more details.
    9.18 +  
    9.19 +  You should have received a copy of the GNU General Public License along with
    9.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    9.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    9.22 +  
    9.23 +  The full GNU General Public License is included in this distribution in the
    9.24 +  file called LICENSE.
    9.25 +  
    9.26 +  Contact Information:
    9.27 +  Linux NICS <linux.nics@intel.com>
    9.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    9.29 +
    9.30 +*******************************************************************************/
    9.31 +
    9.32 +/* e1000_hw.h
    9.33 + * Structures, enums, and macros for the MAC
    9.34 + */
    9.35 +
    9.36 +#ifndef _E1000_HW_H_
    9.37 +#define _E1000_HW_H_
    9.38 +
    9.39 +#include "e1000_osdep.h"
    9.40 +
    9.41 +/* Forward declarations of structures used by the shared code */
    9.42 +struct e1000_hw;
    9.43 +struct e1000_hw_stats;
    9.44 +
    9.45 +/* Enumerated types specific to the e1000 hardware */
    9.46 +/* Media Access Controlers */
    9.47 +typedef enum {
    9.48 +    e1000_undefined = 0,
    9.49 +    e1000_82542_rev2_0,
    9.50 +    e1000_82542_rev2_1,
    9.51 +    e1000_82543,
    9.52 +    e1000_82544,
    9.53 +    e1000_82540,
    9.54 +    e1000_82545,
    9.55 +    e1000_82546,
    9.56 +    e1000_num_macs
    9.57 +} e1000_mac_type;
    9.58 +
    9.59 +/* Media Types */
    9.60 +typedef enum {
    9.61 +    e1000_media_type_copper = 0,
    9.62 +    e1000_media_type_fiber = 1,
    9.63 +    e1000_num_media_types
    9.64 +} e1000_media_type;
    9.65 +
    9.66 +typedef enum {
    9.67 +    e1000_10_half = 0,
    9.68 +    e1000_10_full = 1,
    9.69 +    e1000_100_half = 2,
    9.70 +    e1000_100_full = 3
    9.71 +} e1000_speed_duplex_type;
    9.72 +
    9.73 +/* Flow Control Settings */
    9.74 +typedef enum {
    9.75 +    e1000_fc_none = 0,
    9.76 +    e1000_fc_rx_pause = 1,
    9.77 +    e1000_fc_tx_pause = 2,
    9.78 +    e1000_fc_full = 3,
    9.79 +    e1000_fc_default = 0xFF
    9.80 +} e1000_fc_type;
    9.81 +
    9.82 +/* PCI bus types */
    9.83 +typedef enum {
    9.84 +    e1000_bus_type_unknown = 0,
    9.85 +    e1000_bus_type_pci,
    9.86 +    e1000_bus_type_pcix
    9.87 +} e1000_bus_type;
    9.88 +
    9.89 +/* PCI bus speeds */
    9.90 +typedef enum {
    9.91 +    e1000_bus_speed_unknown = 0,
    9.92 +    e1000_bus_speed_33,
    9.93 +    e1000_bus_speed_66,
    9.94 +    e1000_bus_speed_100,
    9.95 +    e1000_bus_speed_133,
    9.96 +    e1000_bus_speed_reserved
    9.97 +} e1000_bus_speed;
    9.98 +
    9.99 +/* PCI bus widths */
   9.100 +typedef enum {
   9.101 +    e1000_bus_width_unknown = 0,
   9.102 +    e1000_bus_width_32,
   9.103 +    e1000_bus_width_64
   9.104 +} e1000_bus_width;
   9.105 +
   9.106 +/* PHY status info structure and supporting enums */
   9.107 +typedef enum {
   9.108 +    e1000_cable_length_50 = 0,
   9.109 +    e1000_cable_length_50_80,
   9.110 +    e1000_cable_length_80_110,
   9.111 +    e1000_cable_length_110_140,
   9.112 +    e1000_cable_length_140,
   9.113 +    e1000_cable_length_undefined = 0xFF
   9.114 +} e1000_cable_length;
   9.115 +
   9.116 +typedef enum {
   9.117 +    e1000_10bt_ext_dist_enable_normal = 0,
   9.118 +    e1000_10bt_ext_dist_enable_lower,
   9.119 +    e1000_10bt_ext_dist_enable_undefined = 0xFF
   9.120 +} e1000_10bt_ext_dist_enable;
   9.121 +
   9.122 +typedef enum {
   9.123 +    e1000_rev_polarity_normal = 0,
   9.124 +    e1000_rev_polarity_reversed,
   9.125 +    e1000_rev_polarity_undefined = 0xFF
   9.126 +} e1000_rev_polarity;
   9.127 +
   9.128 +typedef enum {
   9.129 +    e1000_polarity_reversal_enabled = 0,
   9.130 +    e1000_polarity_reversal_disabled,
   9.131 +    e1000_polarity_reversal_undefined = 0xFF
   9.132 +} e1000_polarity_reversal;
   9.133 +
   9.134 +typedef enum {
   9.135 +    e1000_auto_x_mode_manual_mdi = 0,
   9.136 +    e1000_auto_x_mode_manual_mdix,
   9.137 +    e1000_auto_x_mode_auto1,
   9.138 +    e1000_auto_x_mode_auto2,
   9.139 +    e1000_auto_x_mode_undefined = 0xFF
   9.140 +} e1000_auto_x_mode;
   9.141 +
   9.142 +typedef enum {
   9.143 +    e1000_1000t_rx_status_not_ok = 0,
   9.144 +    e1000_1000t_rx_status_ok,
   9.145 +    e1000_1000t_rx_status_undefined = 0xFF
   9.146 +} e1000_1000t_rx_status;
   9.147 +
   9.148 +struct e1000_phy_info {
   9.149 +    e1000_cable_length cable_length;
   9.150 +    e1000_10bt_ext_dist_enable extended_10bt_distance;
   9.151 +    e1000_rev_polarity cable_polarity;
   9.152 +    e1000_polarity_reversal polarity_correction;
   9.153 +    e1000_auto_x_mode mdix_mode;
   9.154 +    e1000_1000t_rx_status local_rx;
   9.155 +    e1000_1000t_rx_status remote_rx;
   9.156 +};
   9.157 +
   9.158 +struct e1000_phy_stats {
   9.159 +    uint32_t idle_errors;
   9.160 +    uint32_t receive_errors;
   9.161 +};
   9.162 +
   9.163 +
   9.164 +
   9.165 +/* Error Codes */
   9.166 +#define E1000_SUCCESS      0
   9.167 +#define E1000_ERR_EEPROM   1
   9.168 +#define E1000_ERR_PHY      2
   9.169 +#define E1000_ERR_CONFIG   3
   9.170 +#define E1000_ERR_PARAM    4
   9.171 +#define E1000_ERR_MAC_TYPE 5
   9.172 +
   9.173 +/* Function prototypes */
   9.174 +/* Initialization */
   9.175 +void e1000_reset_hw(struct e1000_hw *hw);
   9.176 +int32_t e1000_init_hw(struct e1000_hw *hw);
   9.177 +int32_t e1000_set_mac_type(struct e1000_hw *hw);
   9.178 +
   9.179 +/* Link Configuration */
   9.180 +int32_t e1000_setup_link(struct e1000_hw *hw);
   9.181 +int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
   9.182 +void e1000_config_collision_dist(struct e1000_hw *hw);
   9.183 +int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
   9.184 +int32_t e1000_check_for_link(struct e1000_hw *hw);
   9.185 +void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
   9.186 +int32_t e1000_wait_autoneg(struct e1000_hw *hw);
   9.187 +
   9.188 +/* PHY */
   9.189 +int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
   9.190 +int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
   9.191 +void e1000_phy_hw_reset(struct e1000_hw *hw);
   9.192 +int32_t e1000_phy_reset(struct e1000_hw *hw);
   9.193 +int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
   9.194 +int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
   9.195 +int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
   9.196 +
   9.197 +/* EEPROM Functions */
   9.198 +int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t *data);
   9.199 +int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
   9.200 +int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
   9.201 +int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t data);
   9.202 +int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
   9.203 +int32_t e1000_read_mac_addr(struct e1000_hw * hw);
   9.204 +
   9.205 +/* Filters (multicast, vlan, receive) */
   9.206 +void e1000_init_rx_addrs(struct e1000_hw *hw);
   9.207 +void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
   9.208 +uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
   9.209 +void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
   9.210 +void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
   9.211 +void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
   9.212 +void e1000_clear_vfta(struct e1000_hw *hw);
   9.213 +
   9.214 +/* LED functions */
   9.215 +int32_t e1000_setup_led(struct e1000_hw *hw);
   9.216 +int32_t e1000_cleanup_led(struct e1000_hw *hw);
   9.217 +int32_t e1000_led_on(struct e1000_hw *hw);
   9.218 +int32_t e1000_led_off(struct e1000_hw *hw);
   9.219 +
   9.220 +/* Adaptive IFS Functions */
   9.221 +
   9.222 +/* Everything else */
   9.223 +void e1000_clear_hw_cntrs(struct e1000_hw *hw);
   9.224 +void e1000_reset_adaptive(struct e1000_hw *hw);
   9.225 +void e1000_update_adaptive(struct e1000_hw *hw);
   9.226 +void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
   9.227 +void e1000_get_bus_info(struct e1000_hw *hw);
   9.228 +void e1000_pci_set_mwi(struct e1000_hw *hw);
   9.229 +void e1000_pci_clear_mwi(struct e1000_hw *hw);
   9.230 +void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
   9.231 +void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
   9.232 +/* Port I/O is only supported on 82544 and newer */
   9.233 +uint32_t e1000_io_read(struct e1000_hw *hw, uint32_t port);
   9.234 +uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
   9.235 +void e1000_io_write(struct e1000_hw *hw, uint32_t port, uint32_t value);
   9.236 +void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
   9.237 +#define E1000_READ_REG_IO(a, reg) \
   9.238 +    e1000_read_reg_io((a), E1000_##reg)
   9.239 +#define E1000_WRITE_REG_IO(a, reg, val) \
   9.240 +    e1000_write_reg_io((a), E1000_##reg, val)
   9.241 +
   9.242 +/* PCI Device IDs */
   9.243 +#define E1000_DEV_ID_82542               0x1000
   9.244 +#define E1000_DEV_ID_82543GC_FIBER       0x1001
   9.245 +#define E1000_DEV_ID_82543GC_COPPER      0x1004
   9.246 +#define E1000_DEV_ID_82544EI_COPPER      0x1008
   9.247 +#define E1000_DEV_ID_82544EI_FIBER       0x1009
   9.248 +#define E1000_DEV_ID_82544GC_COPPER      0x100C
   9.249 +#define E1000_DEV_ID_82544GC_LOM         0x100D
   9.250 +#define E1000_DEV_ID_82540EM             0x100E
   9.251 +#define E1000_DEV_ID_82540EM_LOM         0x1015
   9.252 +#define E1000_DEV_ID_82540EP_LOM         0x1016
   9.253 +#define E1000_DEV_ID_82540EP             0x1017
   9.254 +#define E1000_DEV_ID_82540EP_LP          0x101E
   9.255 +#define E1000_DEV_ID_82545EM_COPPER      0x100F
   9.256 +#define E1000_DEV_ID_82545EM_FIBER       0x1011
   9.257 +#define E1000_DEV_ID_82546EB_COPPER      0x1010
   9.258 +#define E1000_DEV_ID_82546EB_FIBER       0x1012
   9.259 +#define NUM_DEV_IDS 16
   9.260 +
   9.261 +#define NODE_ADDRESS_SIZE 6
   9.262 +#define ETH_LENGTH_OF_ADDRESS 6
   9.263 +
   9.264 +/* MAC decode size is 128K - This is the size of BAR0 */
   9.265 +#define MAC_DECODE_SIZE (128 * 1024)
   9.266 +
   9.267 +#define E1000_82542_2_0_REV_ID 2
   9.268 +#define E1000_82542_2_1_REV_ID 3
   9.269 +
   9.270 +#define SPEED_10    10
   9.271 +#define SPEED_100   100
   9.272 +#define SPEED_1000  1000
   9.273 +#define HALF_DUPLEX 1
   9.274 +#define FULL_DUPLEX 2
   9.275 +
   9.276 +/* The sizes (in bytes) of a ethernet packet */
   9.277 +#define ENET_HEADER_SIZE             14
   9.278 +#define MAXIMUM_ETHERNET_FRAME_SIZE  1518 /* With FCS */
   9.279 +#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
   9.280 +#define ETHERNET_FCS_SIZE            4
   9.281 +#define MAXIMUM_ETHERNET_PACKET_SIZE \
   9.282 +    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
   9.283 +#define MINIMUM_ETHERNET_PACKET_SIZE \
   9.284 +    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
   9.285 +#define CRC_LENGTH                   ETHERNET_FCS_SIZE
   9.286 +#define MAX_JUMBO_FRAME_SIZE         0x3F00
   9.287 +
   9.288 +
   9.289 +/* 802.1q VLAN Packet Sizes */
   9.290 +#define VLAN_TAG_SIZE                     4     /* 802.3ac tag (not DMAed) */
   9.291 +
   9.292 +/* Ethertype field values */
   9.293 +#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
   9.294 +#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
   9.295 +#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
   9.296 +
   9.297 +/* Packet Header defines */
   9.298 +#define IP_PROTOCOL_TCP    6
   9.299 +#define IP_PROTOCOL_UDP    0x11
   9.300 +
   9.301 +/* This defines the bits that are set in the Interrupt Mask
   9.302 + * Set/Read Register.  Each bit is documented below:
   9.303 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
   9.304 + *   o RXSEQ  = Receive Sequence Error 
   9.305 + */
   9.306 +#define POLL_IMS_ENABLE_MASK ( \
   9.307 +    E1000_IMS_RXDMT0 |         \
   9.308 +    E1000_IMS_RXSEQ)
   9.309 +
   9.310 +/* This defines the bits that are set in the Interrupt Mask
   9.311 + * Set/Read Register.  Each bit is documented below:
   9.312 + *   o RXT0   = Receiver Timer Interrupt (ring 0)
   9.313 + *   o TXDW   = Transmit Descriptor Written Back
   9.314 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
   9.315 + *   o RXSEQ  = Receive Sequence Error
   9.316 + *   o LSC    = Link Status Change
   9.317 + */
   9.318 +#define IMS_ENABLE_MASK ( \
   9.319 +    E1000_IMS_RXT0   |    \
   9.320 +    E1000_IMS_TXDW   |    \
   9.321 +    E1000_IMS_RXDMT0 |    \
   9.322 +    E1000_IMS_RXSEQ  |    \
   9.323 +    E1000_IMS_LSC)
   9.324 +
   9.325 +/* The number of high/low register pairs in the RAR. The RAR (Receive Address
   9.326 + * Registers) holds the directed and multicast addresses that we monitor. We
   9.327 + * reserve one of these spots for our directed address, allowing us room for
   9.328 + * E1000_RAR_ENTRIES - 1 multicast addresses. 
   9.329 + */
   9.330 +#define E1000_RAR_ENTRIES 16
   9.331 +
   9.332 +#define MIN_NUMBER_OF_DESCRIPTORS 8
   9.333 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
   9.334 +
   9.335 +/* Receive Descriptor */
   9.336 +struct e1000_rx_desc {
   9.337 +    uint64_t buffer_addr; /* Address of the descriptor's data buffer */
   9.338 +    uint16_t length;     /* Length of data DMAed into data buffer */
   9.339 +    uint16_t csum;       /* Packet checksum */
   9.340 +    uint8_t status;      /* Descriptor status */
   9.341 +    uint8_t errors;      /* Descriptor Errors */
   9.342 +    uint16_t special;
   9.343 +};
   9.344 +
   9.345 +/* Receive Decriptor bit definitions */
   9.346 +#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
   9.347 +#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
   9.348 +#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
   9.349 +#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
   9.350 +#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
   9.351 +#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
   9.352 +#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
   9.353 +#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
   9.354 +#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
   9.355 +#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
   9.356 +#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
   9.357 +#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
   9.358 +#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
   9.359 +#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
   9.360 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
   9.361 +#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
   9.362 +#define E1000_RXD_SPC_PRI_SHIFT 0x000D  /* Priority is in upper 3 of 16 */
   9.363 +#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
   9.364 +#define E1000_RXD_SPC_CFI_SHIFT 0x000C  /* CFI is bit 12 */
   9.365 +
   9.366 +/* mask to determine if packets should be dropped due to frame errors */
   9.367 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
   9.368 +    E1000_RXD_ERR_CE  |                \
   9.369 +    E1000_RXD_ERR_SE  |                \
   9.370 +    E1000_RXD_ERR_SEQ |                \
   9.371 +    E1000_RXD_ERR_CXE |                \
   9.372 +    E1000_RXD_ERR_RXE)
   9.373 +
   9.374 +/* Transmit Descriptor */
   9.375 +struct e1000_tx_desc {
   9.376 +    uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
   9.377 +    union {
   9.378 +        uint32_t data;
   9.379 +        struct {
   9.380 +            uint16_t length;    /* Data buffer length */
   9.381 +            uint8_t cso;        /* Checksum offset */
   9.382 +            uint8_t cmd;        /* Descriptor control */
   9.383 +        } flags;
   9.384 +    } lower;
   9.385 +    union {
   9.386 +        uint32_t data;
   9.387 +        struct {
   9.388 +            uint8_t status;     /* Descriptor status */
   9.389 +            uint8_t css;        /* Checksum start */
   9.390 +            uint16_t special;
   9.391 +        } fields;
   9.392 +    } upper;
   9.393 +};
   9.394 +
   9.395 +/* Transmit Descriptor bit definitions */
   9.396 +#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
   9.397 +#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
   9.398 +#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
   9.399 +#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
   9.400 +#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
   9.401 +#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
   9.402 +#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
   9.403 +#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
   9.404 +#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
   9.405 +#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
   9.406 +#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
   9.407 +#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
   9.408 +#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
   9.409 +#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
   9.410 +#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
   9.411 +#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
   9.412 +#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
   9.413 +#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
   9.414 +#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
   9.415 +#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
   9.416 +
   9.417 +/* Offload Context Descriptor */
   9.418 +struct e1000_context_desc {
   9.419 +    union {
   9.420 +        uint32_t ip_config;
   9.421 +        struct {
   9.422 +            uint8_t ipcss;      /* IP checksum start */
   9.423 +            uint8_t ipcso;      /* IP checksum offset */
   9.424 +            uint16_t ipcse;     /* IP checksum end */
   9.425 +        } ip_fields;
   9.426 +    } lower_setup;
   9.427 +    union {
   9.428 +        uint32_t tcp_config;
   9.429 +        struct {
   9.430 +            uint8_t tucss;      /* TCP checksum start */
   9.431 +            uint8_t tucso;      /* TCP checksum offset */
   9.432 +            uint16_t tucse;     /* TCP checksum end */
   9.433 +        } tcp_fields;
   9.434 +    } upper_setup;
   9.435 +    uint32_t cmd_and_length;    /* */
   9.436 +    union {
   9.437 +        uint32_t data;
   9.438 +        struct {
   9.439 +            uint8_t status;     /* Descriptor status */
   9.440 +            uint8_t hdr_len;    /* Header length */
   9.441 +            uint16_t mss;       /* Maximum segment size */
   9.442 +        } fields;
   9.443 +    } tcp_seg_setup;
   9.444 +};
   9.445 +
   9.446 +/* Offload data descriptor */
   9.447 +struct e1000_data_desc {
   9.448 +    uint64_t buffer_addr;       /* Address of the descriptor's buffer address */
   9.449 +    union {
   9.450 +        uint32_t data;
   9.451 +        struct {
   9.452 +            uint16_t length;    /* Data buffer length */
   9.453 +            uint8_t typ_len_ext;        /* */
   9.454 +            uint8_t cmd;        /* */
   9.455 +        } flags;
   9.456 +    } lower;
   9.457 +    union {
   9.458 +        uint32_t data;
   9.459 +        struct {
   9.460 +            uint8_t status;     /* Descriptor status */
   9.461 +            uint8_t popts;      /* Packet Options */
   9.462 +            uint16_t special;   /* */
   9.463 +        } fields;
   9.464 +    } upper;
   9.465 +};
   9.466 +
   9.467 +/* Filters */
   9.468 +#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
   9.469 +#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
   9.470 +#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
   9.471 +
   9.472 +
   9.473 +/* Receive Address Register */
   9.474 +struct e1000_rar {
   9.475 +    volatile uint32_t low;      /* receive address low */
   9.476 +    volatile uint32_t high;     /* receive address high */
   9.477 +};
   9.478 +
   9.479 +/* The number of entries in the Multicast Table Array (MTA). */
   9.480 +#define E1000_NUM_MTA_REGISTERS 128
   9.481 +
   9.482 +/* IPv4 Address Table Entry */
   9.483 +struct e1000_ipv4_at_entry {
   9.484 +    volatile uint32_t ipv4_addr;        /* IP Address (RW) */
   9.485 +    volatile uint32_t reserved;
   9.486 +};
   9.487 +
   9.488 +/* Four wakeup IP addresses are supported */
   9.489 +#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
   9.490 +#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
   9.491 +#define E1000_IP6AT_SIZE                  1
   9.492 +
   9.493 +/* IPv6 Address Table Entry */
   9.494 +struct e1000_ipv6_at_entry {
   9.495 +    volatile uint8_t ipv6_addr[16];
   9.496 +};
   9.497 +
   9.498 +/* Flexible Filter Length Table Entry */
   9.499 +struct e1000_fflt_entry {
   9.500 +    volatile uint32_t length;   /* Flexible Filter Length (RW) */
   9.501 +    volatile uint32_t reserved;
   9.502 +};
   9.503 +
   9.504 +/* Flexible Filter Mask Table Entry */
   9.505 +struct e1000_ffmt_entry {
   9.506 +    volatile uint32_t mask;     /* Flexible Filter Mask (RW) */
   9.507 +    volatile uint32_t reserved;
   9.508 +};
   9.509 +
   9.510 +/* Flexible Filter Value Table Entry */
   9.511 +struct e1000_ffvt_entry {
   9.512 +    volatile uint32_t value;    /* Flexible Filter Value (RW) */
   9.513 +    volatile uint32_t reserved;
   9.514 +};
   9.515 +
   9.516 +/* Four Flexible Filters are supported */
   9.517 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
   9.518 +
   9.519 +/* Each Flexible Filter is at most 128 (0x80) bytes in length */
   9.520 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
   9.521 +
   9.522 +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
   9.523 +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
   9.524 +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
   9.525 +
   9.526 +/* Register Set. (82543, 82544)
   9.527 + *
   9.528 + * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
   9.529 + * These registers are physically located on the NIC, but are mapped into the 
   9.530 + * host memory address space.
   9.531 + *
   9.532 + * RW - register is both readable and writable
   9.533 + * RO - register is read only
   9.534 + * WO - register is write only
   9.535 + * R/clr - register is read only and is cleared when read
   9.536 + * A - register array
   9.537 + */
   9.538 +#define E1000_CTRL     0x00000  /* Device Control - RW */
   9.539 +#define E1000_STATUS   0x00008  /* Device Status - RO */
   9.540 +#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
   9.541 +#define E1000_EERD     0x00014  /* EEPROM Read - RW */
   9.542 +#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
   9.543 +#define E1000_MDIC     0x00020  /* MDI Control - RW */
   9.544 +#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
   9.545 +#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
   9.546 +#define E1000_FCT      0x00030  /* Flow Control Type - RW */
   9.547 +#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
   9.548 +#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
   9.549 +#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
   9.550 +#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
   9.551 +#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
   9.552 +#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
   9.553 +#define E1000_RCTL     0x00100  /* RX Control - RW */
   9.554 +#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
   9.555 +#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
   9.556 +#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
   9.557 +#define E1000_TCTL     0x00400  /* TX Control - RW */
   9.558 +#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
   9.559 +#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
   9.560 +#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
   9.561 +#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
   9.562 +#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
   9.563 +#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
   9.564 +#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
   9.565 +#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
   9.566 +#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
   9.567 +#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
   9.568 +#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
   9.569 +#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
   9.570 +#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
   9.571 +#define E1000_RXDCTL   0x02828  /* RX Descriptor Control - RW */
   9.572 +#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
   9.573 +#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
   9.574 +#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
   9.575 +#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
   9.576 +#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
   9.577 +#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
   9.578 +#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
   9.579 +#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
   9.580 +#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
   9.581 +#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
   9.582 +#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
   9.583 +#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
   9.584 +#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
   9.585 +#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
   9.586 +#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
   9.587 +#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
   9.588 +#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
   9.589 +#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
   9.590 +#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
   9.591 +#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
   9.592 +#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
   9.593 +#define E1000_COLC     0x04028  /* Collision Count - R/clr */
   9.594 +#define E1000_DC       0x04030  /* Defer Count - R/clr */
   9.595 +#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
   9.596 +#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
   9.597 +#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
   9.598 +#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
   9.599 +#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
   9.600 +#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
   9.601 +#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
   9.602 +#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
   9.603 +#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
   9.604 +#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
   9.605 +#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
   9.606 +#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
   9.607 +#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
   9.608 +#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
   9.609 +#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
   9.610 +#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
   9.611 +#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
   9.612 +#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
   9.613 +#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
   9.614 +#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
   9.615 +#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
   9.616 +#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
   9.617 +#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
   9.618 +#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
   9.619 +#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
   9.620 +#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
   9.621 +#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
   9.622 +#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
   9.623 +#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
   9.624 +#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
   9.625 +#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
   9.626 +#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
   9.627 +#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
   9.628 +#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
   9.629 +#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
   9.630 +#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
   9.631 +#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
   9.632 +#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
   9.633 +#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
   9.634 +#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
   9.635 +#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
   9.636 +#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
   9.637 +#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
   9.638 +#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
   9.639 +#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
   9.640 +#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
   9.641 +#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
   9.642 +#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
   9.643 +#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
   9.644 +#define E1000_RA       0x05400  /* Receive Address - RW Array */
   9.645 +#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
   9.646 +#define E1000_WUC      0x05800  /* Wakeup Control - RW */
   9.647 +#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
   9.648 +#define E1000_WUS      0x05810  /* Wakeup Status - RO */
   9.649 +#define E1000_MANC     0x05820  /* Management Control - RW */
   9.650 +#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
   9.651 +#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
   9.652 +#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
   9.653 +#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
   9.654 +#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
   9.655 +#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
   9.656 +#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
   9.657 +#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
   9.658 +
   9.659 +/* Register Set (82542)
   9.660 + *
   9.661 + * Some of the 82542 registers are located at different offsets than they are
   9.662 + * in more current versions of the 8254x. Despite the difference in location,
   9.663 + * the registers function in the same manner.
   9.664 + */
   9.665 +#define E1000_82542_CTRL     E1000_CTRL
   9.666 +#define E1000_82542_STATUS   E1000_STATUS
   9.667 +#define E1000_82542_EECD     E1000_EECD
   9.668 +#define E1000_82542_EERD     E1000_EERD
   9.669 +#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
   9.670 +#define E1000_82542_MDIC     E1000_MDIC
   9.671 +#define E1000_82542_FCAL     E1000_FCAL
   9.672 +#define E1000_82542_FCAH     E1000_FCAH
   9.673 +#define E1000_82542_FCT      E1000_FCT
   9.674 +#define E1000_82542_VET      E1000_VET
   9.675 +#define E1000_82542_RA       0x00040
   9.676 +#define E1000_82542_ICR      E1000_ICR
   9.677 +#define E1000_82542_ITR      E1000_ITR
   9.678 +#define E1000_82542_ICS      E1000_ICS
   9.679 +#define E1000_82542_IMS      E1000_IMS
   9.680 +#define E1000_82542_IMC      E1000_IMC
   9.681 +#define E1000_82542_RCTL     E1000_RCTL
   9.682 +#define E1000_82542_RDTR     0x00108
   9.683 +#define E1000_82542_RDBAL    0x00110
   9.684 +#define E1000_82542_RDBAH    0x00114
   9.685 +#define E1000_82542_RDLEN    0x00118
   9.686 +#define E1000_82542_RDH      0x00120
   9.687 +#define E1000_82542_RDT      0x00128
   9.688 +#define E1000_82542_FCRTH    0x00160
   9.689 +#define E1000_82542_FCRTL    0x00168
   9.690 +#define E1000_82542_FCTTV    E1000_FCTTV
   9.691 +#define E1000_82542_TXCW     E1000_TXCW
   9.692 +#define E1000_82542_RXCW     E1000_RXCW
   9.693 +#define E1000_82542_MTA      0x00200
   9.694 +#define E1000_82542_TCTL     E1000_TCTL
   9.695 +#define E1000_82542_TIPG     E1000_TIPG
   9.696 +#define E1000_82542_TDBAL    0x00420
   9.697 +#define E1000_82542_TDBAH    0x00424
   9.698 +#define E1000_82542_TDLEN    0x00428
   9.699 +#define E1000_82542_TDH      0x00430
   9.700 +#define E1000_82542_TDT      0x00438
   9.701 +#define E1000_82542_TIDV     0x00440
   9.702 +#define E1000_82542_TBT      E1000_TBT
   9.703 +#define E1000_82542_AIT      E1000_AIT
   9.704 +#define E1000_82542_VFTA     0x00600
   9.705 +#define E1000_82542_LEDCTL   E1000_LEDCTL
   9.706 +#define E1000_82542_PBA      E1000_PBA
   9.707 +#define E1000_82542_RXDCTL   E1000_RXDCTL
   9.708 +#define E1000_82542_RADV     E1000_RADV
   9.709 +#define E1000_82542_RSRPD    E1000_RSRPD
   9.710 +#define E1000_82542_TXDMAC   E1000_TXDMAC
   9.711 +#define E1000_82542_TXDCTL   E1000_TXDCTL
   9.712 +#define E1000_82542_TADV     E1000_TADV
   9.713 +#define E1000_82542_TSPMT    E1000_TSPMT
   9.714 +#define E1000_82542_CRCERRS  E1000_CRCERRS
   9.715 +#define E1000_82542_ALGNERRC E1000_ALGNERRC
   9.716 +#define E1000_82542_SYMERRS  E1000_SYMERRS
   9.717 +#define E1000_82542_RXERRC   E1000_RXERRC
   9.718 +#define E1000_82542_MPC      E1000_MPC
   9.719 +#define E1000_82542_SCC      E1000_SCC
   9.720 +#define E1000_82542_ECOL     E1000_ECOL
   9.721 +#define E1000_82542_MCC      E1000_MCC
   9.722 +#define E1000_82542_LATECOL  E1000_LATECOL
   9.723 +#define E1000_82542_COLC     E1000_COLC
   9.724 +#define E1000_82542_DC       E1000_DC
   9.725 +#define E1000_82542_TNCRS    E1000_TNCRS
   9.726 +#define E1000_82542_SEC      E1000_SEC
   9.727 +#define E1000_82542_CEXTERR  E1000_CEXTERR
   9.728 +#define E1000_82542_RLEC     E1000_RLEC
   9.729 +#define E1000_82542_XONRXC   E1000_XONRXC
   9.730 +#define E1000_82542_XONTXC   E1000_XONTXC
   9.731 +#define E1000_82542_XOFFRXC  E1000_XOFFRXC
   9.732 +#define E1000_82542_XOFFTXC  E1000_XOFFTXC
   9.733 +#define E1000_82542_FCRUC    E1000_FCRUC
   9.734 +#define E1000_82542_PRC64    E1000_PRC64
   9.735 +#define E1000_82542_PRC127   E1000_PRC127
   9.736 +#define E1000_82542_PRC255   E1000_PRC255
   9.737 +#define E1000_82542_PRC511   E1000_PRC511
   9.738 +#define E1000_82542_PRC1023  E1000_PRC1023
   9.739 +#define E1000_82542_PRC1522  E1000_PRC1522
   9.740 +#define E1000_82542_GPRC     E1000_GPRC
   9.741 +#define E1000_82542_BPRC     E1000_BPRC
   9.742 +#define E1000_82542_MPRC     E1000_MPRC
   9.743 +#define E1000_82542_GPTC     E1000_GPTC
   9.744 +#define E1000_82542_GORCL    E1000_GORCL
   9.745 +#define E1000_82542_GORCH    E1000_GORCH
   9.746 +#define E1000_82542_GOTCL    E1000_GOTCL
   9.747 +#define E1000_82542_GOTCH    E1000_GOTCH
   9.748 +#define E1000_82542_RNBC     E1000_RNBC
   9.749 +#define E1000_82542_RUC      E1000_RUC
   9.750 +#define E1000_82542_RFC      E1000_RFC
   9.751 +#define E1000_82542_ROC      E1000_ROC
   9.752 +#define E1000_82542_RJC      E1000_RJC
   9.753 +#define E1000_82542_MGTPRC   E1000_MGTPRC
   9.754 +#define E1000_82542_MGTPDC   E1000_MGTPDC
   9.755 +#define E1000_82542_MGTPTC   E1000_MGTPTC
   9.756 +#define E1000_82542_TORL     E1000_TORL
   9.757 +#define E1000_82542_TORH     E1000_TORH
   9.758 +#define E1000_82542_TOTL     E1000_TOTL
   9.759 +#define E1000_82542_TOTH     E1000_TOTH
   9.760 +#define E1000_82542_TPR      E1000_TPR
   9.761 +#define E1000_82542_TPT      E1000_TPT
   9.762 +#define E1000_82542_PTC64    E1000_PTC64
   9.763 +#define E1000_82542_PTC127   E1000_PTC127
   9.764 +#define E1000_82542_PTC255   E1000_PTC255
   9.765 +#define E1000_82542_PTC511   E1000_PTC511
   9.766 +#define E1000_82542_PTC1023  E1000_PTC1023
   9.767 +#define E1000_82542_PTC1522  E1000_PTC1522
   9.768 +#define E1000_82542_MPTC     E1000_MPTC
   9.769 +#define E1000_82542_BPTC     E1000_BPTC
   9.770 +#define E1000_82542_TSCTC    E1000_TSCTC
   9.771 +#define E1000_82542_TSCTFC   E1000_TSCTFC
   9.772 +#define E1000_82542_RXCSUM   E1000_RXCSUM
   9.773 +#define E1000_82542_WUC      E1000_WUC
   9.774 +#define E1000_82542_WUFC     E1000_WUFC
   9.775 +#define E1000_82542_WUS      E1000_WUS
   9.776 +#define E1000_82542_MANC     E1000_MANC
   9.777 +#define E1000_82542_IPAV     E1000_IPAV
   9.778 +#define E1000_82542_IP4AT    E1000_IP4AT
   9.779 +#define E1000_82542_IP6AT    E1000_IP6AT
   9.780 +#define E1000_82542_WUPL     E1000_WUPL
   9.781 +#define E1000_82542_WUPM     E1000_WUPM
   9.782 +#define E1000_82542_FFLT     E1000_FFLT
   9.783 +#define E1000_82542_FFMT     E1000_FFMT
   9.784 +#define E1000_82542_FFVT     E1000_FFVT
   9.785 +
   9.786 +/* Statistics counters collected by the MAC */
   9.787 +struct e1000_hw_stats {
   9.788 +    uint64_t crcerrs;
   9.789 +    uint64_t algnerrc;
   9.790 +    uint64_t symerrs;
   9.791 +    uint64_t rxerrc;
   9.792 +    uint64_t mpc;
   9.793 +    uint64_t scc;
   9.794 +    uint64_t ecol;
   9.795 +    uint64_t mcc;
   9.796 +    uint64_t latecol;
   9.797 +    uint64_t colc;
   9.798 +    uint64_t dc;
   9.799 +    uint64_t tncrs;
   9.800 +    uint64_t sec;
   9.801 +    uint64_t cexterr;
   9.802 +    uint64_t rlec;
   9.803 +    uint64_t xonrxc;
   9.804 +    uint64_t xontxc;
   9.805 +    uint64_t xoffrxc;
   9.806 +    uint64_t xofftxc;
   9.807 +    uint64_t fcruc;
   9.808 +    uint64_t prc64;
   9.809 +    uint64_t prc127;
   9.810 +    uint64_t prc255;
   9.811 +    uint64_t prc511;
   9.812 +    uint64_t prc1023;
   9.813 +    uint64_t prc1522;
   9.814 +    uint64_t gprc;
   9.815 +    uint64_t bprc;
   9.816 +    uint64_t mprc;
   9.817 +    uint64_t gptc;
   9.818 +    uint64_t gorcl;
   9.819 +    uint64_t gorch;
   9.820 +    uint64_t gotcl;
   9.821 +    uint64_t gotch;
   9.822 +    uint64_t rnbc;
   9.823 +    uint64_t ruc;
   9.824 +    uint64_t rfc;
   9.825 +    uint64_t roc;
   9.826 +    uint64_t rjc;
   9.827 +    uint64_t mgprc;
   9.828 +    uint64_t mgpdc;
   9.829 +    uint64_t mgptc;
   9.830 +    uint64_t torl;
   9.831 +    uint64_t torh;
   9.832 +    uint64_t totl;
   9.833 +    uint64_t toth;
   9.834 +    uint64_t tpr;
   9.835 +    uint64_t tpt;
   9.836 +    uint64_t ptc64;
   9.837 +    uint64_t ptc127;
   9.838 +    uint64_t ptc255;
   9.839 +    uint64_t ptc511;
   9.840 +    uint64_t ptc1023;
   9.841 +    uint64_t ptc1522;
   9.842 +    uint64_t mptc;
   9.843 +    uint64_t bptc;
   9.844 +    uint64_t tsctc;
   9.845 +    uint64_t tsctfc;
   9.846 +};
   9.847 +
   9.848 +/* Structure containing variables used by the shared code (e1000_hw.c) */
   9.849 +struct e1000_hw {
   9.850 +    uint8_t *hw_addr;
   9.851 +    e1000_mac_type mac_type;
   9.852 +    e1000_media_type media_type;
   9.853 +    void *back;
   9.854 +    e1000_fc_type fc;
   9.855 +    e1000_bus_speed bus_speed;
   9.856 +    e1000_bus_width bus_width;
   9.857 +    e1000_bus_type bus_type;
   9.858 +    uint32_t io_base;
   9.859 +    uint32_t phy_id;
   9.860 +    uint32_t phy_revision;
   9.861 +    uint32_t phy_addr;
   9.862 +    uint32_t original_fc;
   9.863 +    uint32_t txcw;
   9.864 +    uint32_t autoneg_failed;
   9.865 +    uint32_t max_frame_size;
   9.866 +    uint32_t min_frame_size;
   9.867 +    uint32_t mc_filter_type;
   9.868 +    uint32_t num_mc_addrs;
   9.869 +    uint32_t collision_delta;
   9.870 +    uint32_t tx_packet_delta;
   9.871 +    uint32_t ledctl_default;
   9.872 +    uint32_t ledctl_mode1;
   9.873 +    uint32_t ledctl_mode2;
   9.874 +    uint16_t autoneg_advertised;
   9.875 +    uint16_t pci_cmd_word;
   9.876 +    uint16_t fc_high_water;
   9.877 +    uint16_t fc_low_water;
   9.878 +    uint16_t fc_pause_time;
   9.879 +    uint16_t current_ifs_val;
   9.880 +    uint16_t ifs_min_val;
   9.881 +    uint16_t ifs_max_val;
   9.882 +    uint16_t ifs_step_size;
   9.883 +    uint16_t ifs_ratio;
   9.884 +    uint16_t device_id;
   9.885 +    uint16_t vendor_id;
   9.886 +    uint16_t subsystem_id;
   9.887 +    uint16_t subsystem_vendor_id;
   9.888 +    uint8_t revision_id;
   9.889 +    uint8_t autoneg;
   9.890 +    uint8_t mdix;
   9.891 +    uint8_t forced_speed_duplex;
   9.892 +    uint8_t wait_autoneg_complete;
   9.893 +    uint8_t dma_fairness;
   9.894 +    uint8_t mac_addr[NODE_ADDRESS_SIZE];
   9.895 +    uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
   9.896 +    boolean_t disable_polarity_correction;
   9.897 +    boolean_t get_link_status;
   9.898 +    boolean_t tbi_compatibility_en;
   9.899 +    boolean_t tbi_compatibility_on;
   9.900 +    boolean_t fc_send_xon;
   9.901 +    boolean_t report_tx_early;
   9.902 +    boolean_t adaptive_ifs;
   9.903 +    boolean_t ifs_params_forced;
   9.904 +    boolean_t in_ifs_mode;
   9.905 +};
   9.906 +
   9.907 +
   9.908 +#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
   9.909 +#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
   9.910 +
   9.911 +/* Register Bit Masks */
   9.912 +/* Device Control */
   9.913 +#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
   9.914 +#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
   9.915 +#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
   9.916 +#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
   9.917 +#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
   9.918 +#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
   9.919 +#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
   9.920 +#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
   9.921 +#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
   9.922 +#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
   9.923 +#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
   9.924 +#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
   9.925 +#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
   9.926 +#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
   9.927 +#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
   9.928 +#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
   9.929 +#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
   9.930 +#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
   9.931 +#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
   9.932 +#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
   9.933 +#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
   9.934 +#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
   9.935 +#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
   9.936 +#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
   9.937 +#define E1000_CTRL_RST      0x04000000  /* Global reset */
   9.938 +#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
   9.939 +#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
   9.940 +#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
   9.941 +#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
   9.942 +#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
   9.943 +
   9.944 +/* Device Status */
   9.945 +#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
   9.946 +#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
   9.947 +#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
   9.948 +#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
   9.949 +#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
   9.950 +#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
   9.951 +#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
   9.952 +#define E1000_STATUS_SPEED_MASK 0x000000C0
   9.953 +#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
   9.954 +#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
   9.955 +#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
   9.956 +#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
   9.957 +#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
   9.958 +#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
   9.959 +#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
   9.960 +#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
   9.961 +#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
   9.962 +
   9.963 +/* Constants used to intrepret the masked PCI-X bus speed. */
   9.964 +#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
   9.965 +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
   9.966 +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
   9.967 +
   9.968 +/* EEPROM/Flash Control */
   9.969 +#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
   9.970 +#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
   9.971 +#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
   9.972 +#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
   9.973 +#define E1000_EECD_FWE_MASK  0x00000030 
   9.974 +#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
   9.975 +#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
   9.976 +#define E1000_EECD_FWE_SHIFT 4
   9.977 +#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
   9.978 +#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
   9.979 +#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
   9.980 +#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
   9.981 +
   9.982 +/* EEPROM Read */
   9.983 +#define E1000_EERD_START      0x00000001 /* Start Read */
   9.984 +#define E1000_EERD_DONE       0x00000010 /* Read Done */
   9.985 +#define E1000_EERD_ADDR_SHIFT 8
   9.986 +#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
   9.987 +#define E1000_EERD_DATA_SHIFT 16
   9.988 +#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
   9.989 +
   9.990 +/* Extended Device Control */
   9.991 +#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */ 
   9.992 +#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
   9.993 +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
   9.994 +#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
   9.995 +#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
   9.996 +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
   9.997 +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
   9.998 +#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
   9.999 +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
  9.1000 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
  9.1001 +#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
  9.1002 +#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
  9.1003 +#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
  9.1004 +#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
  9.1005 +#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
  9.1006 +#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
  9.1007 +#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
  9.1008 +#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
  9.1009 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  9.1010 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
  9.1011 +#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
  9.1012 +#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
  9.1013 +#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
  9.1014 +#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
  9.1015 +#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
  9.1016 +#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
  9.1017 +
  9.1018 +/* MDI Control */
  9.1019 +#define E1000_MDIC_DATA_MASK 0x0000FFFF
  9.1020 +#define E1000_MDIC_REG_MASK  0x001F0000
  9.1021 +#define E1000_MDIC_REG_SHIFT 16
  9.1022 +#define E1000_MDIC_PHY_MASK  0x03E00000
  9.1023 +#define E1000_MDIC_PHY_SHIFT 21
  9.1024 +#define E1000_MDIC_OP_WRITE  0x04000000
  9.1025 +#define E1000_MDIC_OP_READ   0x08000000
  9.1026 +#define E1000_MDIC_READY     0x10000000
  9.1027 +#define E1000_MDIC_INT_EN    0x20000000
  9.1028 +#define E1000_MDIC_ERROR     0x40000000
  9.1029 +
  9.1030 +/* LED Control */
  9.1031 +#define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
  9.1032 +#define E1000_LEDCTL_LED0_MODE_SHIFT 0
  9.1033 +#define E1000_LEDCTL_LED0_IVRT       0x00000040
  9.1034 +#define E1000_LEDCTL_LED0_BLINK      0x00000080
  9.1035 +#define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
  9.1036 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8
  9.1037 +#define E1000_LEDCTL_LED1_IVRT       0x00004000
  9.1038 +#define E1000_LEDCTL_LED1_BLINK      0x00008000
  9.1039 +#define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
  9.1040 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16
  9.1041 +#define E1000_LEDCTL_LED2_IVRT       0x00400000
  9.1042 +#define E1000_LEDCTL_LED2_BLINK      0x00800000
  9.1043 +#define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
  9.1044 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24
  9.1045 +#define E1000_LEDCTL_LED3_IVRT       0x40000000
  9.1046 +#define E1000_LEDCTL_LED3_BLINK      0x80000000
  9.1047 +
  9.1048 +#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
  9.1049 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
  9.1050 +#define E1000_LEDCTL_MODE_LINK_UP       0x2
  9.1051 +#define E1000_LEDCTL_MODE_ACTIVITY      0x3
  9.1052 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
  9.1053 +#define E1000_LEDCTL_MODE_LINK_10       0x5
  9.1054 +#define E1000_LEDCTL_MODE_LINK_100      0x6
  9.1055 +#define E1000_LEDCTL_MODE_LINK_1000     0x7
  9.1056 +#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
  9.1057 +#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
  9.1058 +#define E1000_LEDCTL_MODE_COLLISION     0xA
  9.1059 +#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
  9.1060 +#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
  9.1061 +#define E1000_LEDCTL_MODE_PAUSED        0xD
  9.1062 +#define E1000_LEDCTL_MODE_LED_ON        0xE
  9.1063 +#define E1000_LEDCTL_MODE_LED_OFF       0xF
  9.1064 +
  9.1065 +/* Receive Address */
  9.1066 +#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
  9.1067 +
  9.1068 +/* Interrupt Cause Read */
  9.1069 +#define E1000_ICR_TXDW    0x00000001    /* Transmit desc written back */
  9.1070 +#define E1000_ICR_TXQE    0x00000002    /* Transmit Queue empty */
  9.1071 +#define E1000_ICR_LSC     0x00000004    /* Link Status Change */
  9.1072 +#define E1000_ICR_RXSEQ   0x00000008    /* rx sequence error */
  9.1073 +#define E1000_ICR_RXDMT0  0x00000010    /* rx desc min. threshold (0) */
  9.1074 +#define E1000_ICR_RXO     0x00000040    /* rx overrun */
  9.1075 +#define E1000_ICR_RXT0    0x00000080    /* rx timer intr (ring 0) */
  9.1076 +#define E1000_ICR_MDAC    0x00000200    /* MDIO access complete */
  9.1077 +#define E1000_ICR_RXCFG   0x00000400    /* RX /c/ ordered set */
  9.1078 +#define E1000_ICR_GPI_EN0 0x00000800    /* GP Int 0 */
  9.1079 +#define E1000_ICR_GPI_EN1 0x00001000    /* GP Int 1 */
  9.1080 +#define E1000_ICR_GPI_EN2 0x00002000    /* GP Int 2 */
  9.1081 +#define E1000_ICR_GPI_EN3 0x00004000    /* GP Int 3 */
  9.1082 +#define E1000_ICR_TXD_LOW 0x00008000
  9.1083 +#define E1000_ICR_SRPD    0x00010000
  9.1084 +
  9.1085 +/* Interrupt Cause Set */
  9.1086 +#define E1000_ICS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
  9.1087 +#define E1000_ICS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
  9.1088 +#define E1000_ICS_LSC     E1000_ICR_LSC         /* Link Status Change */
  9.1089 +#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
  9.1090 +#define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
  9.1091 +#define E1000_ICS_RXO     E1000_ICR_RXO         /* rx overrun */
  9.1092 +#define E1000_ICS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
  9.1093 +#define E1000_ICS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
  9.1094 +#define E1000_ICS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
  9.1095 +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
  9.1096 +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
  9.1097 +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
  9.1098 +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
  9.1099 +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
  9.1100 +#define E1000_ICS_SRPD    E1000_ICR_SRPD
  9.1101 +
  9.1102 +/* Interrupt Mask Set */
  9.1103 +#define E1000_IMS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
  9.1104 +#define E1000_IMS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
  9.1105 +#define E1000_IMS_LSC     E1000_ICR_LSC         /* Link Status Change */
  9.1106 +#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
  9.1107 +#define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
  9.1108 +#define E1000_IMS_RXO     E1000_ICR_RXO         /* rx overrun */
  9.1109 +#define E1000_IMS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
  9.1110 +#define E1000_IMS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
  9.1111 +#define E1000_IMS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
  9.1112 +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
  9.1113 +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
  9.1114 +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
  9.1115 +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
  9.1116 +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
  9.1117 +#define E1000_IMS_SRPD    E1000_ICR_SRPD
  9.1118 +
  9.1119 +/* Interrupt Mask Clear */
  9.1120 +#define E1000_IMC_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
  9.1121 +#define E1000_IMC_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
  9.1122 +#define E1000_IMC_LSC     E1000_ICR_LSC         /* Link Status Change */
  9.1123 +#define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
  9.1124 +#define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
  9.1125 +#define E1000_IMC_RXO     E1000_ICR_RXO         /* rx overrun */
  9.1126 +#define E1000_IMC_RXT0    E1000_ICR_RXT0        /* rx timer intr */
  9.1127 +#define E1000_IMC_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
  9.1128 +#define E1000_IMC_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
  9.1129 +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
  9.1130 +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
  9.1131 +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
  9.1132 +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
  9.1133 +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
  9.1134 +#define E1000_IMC_SRPD    E1000_ICR_SRPD
  9.1135 +
  9.1136 +/* Receive Control */
  9.1137 +#define E1000_RCTL_RST          0x00000001      /* Software reset */
  9.1138 +#define E1000_RCTL_EN           0x00000002      /* enable */
  9.1139 +#define E1000_RCTL_SBP          0x00000004      /* store bad packet */
  9.1140 +#define E1000_RCTL_UPE          0x00000008      /* unicast promiscuous enable */
  9.1141 +#define E1000_RCTL_MPE          0x00000010      /* multicast promiscuous enab */
  9.1142 +#define E1000_RCTL_LPE          0x00000020      /* long packet enable */
  9.1143 +#define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
  9.1144 +#define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
  9.1145 +#define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
  9.1146 +#define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
  9.1147 +#define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min threshold size */
  9.1148 +#define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min threshold size */
  9.1149 +#define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min threshold size */
  9.1150 +#define E1000_RCTL_MO_SHIFT     12              /* multicast offset shift */
  9.1151 +#define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
  9.1152 +#define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
  9.1153 +#define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
  9.1154 +#define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
  9.1155 +#define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
  9.1156 +#define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
  9.1157 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
  9.1158 +#define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
  9.1159 +#define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
  9.1160 +#define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
  9.1161 +#define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
  9.1162 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
  9.1163 +#define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
  9.1164 +#define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
  9.1165 +#define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
  9.1166 +#define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
  9.1167 +#define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
  9.1168 +#define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
  9.1169 +#define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
  9.1170 +#define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
  9.1171 +#define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
  9.1172 +
  9.1173 +/* Receive Descriptor */
  9.1174 +#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
  9.1175 +#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
  9.1176 +#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
  9.1177 +#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
  9.1178 +#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
  9.1179 +
  9.1180 +/* Flow Control */
  9.1181 +#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
  9.1182 +#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
  9.1183 +#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
  9.1184 +#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
  9.1185 +
  9.1186 +/* Receive Descriptor Control */
  9.1187 +#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
  9.1188 +#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
  9.1189 +#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
  9.1190 +#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
  9.1191 +
  9.1192 +/* Transmit Descriptor Control */
  9.1193 +#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
  9.1194 +#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
  9.1195 +#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
  9.1196 +#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
  9.1197 +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
  9.1198 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
  9.1199 +
  9.1200 +/* Transmit Configuration Word */
  9.1201 +#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
  9.1202 +#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
  9.1203 +#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
  9.1204 +#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
  9.1205 +#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
  9.1206 +#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
  9.1207 +#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
  9.1208 +#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
  9.1209 +#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
  9.1210 +#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
  9.1211 +
  9.1212 +/* Receive Configuration Word */
  9.1213 +#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
  9.1214 +#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
  9.1215 +#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
  9.1216 +#define E1000_RXCW_CC    0x10000000     /* Receive config change */
  9.1217 +#define E1000_RXCW_C     0x20000000     /* Receive config */
  9.1218 +#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
  9.1219 +#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
  9.1220 +
  9.1221 +/* Transmit Control */
  9.1222 +#define E1000_TCTL_RST    0x00000001    /* software reset */
  9.1223 +#define E1000_TCTL_EN     0x00000002    /* enable tx */
  9.1224 +#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
  9.1225 +#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
  9.1226 +#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
  9.1227 +#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
  9.1228 +#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
  9.1229 +#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
  9.1230 +#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
  9.1231 +#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
  9.1232 +
  9.1233 +/* Receive Checksum Control */
  9.1234 +#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
  9.1235 +#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
  9.1236 +#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
  9.1237 +#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
  9.1238 +
  9.1239 +/* Definitions for power management and wakeup registers */
  9.1240 +/* Wake Up Control */
  9.1241 +#define E1000_WUC_APME       0x00000001 /* APM Enable */
  9.1242 +#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  9.1243 +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
  9.1244 +#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
  9.1245 +
  9.1246 +/* Wake Up Filter Control */
  9.1247 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  9.1248 +#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  9.1249 +#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  9.1250 +#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  9.1251 +#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  9.1252 +#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
  9.1253 +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
  9.1254 +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
  9.1255 +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
  9.1256 +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
  9.1257 +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
  9.1258 +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
  9.1259 +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
  9.1260 +#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
  9.1261 +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  9.1262 +
  9.1263 +/* Wake Up Status */
  9.1264 +#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
  9.1265 +#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
  9.1266 +#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
  9.1267 +#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
  9.1268 +#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
  9.1269 +#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
  9.1270 +#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
  9.1271 +#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
  9.1272 +#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
  9.1273 +#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
  9.1274 +#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
  9.1275 +#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
  9.1276 +#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
  9.1277 +
  9.1278 +/* Management Control */
  9.1279 +#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
  9.1280 +#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
  9.1281 +#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
  9.1282 +#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
  9.1283 +#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
  9.1284 +#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
  9.1285 +#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
  9.1286 +#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
  9.1287 +#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
  9.1288 +#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery 
  9.1289 +                                             * Filtering */
  9.1290 +#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
  9.1291 +#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
  9.1292 +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
  9.1293 +#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
  9.1294 +#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
  9.1295 +#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
  9.1296 +#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
  9.1297 +#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
  9.1298 +#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
  9.1299 +
  9.1300 +#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
  9.1301 +#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
  9.1302 +
  9.1303 +/* Wake Up Packet Length */
  9.1304 +#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
  9.1305 +
  9.1306 +#define E1000_MDALIGN          4096
  9.1307 +
  9.1308 +/* EEPROM Commands */
  9.1309 +#define EEPROM_READ_OPCODE  0x6  /* EERPOM read opcode */
  9.1310 +#define EEPROM_WRITE_OPCODE 0x5  /* EERPOM write opcode */
  9.1311 +#define EEPROM_ERASE_OPCODE 0x7  /* EERPOM erase opcode */
  9.1312 +#define EEPROM_EWEN_OPCODE  0x13 /* EERPOM erase/write enable */
  9.1313 +#define EEPROM_EWDS_OPCODE  0x10 /* EERPOM erast/write disable */
  9.1314 +
  9.1315 +/* EEPROM Word Offsets */
  9.1316 +#define EEPROM_COMPAT              0x0003
  9.1317 +#define EEPROM_ID_LED_SETTINGS     0x0004
  9.1318 +#define EEPROM_INIT_CONTROL1_REG   0x000A
  9.1319 +#define EEPROM_INIT_CONTROL2_REG   0x000F
  9.1320 +#define EEPROM_FLASH_VERSION       0x0032
  9.1321 +#define EEPROM_CHECKSUM_REG        0x003F
  9.1322 +
  9.1323 +/* Word definitions for ID LED Settings */
  9.1324 +#define ID_LED_RESERVED_0000 0x0000
  9.1325 +#define ID_LED_RESERVED_FFFF 0xFFFF
  9.1326 +#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
  9.1327 +                              (ID_LED_OFF1_OFF2 << 8) | \
  9.1328 +                              (ID_LED_DEF1_DEF2 << 4) | \
  9.1329 +                              (ID_LED_DEF1_DEF2))
  9.1330 +#define ID_LED_DEF1_DEF2     0x1
  9.1331 +#define ID_LED_DEF1_ON2      0x2
  9.1332 +#define ID_LED_DEF1_OFF2     0x3
  9.1333 +#define ID_LED_ON1_DEF2      0x4
  9.1334 +#define ID_LED_ON1_ON2       0x5
  9.1335 +#define ID_LED_ON1_OFF2      0x6
  9.1336 +#define ID_LED_OFF1_DEF2     0x7
  9.1337 +#define ID_LED_OFF1_ON2      0x8
  9.1338 +#define ID_LED_OFF1_OFF2     0x9
  9.1339 +
  9.1340 +/* Mask bits for fields in Word 0x03 of the EEPROM */
  9.1341 +#define EEPROM_COMPAT_SERVER 0x0400
  9.1342 +#define EEPROM_COMPAT_CLIENT 0x0200
  9.1343 +
  9.1344 +/* Mask bits for fields in Word 0x0a of the EEPROM */
  9.1345 +#define EEPROM_WORD0A_ILOS   0x0010
  9.1346 +#define EEPROM_WORD0A_SWDPIO 0x01E0
  9.1347 +#define EEPROM_WORD0A_LRST   0x0200
  9.1348 +#define EEPROM_WORD0A_FD     0x0400
  9.1349 +#define EEPROM_WORD0A_66MHZ  0x0800
  9.1350 +
  9.1351 +/* Mask bits for fields in Word 0x0f of the EEPROM */
  9.1352 +#define EEPROM_WORD0F_PAUSE_MASK 0x3000
  9.1353 +#define EEPROM_WORD0F_PAUSE      0x1000
  9.1354 +#define EEPROM_WORD0F_ASM_DIR    0x2000
  9.1355 +#define EEPROM_WORD0F_ANE        0x0800
  9.1356 +#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
  9.1357 +
  9.1358 +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
  9.1359 +#define EEPROM_SUM 0xBABA
  9.1360 +
  9.1361 +/* EEPROM Map defines (WORD OFFSETS)*/
  9.1362 +#define EEPROM_NODE_ADDRESS_BYTE_0 0
  9.1363 +#define EEPROM_PBA_BYTE_1          8
  9.1364 +
  9.1365 +/* EEPROM Map Sizes (Byte Counts) */
  9.1366 +#define PBA_SIZE 4
  9.1367 +
  9.1368 +/* Collision related configuration parameters */
  9.1369 +#define E1000_COLLISION_THRESHOLD       16
  9.1370 +#define E1000_CT_SHIFT                  4
  9.1371 +#define E1000_COLLISION_DISTANCE        64
  9.1372 +#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
  9.1373 +#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
  9.1374 +#define E1000_GB_HDX_COLLISION_DISTANCE 512
  9.1375 +#define E1000_COLD_SHIFT                12
  9.1376 +
  9.1377 +/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
  9.1378 +#define REQ_TX_DESCRIPTOR_MULTIPLE  8
  9.1379 +#define REQ_RX_DESCRIPTOR_MULTIPLE  8
  9.1380 +
  9.1381 +/* Default values for the transmit IPG register */
  9.1382 +#define DEFAULT_82542_TIPG_IPGT        10
  9.1383 +#define DEFAULT_82543_TIPG_IPGT_FIBER  9
  9.1384 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
  9.1385 +
  9.1386 +#define E1000_TIPG_IPGT_MASK  0x000003FF
  9.1387 +#define E1000_TIPG_IPGR1_MASK 0x000FFC00
  9.1388 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000
  9.1389 +
  9.1390 +#define DEFAULT_82542_TIPG_IPGR1 2
  9.1391 +#define DEFAULT_82543_TIPG_IPGR1 8
  9.1392 +#define E1000_TIPG_IPGR1_SHIFT  10
  9.1393 +
  9.1394 +#define DEFAULT_82542_TIPG_IPGR2 10
  9.1395 +#define DEFAULT_82543_TIPG_IPGR2 6
  9.1396 +#define E1000_TIPG_IPGR2_SHIFT  20
  9.1397 +
  9.1398 +#define E1000_TXDMAC_DPP 0x00000001
  9.1399 +
  9.1400 +/* Adaptive IFS defines */
  9.1401 +#define TX_THRESHOLD_START     8
  9.1402 +#define TX_THRESHOLD_INCREMENT 10
  9.1403 +#define TX_THRESHOLD_DECREMENT 1
  9.1404 +#define TX_THRESHOLD_STOP      190
  9.1405 +#define TX_THRESHOLD_DISABLE   0
  9.1406 +#define TX_THRESHOLD_TIMER_MS  10000
  9.1407 +#define MIN_NUM_XMITS          1000
  9.1408 +#define IFS_MAX                80
  9.1409 +#define IFS_STEP               10
  9.1410 +#define IFS_MIN                40
  9.1411 +#define IFS_RATIO              4
  9.1412 +
  9.1413 +/* PBA constants */
  9.1414 +#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
  9.1415 +#define E1000_PBA_24K 0x0018
  9.1416 +#define E1000_PBA_40K 0x0028
  9.1417 +#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
  9.1418 +
  9.1419 +/* Flow Control Constants */
  9.1420 +#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
  9.1421 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
  9.1422 +#define FLOW_CONTROL_TYPE         0x8808
  9.1423 +
  9.1424 +/* The historical defaults for the flow control values are given below. */
  9.1425 +#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
  9.1426 +#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
  9.1427 +#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
  9.1428 +
  9.1429 +/* PCIX Config space */
  9.1430 +#define PCIX_COMMAND_REGISTER    0xE6
  9.1431 +#define PCIX_STATUS_REGISTER_LO  0xE8
  9.1432 +#define PCIX_STATUS_REGISTER_HI  0xEA
  9.1433 +
  9.1434 +#define PCIX_COMMAND_MMRBC_MASK      0x000C
  9.1435 +#define PCIX_COMMAND_MMRBC_SHIFT     0x2
  9.1436 +#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
  9.1437 +#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
  9.1438 +#define PCIX_STATUS_HI_MMRBC_4K      0x3
  9.1439 +#define PCIX_STATUS_HI_MMRBC_2K      0x2
  9.1440 +
  9.1441 +
  9.1442 +/* The number of bits that we need to shift right to move the "pause"
  9.1443 + * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
  9.1444 + * in the TXCW register 
  9.1445 + */
  9.1446 +#define PAUSE_SHIFT 5
  9.1447 +
  9.1448 +/* The number of bits that we need to shift left to move the "SWDPIO"
  9.1449 + * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
  9.1450 + * in the CTRL register 
  9.1451 + */
  9.1452 +#define SWDPIO_SHIFT 17
  9.1453 +
  9.1454 +/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
  9.1455 + * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
  9.1456 + * Extended CTRL register.
  9.1457 + * in the CTRL register 
  9.1458 + */
  9.1459 +#define SWDPIO__EXT_SHIFT 4
  9.1460 +
  9.1461 +/* The number of bits that we need to shift left to move the "ILOS"
  9.1462 + * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
  9.1463 + * in the CTRL register 
  9.1464 + */
  9.1465 +#define ILOS_SHIFT  3
  9.1466 +
  9.1467 +
  9.1468 +#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
  9.1469 +
  9.1470 +/* The number of milliseconds we wait for auto-negotiation to complete */
  9.1471 +#define LINK_UP_TIMEOUT             500
  9.1472 +
  9.1473 +#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
  9.1474 +
  9.1475 +/* The carrier extension symbol, as received by the NIC. */
  9.1476 +#define CARRIER_EXTENSION   0x0F
  9.1477 +
  9.1478 +/* TBI_ACCEPT macro definition:
  9.1479 + *
  9.1480 + * This macro requires:
  9.1481 + *      adapter = a pointer to struct e1000_hw 
  9.1482 + *      status = the 8 bit status field of the RX descriptor with EOP set
  9.1483 + *      error = the 8 bit error field of the RX descriptor with EOP set
  9.1484 + *      length = the sum of all the length fields of the RX descriptors that
  9.1485 + *               make up the current frame
  9.1486 + *      last_byte = the last byte of the frame DMAed by the hardware
  9.1487 + *      max_frame_length = the maximum frame length we want to accept.
  9.1488 + *      min_frame_length = the minimum frame length we want to accept.
  9.1489 + *
  9.1490 + * This macro is a conditional that should be used in the interrupt 
  9.1491 + * handler's Rx processing routine when RxErrors have been detected.
  9.1492 + *
  9.1493 + * Typical use:
  9.1494 + *  ...
  9.1495 + *  if (TBI_ACCEPT) {
  9.1496 + *      accept_frame = TRUE;
  9.1497 + *      e1000_tbi_adjust_stats(adapter, MacAddress);
  9.1498 + *      frame_length--;
  9.1499 + *  } else {
  9.1500 + *      accept_frame = FALSE;
  9.1501 + *  }
  9.1502 + *  ...
  9.1503 + */
  9.1504 +
  9.1505 +#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
  9.1506 +    ((adapter)->tbi_compatibility_on && \
  9.1507 +     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
  9.1508 +     ((last_byte) == CARRIER_EXTENSION) && \
  9.1509 +     (((status) & E1000_RXD_STAT_VP) ? \
  9.1510 +          (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
  9.1511 +           ((length) <= ((adapter)->max_frame_size + 1))) : \
  9.1512 +          (((length) > (adapter)->min_frame_size) && \
  9.1513 +           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
  9.1514 +
  9.1515 +
  9.1516 +/* Structures, enums, and macros for the PHY */
  9.1517 +
  9.1518 +/* Bit definitions for the Management Data IO (MDIO) and Management Data
  9.1519 + * Clock (MDC) pins in the Device Control Register.
  9.1520 + */
  9.1521 +#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
  9.1522 +#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
  9.1523 +#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
  9.1524 +#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
  9.1525 +#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
  9.1526 +#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
  9.1527 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
  9.1528 +#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
  9.1529 +
  9.1530 +/* PHY 1000 MII Register/Bit Definitions */
  9.1531 +/* PHY Registers defined by IEEE */
  9.1532 +#define PHY_CTRL         0x00 /* Control Register */
  9.1533 +#define PHY_STATUS       0x01 /* Status Regiser */
  9.1534 +#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
  9.1535 +#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
  9.1536 +#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
  9.1537 +#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
  9.1538 +#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
  9.1539 +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
  9.1540 +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
  9.1541 +#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
  9.1542 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
  9.1543 +#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
  9.1544 +
  9.1545 +/* M88E1000 Specific Registers */
  9.1546 +#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
  9.1547 +#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
  9.1548 +#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
  9.1549 +#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
  9.1550 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
  9.1551 +#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
  9.1552 +
  9.1553 +#define MAX_PHY_REG_ADDRESS 0x1F        /* 5 bit address bus (0-0x1F) */
  9.1554 +
  9.1555 +/* PHY Control Register */
  9.1556 +#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
  9.1557 +#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
  9.1558 +#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
  9.1559 +#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
  9.1560 +#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
  9.1561 +#define MII_CR_POWER_DOWN       0x0800  /* Power down */
  9.1562 +#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
  9.1563 +#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
  9.1564 +#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
  9.1565 +#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
  9.1566 +
  9.1567 +/* PHY Status Register */
  9.1568 +#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
  9.1569 +#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
  9.1570 +#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
  9.1571 +#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
  9.1572 +#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
  9.1573 +#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
  9.1574 +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
  9.1575 +#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
  9.1576 +#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
  9.1577 +#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
  9.1578 +#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
  9.1579 +#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
  9.1580 +#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
  9.1581 +#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
  9.1582 +#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
  9.1583 +
  9.1584 +/* Autoneg Advertisement Register */
  9.1585 +#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
  9.1586 +#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
  9.1587 +#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
  9.1588 +#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
  9.1589 +#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
  9.1590 +#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
  9.1591 +#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
  9.1592 +#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
  9.1593 +#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
  9.1594 +#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
  9.1595 +
  9.1596 +/* Link Partner Ability Register (Base Page) */
  9.1597 +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
  9.1598 +#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
  9.1599 +#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
  9.1600 +#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
  9.1601 +#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
  9.1602 +#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
  9.1603 +#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
  9.1604 +#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
  9.1605 +#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
  9.1606 +#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
  9.1607 +#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
  9.1608 +
  9.1609 +/* Autoneg Expansion Register */
  9.1610 +#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
  9.1611 +#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
  9.1612 +#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
  9.1613 +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
  9.1614 +#define NWAY_ER_PAR_DETECT_FAULT  0x0100 /* LP is 100TX Full Duplex Capable */
  9.1615 +
  9.1616 +/* Next Page TX Register */
  9.1617 +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
  9.1618 +#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
  9.1619 +                                    * of different NP
  9.1620 +                                    */
  9.1621 +#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
  9.1622 +                                    * 0 = cannot comply with msg
  9.1623 +                                    */
  9.1624 +#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
  9.1625 +#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow 
  9.1626 +                                    * 0 = sending last NP
  9.1627 +                                    */
  9.1628 +
  9.1629 +/* Link Partner Next Page Register */
  9.1630 +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
  9.1631 +#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
  9.1632 +                                       * of different NP
  9.1633 +                                       */
  9.1634 +#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg 
  9.1635 +                                       * 0 = cannot comply with msg
  9.1636 +                                       */
  9.1637 +#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
  9.1638 +#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
  9.1639 +#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
  9.1640 +                                        * 0 = sending last NP 
  9.1641 +                                        */
  9.1642 +
  9.1643 +/* 1000BASE-T Control Register */
  9.1644 +#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
  9.1645 +#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
  9.1646 +#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
  9.1647 +#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
  9.1648 +                                        /* 0=DTE device */
  9.1649 +#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
  9.1650 +                                        /* 0=Configure PHY as Slave */
  9.1651 +#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
  9.1652 +                                        /* 0=Automatic Master/Slave config */
  9.1653 +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
  9.1654 +#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
  9.1655 +#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
  9.1656 +#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
  9.1657 +#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
  9.1658 +
  9.1659 +/* 1000BASE-T Status Register */
  9.1660 +#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
  9.1661 +#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
  9.1662 +#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
  9.1663 +#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
  9.1664 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
  9.1665 +#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
  9.1666 +#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
  9.1667 +#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
  9.1668 +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
  9.1669 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
  9.1670 +
  9.1671 +/* Extended Status Register */
  9.1672 +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
  9.1673 +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
  9.1674 +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
  9.1675 +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
  9.1676 +
  9.1677 +#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
  9.1678 +#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
  9.1679 +
  9.1680 +#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
  9.1681 +                                      /* (0=enable, 1=disable) */
  9.1682 +
  9.1683 +/* M88E1000 PHY Specific Control Register */
  9.1684 +#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
  9.1685 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
  9.1686 +#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
  9.1687 +#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low, 
  9.1688 +                                                * 0=CLK125 toggling
  9.1689 +                                                */
  9.1690 +#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
  9.1691 +                                               /* Manual MDI configuration */
  9.1692 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
  9.1693 +#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
  9.1694 +                                                *  100BASE-TX/10BASE-T: 
  9.1695 +                                                *  MDI Mode
  9.1696 +                                                */
  9.1697 +#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled 
  9.1698 +                                                * all speeds. 
  9.1699 +                                                */
  9.1700 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 
  9.1701 +                                        /* 1=Enable Extended 10BASE-T distance
  9.1702 +                                         * (Lower 10BASE-T RX Threshold)
  9.1703 +                                         * 0=Normal 10BASE-T RX Threshold */
  9.1704 +#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
  9.1705 +                                        /* 1=5-Bit interface in 100BASE-TX
  9.1706 +                                         * 0=MII interface in 100BASE-TX */
  9.1707 +#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
  9.1708 +#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
  9.1709 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
  9.1710 +
  9.1711 +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
  9.1712 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
  9.1713 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
  9.1714 +
  9.1715 +/* M88E1000 PHY Specific Status Register */
  9.1716 +#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
  9.1717 +#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
  9.1718 +#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
  9.1719 +#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
  9.1720 +                                            * 3=110-140M;4=>140M */
  9.1721 +#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
  9.1722 +#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
  9.1723 +#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
  9.1724 +#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
  9.1725 +#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
  9.1726 +#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
  9.1727 +#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
  9.1728 +#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
  9.1729 +
  9.1730 +#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
  9.1731 +#define M88E1000_PSSR_MDIX_SHIFT         6
  9.1732 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
  9.1733 +
  9.1734 +/* M88E1000 Extended PHY Specific Control Register */
  9.1735 +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
  9.1736 +#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
  9.1737 +                                              * Will assert lost lock and bring
  9.1738 +                                              * link down if idle not seen
  9.1739 +                                              * within 1ms in 1000BASE-T 
  9.1740 +                                              */
  9.1741 +/* Number of times we will attempt to autonegotiate before downshifting if we
  9.1742 + * are the master */
  9.1743 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
  9.1744 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000    
  9.1745 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
  9.1746 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
  9.1747 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
  9.1748 +/* Number of times we will attempt to autonegotiate before downshifting if we
  9.1749 + * are the slave */
  9.1750 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
  9.1751 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
  9.1752 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
  9.1753 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
  9.1754 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
  9.1755 +#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
  9.1756 +#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
  9.1757 +#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
  9.1758 +
  9.1759 +/* Bit definitions for valid PHY IDs. */
  9.1760 +#define M88E1000_E_PHY_ID  0x01410C50
  9.1761 +#define M88E1000_I_PHY_ID  0x01410C30
  9.1762 +#define M88E1011_I_PHY_ID  0x01410C20
  9.1763 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
  9.1764 +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
  9.1765 +#define M88E1011_I_REV_4   0x04
  9.1766 +
  9.1767 +/* Miscellaneous PHY bit definitions. */
  9.1768 +#define PHY_PREAMBLE        0xFFFFFFFF
  9.1769 +#define PHY_SOF             0x01
  9.1770 +#define PHY_OP_READ         0x02
  9.1771 +#define PHY_OP_WRITE        0x01
  9.1772 +#define PHY_TURNAROUND      0x02
  9.1773 +#define PHY_PREAMBLE_SIZE   32
  9.1774 +#define MII_CR_SPEED_1000   0x0040
  9.1775 +#define MII_CR_SPEED_100    0x2000
  9.1776 +#define MII_CR_SPEED_10     0x0000
  9.1777 +#define E1000_PHY_ADDRESS   0x01
  9.1778 +#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
  9.1779 +#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
  9.1780 +#define PHY_REVISION_MASK   0xFFFFFFF0
  9.1781 +#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
  9.1782 +#define REG4_SPEED_MASK     0x01E0
  9.1783 +#define REG9_SPEED_MASK     0x0300
  9.1784 +#define ADVERTISE_10_HALF   0x0001
  9.1785 +#define ADVERTISE_10_FULL   0x0002
  9.1786 +#define ADVERTISE_100_HALF  0x0004
  9.1787 +#define ADVERTISE_100_FULL  0x0008
  9.1788 +#define ADVERTISE_1000_HALF 0x0010
  9.1789 +#define ADVERTISE_1000_FULL 0x0020
  9.1790 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
  9.1791 +
  9.1792 +#endif /* _E1000_HW_H_ */
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_main.c	Sat Feb 08 17:39:26 2003 +0000
    10.3 @@ -0,0 +1,2281 @@
    10.4 +/*******************************************************************************
    10.5 +
    10.6 +  
    10.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    10.8 +  
    10.9 +  This program is free software; you can redistribute it and/or modify it 
   10.10 +  under the terms of the GNU General Public License as published by the Free 
   10.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   10.12 +  any later version.
   10.13 +  
   10.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   10.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   10.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   10.17 +  more details.
   10.18 +  
   10.19 +  You should have received a copy of the GNU General Public License along with
   10.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   10.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   10.22 +  
   10.23 +  The full GNU General Public License is included in this distribution in the
   10.24 +  file called LICENSE.
   10.25 +  
   10.26 +  Contact Information:
   10.27 +  Linux NICS <linux.nics@intel.com>
   10.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   10.29 +
   10.30 +*******************************************************************************/
   10.31 +
   10.32 +#include "e1000.h"
   10.33 +
   10.34 +/* Change Log
   10.35 + *
   10.36 + * 4.4.19       11/27/02
   10.37 + *   o Feature: Added user-settable knob for interrupt throttle rate (ITR).
   10.38 + *   o Cleanup: removed large static array allocations.
   10.39 + *   o Cleanup: C99 struct initializer format.
   10.40 + *   o Bug fix: restore VLAN settings when interface is brought up.
   10.41 + *   o Bug fix: return cleanly in probe if error in detecting MAC type.
   10.42 + *   o Bug fix: Wake up on magic packet by default only if enabled in eeprom.
   10.43 + *   o Bug fix: Validate MAC address in set_mac.
   10.44 + *   o Bug fix: Throw away zero-length Tx skbs.
   10.45 + *   o Bug fix: Make ethtool EEPROM acceses work on older versions of ethtool.
   10.46 + * 
   10.47 + * 4.4.12       10/15/02
   10.48 + *   o Clean up: use members of pci_device rather than direct calls to
   10.49 + *     pci_read_config_word.
   10.50 + *   o Bug fix: changed default flow control settings.
   10.51 + *   o Clean up: ethtool file now has an inclusive list for adapters in the
   10.52 + *     Wake-On-LAN capabilities instead of an exclusive list.
   10.53 + *   o Bug fix: miscellaneous WoL bug fixes.
   10.54 + *   o Added software interrupt for clearing rx ring
   10.55 + *   o Bug fix: easier to undo "forcing" of 1000/fd using ethtool.
   10.56 + *   o Now setting netdev->mem_end in e1000_probe.
   10.57 + *   o Clean up: Moved tx_timeout from interrupt context to process context
   10.58 + *     using schedule_task.
   10.59 + * 
   10.60 + * 4.3.15       8/9/02
   10.61 + */
   10.62 +
   10.63 +char e1000_driver_name[] = "e1000";
   10.64 +char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
   10.65 +char e1000_driver_version[] = "4.4.19-k2";
   10.66 +char e1000_copyright[] = "Copyright (c) 1999-2002 Intel Corporation.";
   10.67 +
   10.68 +/* e1000_pci_tbl - PCI Device ID Table
   10.69 + *
   10.70 + * Private driver_data field (last one) stores an index into e1000_strings
   10.71 + * Wildcard entries (PCI_ANY_ID) should come last
   10.72 + * Last entry must be all 0s
   10.73 + *
   10.74 + * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
   10.75 + *   Class, Class Mask, String Index }
   10.76 + */
   10.77 +static struct pci_device_id e1000_pci_tbl[] __devinitdata = {
   10.78 +	/* Intel(R) PRO/1000 Network Connection */
   10.79 +	{0x8086, 0x1000, 0x8086, 0x1000, 0, 0, 0},
   10.80 +	{0x8086, 0x1001, 0x8086, 0x1003, 0, 0, 0},
   10.81 +	{0x8086, 0x1004, 0x8086, 0x1004, 0, 0, 0},
   10.82 +	{0x8086, 0x1008, 0x8086, 0x1107, 0, 0, 0},
   10.83 +	{0x8086, 0x1009, 0x8086, 0x1109, 0, 0, 0},
   10.84 +	{0x8086, 0x100C, 0x8086, 0x1112, 0, 0, 0},
   10.85 +	{0x8086, 0x100E, 0x8086, 0x001E, 0, 0, 0},
   10.86 +	/* Compaq Gigabit Ethernet Server Adapter */
   10.87 +	{0x8086, 0x1000, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   10.88 +	{0x8086, 0x1001, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   10.89 +	{0x8086, 0x1004, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   10.90 +	/* IBM Mobile, Desktop & Server Adapters */
   10.91 +	{0x8086, 0x1000, 0x1014, PCI_ANY_ID, 0, 0, 2},
   10.92 +	{0x8086, 0x1001, 0x1014, PCI_ANY_ID, 0, 0, 2},
   10.93 +	{0x8086, 0x1004, 0x1014, PCI_ANY_ID, 0, 0, 2},
   10.94 +	/* Generic */
   10.95 +	{0x8086, 0x1000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   10.96 +	{0x8086, 0x1001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   10.97 +	{0x8086, 0x1004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   10.98 +	{0x8086, 0x1008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   10.99 +	{0x8086, 0x1009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.100 +	{0x8086, 0x100C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.101 +	{0x8086, 0x100D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.102 +	{0x8086, 0x100E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.103 +	{0x8086, 0x100F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.104 +	{0x8086, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.105 +	{0x8086, 0x1010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.106 +	{0x8086, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.107 +	{0x8086, 0x1016, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.108 +	{0x8086, 0x1017, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.109 +	{0x8086, 0x101E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  10.110 +	/* required last entry */
  10.111 +	{0,}
  10.112 +};
  10.113 +
  10.114 +MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
  10.115 +
  10.116 +static char *e1000_strings[] = {
  10.117 +	"Intel(R) PRO/1000 Network Connection",
  10.118 +	"Compaq Gigabit Ethernet Server Adapter",
  10.119 +	"IBM Mobile, Desktop & Server Adapters"
  10.120 +};
  10.121 +
  10.122 +/* Local Function Prototypes */
  10.123 +
  10.124 +int e1000_up(struct e1000_adapter *adapter);
  10.125 +void e1000_down(struct e1000_adapter *adapter);
  10.126 +void e1000_reset(struct e1000_adapter *adapter);
  10.127 +
  10.128 +static int e1000_init_module(void);
  10.129 +static void e1000_exit_module(void);
  10.130 +static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  10.131 +static void e1000_remove(struct pci_dev *pdev);
  10.132 +static int e1000_sw_init(struct e1000_adapter *adapter);
  10.133 +static int e1000_open(struct net_device *netdev);
  10.134 +static int e1000_close(struct net_device *netdev);
  10.135 +static int e1000_setup_tx_resources(struct e1000_adapter *adapter);
  10.136 +static int e1000_setup_rx_resources(struct e1000_adapter *adapter);
  10.137 +static void e1000_configure_tx(struct e1000_adapter *adapter);
  10.138 +static void e1000_configure_rx(struct e1000_adapter *adapter);
  10.139 +static void e1000_setup_rctl(struct e1000_adapter *adapter);
  10.140 +static void e1000_clean_tx_ring(struct e1000_adapter *adapter);
  10.141 +static void e1000_clean_rx_ring(struct e1000_adapter *adapter);
  10.142 +static void e1000_free_tx_resources(struct e1000_adapter *adapter);
  10.143 +static void e1000_free_rx_resources(struct e1000_adapter *adapter);
  10.144 +static void e1000_set_multi(struct net_device *netdev);
  10.145 +static void e1000_update_phy_info(unsigned long data);
  10.146 +static void e1000_watchdog(unsigned long data);
  10.147 +static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  10.148 +static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
  10.149 +static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
  10.150 +static int e1000_set_mac(struct net_device *netdev, void *p);
  10.151 +static void e1000_update_stats(struct e1000_adapter *adapter);
  10.152 +static inline void e1000_irq_disable(struct e1000_adapter *adapter);
  10.153 +static inline void e1000_irq_enable(struct e1000_adapter *adapter);
  10.154 +static void e1000_intr(int irq, void *data, struct pt_regs *regs);
  10.155 +static void e1000_clean_tx_irq(struct e1000_adapter *adapter);
  10.156 +static void e1000_clean_rx_irq(struct e1000_adapter *adapter);
  10.157 +static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
  10.158 +static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
  10.159 +static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
  10.160 +static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
  10.161 +static inline void e1000_rx_checksum(struct e1000_adapter *adapter,
  10.162 +                                     struct e1000_rx_desc *rx_desc,
  10.163 +                                     struct sk_buff *skb);
  10.164 +static void e1000_tx_timeout(struct net_device *dev);
  10.165 +static void e1000_tx_timeout_task(struct net_device *dev);
  10.166 +
  10.167 +static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
  10.168 +static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
  10.169 +static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
  10.170 +static void e1000_restore_vlan(struct e1000_adapter *adapter);
  10.171 +
  10.172 +static int e1000_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
  10.173 +static int e1000_suspend(struct pci_dev *pdev, uint32_t state);
  10.174 +#ifdef CONFIG_PM
  10.175 +static int e1000_resume(struct pci_dev *pdev);
  10.176 +#endif
  10.177 +
  10.178 +struct notifier_block e1000_notifier_reboot = {
  10.179 +	.notifier_call	= e1000_notify_reboot,
  10.180 +	.next		= NULL,
  10.181 +	.priority	= 0
  10.182 +};
  10.183 +
  10.184 +/* Exported from other modules */
  10.185 +
  10.186 +extern void e1000_check_options(struct e1000_adapter *adapter);
  10.187 +extern int e1000_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr);
  10.188 +
  10.189 +static struct pci_driver e1000_driver = {
  10.190 +	.name     = e1000_driver_name,
  10.191 +	.id_table = e1000_pci_tbl,
  10.192 +	.probe    = e1000_probe,
  10.193 +	.remove   = __devexit_p(e1000_remove),
  10.194 +	/* Power Managment Hooks */
  10.195 +#ifdef CONFIG_PM
  10.196 +	.suspend  = e1000_suspend,
  10.197 +	.resume   = e1000_resume
  10.198 +#endif
  10.199 +};
  10.200 +
  10.201 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  10.202 +MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
  10.203 +MODULE_LICENSE("GPL");
  10.204 +
  10.205 +/**
  10.206 + * e1000_init_module - Driver Registration Routine
  10.207 + *
  10.208 + * e1000_init_module is the first routine called when the driver is
  10.209 + * loaded. All it does is register with the PCI subsystem.
  10.210 + **/
  10.211 +
  10.212 +static int __init
  10.213 +e1000_init_module(void)
  10.214 +{
  10.215 +	int ret;
  10.216 +	printk(KERN_INFO "%s - version %s\n",
  10.217 +	       e1000_driver_string, e1000_driver_version);
  10.218 +
  10.219 +	printk(KERN_INFO "%s\n", e1000_copyright);
  10.220 +
  10.221 +	ret = pci_module_init(&e1000_driver);
  10.222 +//	if(ret >= 0)
  10.223 +//		register_reboot_notifier(&e1000_notifier_reboot);
  10.224 +	return ret;
  10.225 +}
  10.226 +
  10.227 +module_init(e1000_init_module);
  10.228 +
  10.229 +/**
  10.230 + * e1000_exit_module - Driver Exit Cleanup Routine
  10.231 + *
  10.232 + * e1000_exit_module is called just before the driver is removed
  10.233 + * from memory.
  10.234 + **/
  10.235 +
  10.236 +static void __exit
  10.237 +e1000_exit_module(void)
  10.238 +{
  10.239 +//	unregister_reboot_notifier(&e1000_notifier_reboot);
  10.240 +	pci_unregister_driver(&e1000_driver);
  10.241 +}
  10.242 +
  10.243 +module_exit(e1000_exit_module);
  10.244 +
  10.245 +
  10.246 +int
  10.247 +e1000_up(struct e1000_adapter *adapter)
  10.248 +{
  10.249 +	struct net_device *netdev = adapter->netdev;
  10.250 +
  10.251 +	if(request_irq(netdev->irq, &e1000_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
  10.252 +	               netdev->name, netdev))
  10.253 +		return -1;
  10.254 +
  10.255 +	/* hardware has been reset, we need to reload some things */
  10.256 +
  10.257 +	e1000_set_multi(netdev);
  10.258 +	e1000_restore_vlan(adapter);
  10.259 +
  10.260 +	e1000_configure_tx(adapter);
  10.261 +	e1000_setup_rctl(adapter);
  10.262 +	e1000_configure_rx(adapter);
  10.263 +	e1000_alloc_rx_buffers(adapter);
  10.264 +
  10.265 +	mod_timer(&adapter->watchdog_timer, jiffies);
  10.266 +	e1000_irq_enable(adapter);
  10.267 +
  10.268 +	return 0;
  10.269 +}
  10.270 +
  10.271 +void
  10.272 +e1000_down(struct e1000_adapter *adapter)
  10.273 +{
  10.274 +	struct net_device *netdev = adapter->netdev;
  10.275 +
  10.276 +	e1000_irq_disable(adapter);
  10.277 +	free_irq(netdev->irq, netdev);
  10.278 +	del_timer_sync(&adapter->watchdog_timer);
  10.279 +	del_timer_sync(&adapter->phy_info_timer);
  10.280 +	adapter->link_speed = 0;
  10.281 +	adapter->link_duplex = 0;
  10.282 +	netif_carrier_off(netdev);
  10.283 +	netif_stop_queue(netdev);
  10.284 +
  10.285 +	e1000_reset(adapter);
  10.286 +	e1000_clean_tx_ring(adapter);
  10.287 +	e1000_clean_rx_ring(adapter);
  10.288 +}
  10.289 +
  10.290 +void
  10.291 +e1000_reset(struct e1000_adapter *adapter)
  10.292 +{
  10.293 +	/* Repartition Pba for greater than 9k mtu
  10.294 +	 * To take effect CTRL.RST is required.
  10.295 +	 */
  10.296 +
  10.297 +	if(adapter->rx_buffer_len > E1000_RXBUFFER_8192)
  10.298 +		E1000_WRITE_REG(&adapter->hw, PBA, E1000_JUMBO_PBA);
  10.299 +	else
  10.300 +		E1000_WRITE_REG(&adapter->hw, PBA, E1000_DEFAULT_PBA);
  10.301 +
  10.302 +	adapter->hw.fc = adapter->hw.original_fc;
  10.303 +	e1000_reset_hw(&adapter->hw);
  10.304 +printk("RESET_H/W\n");
  10.305 +	if(adapter->hw.mac_type >= e1000_82544)
  10.306 +		E1000_WRITE_REG(&adapter->hw, WUC, 0);
  10.307 +	e1000_init_hw(&adapter->hw);
  10.308 +printk("INIT H/W\n");
  10.309 +	e1000_reset_adaptive(&adapter->hw);
  10.310 +	e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
  10.311 +}
  10.312 +
  10.313 +/**
  10.314 + * e1000_probe - Device Initialization Routine
  10.315 + * @pdev: PCI device information struct
  10.316 + * @ent: entry in e1000_pci_tbl
  10.317 + *
  10.318 + * Returns 0 on success, negative on failure
  10.319 + *
  10.320 + * e1000_probe initializes an adapter identified by a pci_dev structure.
  10.321 + * The OS initialization, configuring of the adapter private structure,
  10.322 + * and a hardware reset occur.
  10.323 + **/
  10.324 +
  10.325 +static int __devinit
  10.326 +e1000_probe(struct pci_dev *pdev,
  10.327 +            const struct pci_device_id *ent)
  10.328 +{
  10.329 +	struct net_device *netdev;
  10.330 +	struct e1000_adapter *adapter;
  10.331 +	static int cards_found = 0;
  10.332 +	unsigned long mmio_start;
  10.333 +	int mmio_len;
  10.334 +	int pci_using_dac;
  10.335 +	int i;
  10.336 +	uint16_t eeprom_data;
  10.337 +
  10.338 +	if((i = pci_enable_device(pdev)))
  10.339 +		return i;
  10.340 +
  10.341 +	if(!(i = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
  10.342 +		pci_using_dac = 1;
  10.343 +	} else {
  10.344 +		if((i = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
  10.345 +			E1000_ERR("No usable DMA configuration, aborting\n");
  10.346 +			return i;
  10.347 +		}
  10.348 +		pci_using_dac = 0;
  10.349 +	}
  10.350 +
  10.351 +	if((i = pci_request_regions(pdev, e1000_driver_name)))
  10.352 +		return i;
  10.353 +
  10.354 +	pci_set_master(pdev);
  10.355 +
  10.356 +	netdev = alloc_etherdev(sizeof(struct e1000_adapter));
  10.357 +	if(!netdev)
  10.358 +		goto err_alloc_etherdev;
  10.359 +
  10.360 +	SET_MODULE_OWNER(netdev);
  10.361 +
  10.362 +	pci_set_drvdata(pdev, netdev);
  10.363 +	adapter = netdev->priv;
  10.364 +	adapter->netdev = netdev;
  10.365 +	adapter->pdev = pdev;
  10.366 +	adapter->hw.back = adapter;
  10.367 +
  10.368 +	mmio_start = pci_resource_start(pdev, BAR_0);
  10.369 +	mmio_len = pci_resource_len(pdev, BAR_0);
  10.370 +
  10.371 +	adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  10.372 +	if(!adapter->hw.hw_addr)
  10.373 +		goto err_ioremap;
  10.374 +
  10.375 +	for(i = BAR_1; i <= BAR_5; i++) {
  10.376 +		if(pci_resource_len(pdev, i) == 0)
  10.377 +			continue;
  10.378 +		if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  10.379 +			adapter->hw.io_base = pci_resource_start(pdev, i);
  10.380 +			break;
  10.381 +		}
  10.382 +	}
  10.383 +
  10.384 +	netdev->open = &e1000_open;
  10.385 +	netdev->stop = &e1000_close;
  10.386 +	netdev->hard_start_xmit = &e1000_xmit_frame;
  10.387 +	netdev->get_stats = &e1000_get_stats;
  10.388 +	netdev->set_multicast_list = &e1000_set_multi;
  10.389 +	netdev->set_mac_address = &e1000_set_mac;
  10.390 +	netdev->change_mtu = &e1000_change_mtu;
  10.391 +	netdev->do_ioctl = &e1000_ioctl;
  10.392 +	netdev->tx_timeout = &e1000_tx_timeout;
  10.393 +	netdev->watchdog_timeo = HZ;
  10.394 +	netdev->vlan_rx_register = e1000_vlan_rx_register;
  10.395 +	netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
  10.396 +	netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
  10.397 +
  10.398 +	netdev->irq = pdev->irq;
  10.399 +	netdev->mem_start = mmio_start;
  10.400 +	netdev->mem_end = mmio_start + mmio_len;
  10.401 +	netdev->base_addr = adapter->hw.io_base;
  10.402 +
  10.403 +	adapter->bd_number = cards_found;
  10.404 +	adapter->id_string = e1000_strings[ent->driver_data];
  10.405 +
  10.406 +	/* setup the private structure */
  10.407 +
  10.408 +	if(e1000_sw_init(adapter))
  10.409 +		goto err_sw_init;
  10.410 +
  10.411 +	if(adapter->hw.mac_type >= e1000_82543) {
  10.412 +		netdev->features = NETIF_F_SG |
  10.413 +			           NETIF_F_HW_CSUM |
  10.414 +		       	           NETIF_F_HW_VLAN_TX |
  10.415 +		                   NETIF_F_HW_VLAN_RX |
  10.416 +				   NETIF_F_HW_VLAN_FILTER;
  10.417 +	} else {
  10.418 +		netdev->features = NETIF_F_SG;
  10.419 +	}
  10.420 +
  10.421 +	if(pci_using_dac)
  10.422 +		netdev->features |= NETIF_F_HIGHDMA;
  10.423 +
  10.424 +	/* make sure the EEPROM is good */
  10.425 +
  10.426 +	if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
  10.427 +		printk(KERN_ERR "The EEPROM Checksum Is Not Valid\n");
  10.428 +		goto err_eeprom;
  10.429 +	}
  10.430 +
  10.431 +	/* copy the MAC address out of the EEPROM */
  10.432 +
  10.433 +	e1000_read_mac_addr(&adapter->hw);
  10.434 +	memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  10.435 +
  10.436 +	if(!is_valid_ether_addr(netdev->dev_addr))
  10.437 +		goto err_eeprom;
  10.438 +
  10.439 +	e1000_read_part_num(&adapter->hw, &(adapter->part_num));
  10.440 +
  10.441 +	e1000_get_bus_info(&adapter->hw);
  10.442 +
  10.443 +	if((adapter->hw.mac_type == e1000_82544) &&
  10.444 +	   (adapter->hw.bus_type == e1000_bus_type_pcix))
  10.445 +
  10.446 +		adapter->max_data_per_txd = 4096;
  10.447 +	else
  10.448 +		adapter->max_data_per_txd = MAX_JUMBO_FRAME_SIZE;
  10.449 +
  10.450 +
  10.451 +	init_timer(&adapter->watchdog_timer);
  10.452 +	adapter->watchdog_timer.function = &e1000_watchdog;
  10.453 +	adapter->watchdog_timer.data = (unsigned long) adapter;
  10.454 +
  10.455 +	init_timer(&adapter->phy_info_timer);
  10.456 +	adapter->phy_info_timer.function = &e1000_update_phy_info;
  10.457 +	adapter->phy_info_timer.data = (unsigned long) adapter;
  10.458 +
  10.459 +	INIT_TQUEUE(&adapter->tx_timeout_task,
  10.460 +		(void (*)(void *))e1000_tx_timeout_task, netdev);
  10.461 +
  10.462 +	register_netdev(netdev);
  10.463 +	memcpy(adapter->ifname, netdev->name, IFNAMSIZ);
  10.464 +	adapter->ifname[IFNAMSIZ-1] = 0;
  10.465 +
  10.466 +	/* we're going to reset, so assume we have no link for now */
  10.467 +
  10.468 +	netif_carrier_off(netdev);
  10.469 +	netif_stop_queue(netdev);
  10.470 +
  10.471 +	printk(KERN_INFO "%s: %s\n", netdev->name, adapter->id_string);
  10.472 +	e1000_check_options(adapter);
  10.473 +printk("OPTIONS OVER\n");
  10.474 +	/* Initial Wake on LAN setting
  10.475 +	 * If APM wake is enabled in the EEPROM,
  10.476 +	 * enable the ACPI Magic Packet filter
  10.477 +	 */
  10.478 +
  10.479 +	e1000_read_eeprom(&adapter->hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data);
  10.480 +printk("EPROM OVER\n");
  10.481 +	if((adapter->hw.mac_type >= e1000_82544) &&
  10.482 +	   (eeprom_data & E1000_EEPROM_APME))
  10.483 +		adapter->wol |= E1000_WUFC_MAG;
  10.484 +
  10.485 +	/* reset the hardware with the new settings */
  10.486 +
  10.487 +	e1000_reset(adapter);
  10.488 +printk("PROBE OVER\n");
  10.489 +	cards_found++;
  10.490 +	return 0;
  10.491 +
  10.492 +err_sw_init:
  10.493 +err_eeprom:
  10.494 +	iounmap(adapter->hw.hw_addr);
  10.495 +err_ioremap:
  10.496 +	pci_release_regions(pdev);
  10.497 +	kfree(netdev);
  10.498 +err_alloc_etherdev:
  10.499 +	return -ENOMEM;
  10.500 +}
  10.501 +
  10.502 +/**
  10.503 + * e1000_remove - Device Removal Routine
  10.504 + * @pdev: PCI device information struct
  10.505 + *
  10.506 + * e1000_remove is called by the PCI subsystem to alert the driver
  10.507 + * that it should release a PCI device.  The could be caused by a
  10.508 + * Hot-Plug event, or because the driver is going to be removed from
  10.509 + * memory.
  10.510 + **/
  10.511 +
  10.512 +static void __devexit
  10.513 +e1000_remove(struct pci_dev *pdev)
  10.514 +{
  10.515 +	struct net_device *netdev = pci_get_drvdata(pdev);
  10.516 +	struct e1000_adapter *adapter = netdev->priv;
  10.517 +	uint32_t manc;
  10.518 +
  10.519 +	if(adapter->hw.mac_type >= e1000_82540) {
  10.520 +		manc = E1000_READ_REG(&adapter->hw, MANC);
  10.521 +		if(manc & E1000_MANC_SMBUS_EN) {
  10.522 +			manc |= E1000_MANC_ARP_EN;
  10.523 +			E1000_WRITE_REG(&adapter->hw, MANC, manc);
  10.524 +		}
  10.525 +	}
  10.526 +
  10.527 +	unregister_netdev(netdev);
  10.528 +
  10.529 +	e1000_phy_hw_reset(&adapter->hw);
  10.530 +
  10.531 +	iounmap(adapter->hw.hw_addr);
  10.532 +	pci_release_regions(pdev);
  10.533 +
  10.534 +	kfree(netdev);
  10.535 +}
  10.536 +
  10.537 +/**
  10.538 + * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  10.539 + * @adapter: board private structure to initialize
  10.540 + *
  10.541 + * e1000_sw_init initializes the Adapter private data structure.
  10.542 + * Fields are initialized based on PCI device information and
  10.543 + * OS network device settings (MTU size).
  10.544 + **/
  10.545 +
  10.546 +static int __devinit
  10.547 +e1000_sw_init(struct e1000_adapter *adapter)
  10.548 +{
  10.549 +	struct e1000_hw *hw = &adapter->hw;
  10.550 +	struct net_device *netdev = adapter->netdev;
  10.551 +	struct pci_dev *pdev = adapter->pdev;
  10.552 +
  10.553 +	/* PCI config space info */
  10.554 +
  10.555 +	hw->vendor_id = pdev->vendor;
  10.556 +	hw->device_id = pdev->device;
  10.557 +	hw->subsystem_vendor_id = pdev->subsystem_vendor;
  10.558 +	hw->subsystem_id = pdev->subsystem_device;
  10.559 +
  10.560 +	pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
  10.561 +
  10.562 +	pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
  10.563 +
  10.564 +	adapter->rx_buffer_len = E1000_RXBUFFER_2048;
  10.565 +	hw->max_frame_size = netdev->mtu +
  10.566 +	                         ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
  10.567 +	hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
  10.568 +
  10.569 +	/* identify the MAC */
  10.570 +
  10.571 +	if (e1000_set_mac_type(hw)) {
  10.572 +		E1000_ERR("Unknown MAC Type\n");
  10.573 +		return -1;
  10.574 +	}
  10.575 +
  10.576 +	/* flow control settings */
  10.577 +
  10.578 +	hw->fc_high_water = E1000_FC_HIGH_THRESH;
  10.579 +	hw->fc_low_water = E1000_FC_LOW_THRESH;
  10.580 +	hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  10.581 +	hw->fc_send_xon = 1;
  10.582 +
  10.583 +	/* Media type - copper or fiber */
  10.584 +
  10.585 +	if(hw->mac_type >= e1000_82543) {
  10.586 +		uint32_t status = E1000_READ_REG(hw, STATUS);
  10.587 +
  10.588 +		if(status & E1000_STATUS_TBIMODE)
  10.589 +			hw->media_type = e1000_media_type_fiber;
  10.590 +		else
  10.591 +			hw->media_type = e1000_media_type_copper;
  10.592 +	} else {
  10.593 +		hw->media_type = e1000_media_type_fiber;
  10.594 +	}
  10.595 +
  10.596 +	if(hw->mac_type < e1000_82543)
  10.597 +		hw->report_tx_early = 0;
  10.598 +	else
  10.599 +		hw->report_tx_early = 1;
  10.600 +
  10.601 +	hw->wait_autoneg_complete = FALSE;
  10.602 +	hw->tbi_compatibility_en = TRUE;
  10.603 +	hw->adaptive_ifs = TRUE;
  10.604 +
  10.605 +	/* Copper options */
  10.606 +
  10.607 +	if(hw->media_type == e1000_media_type_copper) {
  10.608 +		hw->mdix = AUTO_ALL_MODES;
  10.609 +		hw->disable_polarity_correction = FALSE;
  10.610 +	}
  10.611 +
  10.612 +	atomic_set(&adapter->irq_sem, 1);
  10.613 +	spin_lock_init(&adapter->stats_lock);
  10.614 +
  10.615 +	return 0;
  10.616 +}
  10.617 +
  10.618 +/**
  10.619 + * e1000_open - Called when a network interface is made active
  10.620 + * @netdev: network interface device structure
  10.621 + *
  10.622 + * Returns 0 on success, negative value on failure
  10.623 + *
  10.624 + * The open entry point is called when a network interface is made
  10.625 + * active by the system (IFF_UP).  At this point all resources needed
  10.626 + * for transmit and receive operations are allocated, the interrupt
  10.627 + * handler is registered with the OS, the watchdog timer is started,
  10.628 + * and the stack is notified that the interface is ready.
  10.629 + **/
  10.630 +
  10.631 +static int
  10.632 +e1000_open(struct net_device *netdev)
  10.633 +{
  10.634 +	struct e1000_adapter *adapter = netdev->priv;
  10.635 +
  10.636 +	/* allocate transmit descriptors */
  10.637 +
  10.638 +	if(e1000_setup_tx_resources(adapter))
  10.639 +		goto err_setup_tx;
  10.640 +
  10.641 +	/* allocate receive descriptors */
  10.642 +
  10.643 +	if(e1000_setup_rx_resources(adapter))
  10.644 +		goto err_setup_rx;
  10.645 +
  10.646 +	if(e1000_up(adapter))
  10.647 +		goto err_up;
  10.648 +
  10.649 +	return 0;
  10.650 +
  10.651 +err_up:
  10.652 +	e1000_free_rx_resources(adapter);
  10.653 +err_setup_rx:
  10.654 +	e1000_free_tx_resources(adapter);
  10.655 +err_setup_tx:
  10.656 +	e1000_reset(adapter);
  10.657 +
  10.658 +	return -EBUSY;
  10.659 +}
  10.660 +
  10.661 +/**
  10.662 + * e1000_close - Disables a network interface
  10.663 + * @netdev: network interface device structure
  10.664 + *
  10.665 + * Returns 0, this is not allowed to fail
  10.666 + *
  10.667 + * The close entry point is called when an interface is de-activated
  10.668 + * by the OS.  The hardware is still under the drivers control, but
  10.669 + * needs to be disabled.  A global MAC reset is issued to stop the
  10.670 + * hardware, and all transmit and receive resources are freed.
  10.671 + **/
  10.672 +
  10.673 +static int
  10.674 +e1000_close(struct net_device *netdev)
  10.675 +{
  10.676 +	struct e1000_adapter *adapter = netdev->priv;
  10.677 +
  10.678 +	e1000_down(adapter);
  10.679 +
  10.680 +	e1000_free_tx_resources(adapter);
  10.681 +	e1000_free_rx_resources(adapter);
  10.682 +
  10.683 +	return 0;
  10.684 +}
  10.685 +
  10.686 +/**
  10.687 + * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
  10.688 + * @adapter: board private structure
  10.689 + *
  10.690 + * Return 0 on success, negative on failure
  10.691 + **/
  10.692 +
  10.693 +static int
  10.694 +e1000_setup_tx_resources(struct e1000_adapter *adapter)
  10.695 +{
  10.696 +	struct e1000_desc_ring *txdr = &adapter->tx_ring;
  10.697 +	struct pci_dev *pdev = adapter->pdev;
  10.698 +	int size;
  10.699 +
  10.700 +	size = sizeof(struct e1000_buffer) * txdr->count;
  10.701 +	txdr->buffer_info = kmalloc(size, GFP_KERNEL);
  10.702 +	if(!txdr->buffer_info) {
  10.703 +		return -ENOMEM;
  10.704 +	}
  10.705 +	memset(txdr->buffer_info, 0, size);
  10.706 +
  10.707 +	/* round up to nearest 4K */
  10.708 +
  10.709 +	txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
  10.710 +	E1000_ROUNDUP(txdr->size, 4096);
  10.711 +
  10.712 +	txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  10.713 +	if(!txdr->desc) {
  10.714 +		kfree(txdr->buffer_info);
  10.715 +		return -ENOMEM;
  10.716 +	}
  10.717 +	memset(txdr->desc, 0, txdr->size);
  10.718 +
  10.719 +	txdr->next_to_use = 0;
  10.720 +	txdr->next_to_clean = 0;
  10.721 +
  10.722 +	return 0;
  10.723 +}
  10.724 +
  10.725 +/**
  10.726 + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  10.727 + * @adapter: board private structure
  10.728 + *
  10.729 + * Configure the Tx unit of the MAC after a reset.
  10.730 + **/
  10.731 +
  10.732 +static void
  10.733 +e1000_configure_tx(struct e1000_adapter *adapter)
  10.734 +{
  10.735 +	uint64_t tdba = adapter->tx_ring.dma;
  10.736 +	uint32_t tdlen = adapter->tx_ring.count * sizeof(struct e1000_tx_desc);
  10.737 +	uint32_t tctl, tipg;
  10.738 +
  10.739 +	E1000_WRITE_REG(&adapter->hw, TDBAL, (tdba & 0x00000000ffffffffULL));
  10.740 +	E1000_WRITE_REG(&adapter->hw, TDBAH, (tdba >> 32));
  10.741 +
  10.742 +	E1000_WRITE_REG(&adapter->hw, TDLEN, tdlen);
  10.743 +
  10.744 +	/* Setup the HW Tx Head and Tail descriptor pointers */
  10.745 +
  10.746 +	E1000_WRITE_REG(&adapter->hw, TDH, 0);
  10.747 +	E1000_WRITE_REG(&adapter->hw, TDT, 0);
  10.748 +
  10.749 +	/* Set the default values for the Tx Inter Packet Gap timer */
  10.750 +
  10.751 +	switch (adapter->hw.mac_type) {
  10.752 +	case e1000_82542_rev2_0:
  10.753 +	case e1000_82542_rev2_1:
  10.754 +		tipg = DEFAULT_82542_TIPG_IPGT;
  10.755 +		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  10.756 +		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  10.757 +		break;
  10.758 +	default:
  10.759 +		if(adapter->hw.media_type == e1000_media_type_fiber)
  10.760 +			tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  10.761 +		else
  10.762 +			tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  10.763 +		tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  10.764 +		tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  10.765 +	}
  10.766 +	E1000_WRITE_REG(&adapter->hw, TIPG, tipg);
  10.767 +
  10.768 +	/* Set the Tx Interrupt Delay register */
  10.769 +
  10.770 +	E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay);
  10.771 +	if(adapter->hw.mac_type >= e1000_82540)
  10.772 +		E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay);
  10.773 +
  10.774 +	/* Program the Transmit Control Register */
  10.775 +
  10.776 +	tctl = E1000_READ_REG(&adapter->hw, TCTL);
  10.777 +
  10.778 +	tctl &= ~E1000_TCTL_CT;
  10.779 +	tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  10.780 +	       (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  10.781 +
  10.782 +	E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
  10.783 +
  10.784 +	e1000_config_collision_dist(&adapter->hw);
  10.785 +
  10.786 +	/* Setup Transmit Descriptor Settings for this adapter */
  10.787 +	adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE;
  10.788 +
  10.789 +	if(adapter->hw.report_tx_early == 1)
  10.790 +		adapter->txd_cmd |= E1000_TXD_CMD_RS;
  10.791 +	else
  10.792 +		adapter->txd_cmd |= E1000_TXD_CMD_RPS;
  10.793 +}
  10.794 +
  10.795 +/**
  10.796 + * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
  10.797 + * @adapter: board private structure
  10.798 + *
  10.799 + * Returns 0 on success, negative on failure
  10.800 + **/
  10.801 +
  10.802 +static int
  10.803 +e1000_setup_rx_resources(struct e1000_adapter *adapter)
  10.804 +{
  10.805 +	struct e1000_desc_ring *rxdr = &adapter->rx_ring;
  10.806 +	struct pci_dev *pdev = adapter->pdev;
  10.807 +	int size;
  10.808 +
  10.809 +	size = sizeof(struct e1000_buffer) * rxdr->count;
  10.810 +	rxdr->buffer_info = kmalloc(size, GFP_KERNEL);
  10.811 +	if(!rxdr->buffer_info) {
  10.812 +		return -ENOMEM;
  10.813 +	}
  10.814 +	memset(rxdr->buffer_info, 0, size);
  10.815 +
  10.816 +	/* Round up to nearest 4K */
  10.817 +
  10.818 +	rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
  10.819 +	E1000_ROUNDUP(rxdr->size, 4096);
  10.820 +
  10.821 +	rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  10.822 +
  10.823 +	if(!rxdr->desc) {
  10.824 +		kfree(rxdr->buffer_info);
  10.825 +		return -ENOMEM;
  10.826 +	}
  10.827 +	memset(rxdr->desc, 0, rxdr->size);
  10.828 +
  10.829 +	rxdr->next_to_clean = 0;
  10.830 +	rxdr->next_to_use = 0;
  10.831 +
  10.832 +	return 0;
  10.833 +}
  10.834 +
  10.835 +/**
  10.836 + * e1000_setup_rctl - configure the receive control register
  10.837 + * @adapter: Board private structure
  10.838 + **/
  10.839 +
  10.840 +static void
  10.841 +e1000_setup_rctl(struct e1000_adapter *adapter)
  10.842 +{
  10.843 +	uint32_t rctl;
  10.844 +
  10.845 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
  10.846 +
  10.847 +	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  10.848 +
  10.849 +	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
  10.850 +	        E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
  10.851 +	        (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
  10.852 +
  10.853 +	if(adapter->hw.tbi_compatibility_on == 1)
  10.854 +		rctl |= E1000_RCTL_SBP;
  10.855 +	else
  10.856 +		rctl &= ~E1000_RCTL_SBP;
  10.857 +
  10.858 +	rctl &= ~(E1000_RCTL_SZ_4096);
  10.859 +	switch (adapter->rx_buffer_len) {
  10.860 +	case E1000_RXBUFFER_2048:
  10.861 +	default:
  10.862 +		rctl |= E1000_RCTL_SZ_2048;
  10.863 +		rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  10.864 +		break;
  10.865 +	case E1000_RXBUFFER_4096:
  10.866 +		rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  10.867 +		break;
  10.868 +	case E1000_RXBUFFER_8192:
  10.869 +		rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  10.870 +		break;
  10.871 +	case E1000_RXBUFFER_16384:
  10.872 +		rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  10.873 +		break;
  10.874 +	}
  10.875 +
  10.876 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  10.877 +}
  10.878 +
  10.879 +/**
  10.880 + * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  10.881 + * @adapter: board private structure
  10.882 + *
  10.883 + * Configure the Rx unit of the MAC after a reset.
  10.884 + **/
  10.885 +
  10.886 +static void
  10.887 +e1000_configure_rx(struct e1000_adapter *adapter)
  10.888 +{
  10.889 +	uint64_t rdba = adapter->rx_ring.dma;
  10.890 +	uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
  10.891 +	uint32_t rctl;
  10.892 +	uint32_t rxcsum;
  10.893 +
  10.894 +	/* make sure receives are disabled while setting up the descriptors */
  10.895 +
  10.896 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
  10.897 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
  10.898 +
  10.899 +	/* set the Receive Delay Timer Register */
  10.900 +
  10.901 +	E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay);
  10.902 +
  10.903 +	if(adapter->hw.mac_type >= e1000_82540) {
  10.904 +		E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay);
  10.905 +
  10.906 +		/* Set the interrupt throttling rate.  Value is calculated
  10.907 +		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  10.908 +#define MAX_INTS_PER_SEC        8000
  10.909 +#define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
  10.910 +		E1000_WRITE_REG(&adapter->hw, ITR, DEFAULT_ITR);
  10.911 +	}
  10.912 +
  10.913 +	/* Setup the Base and Length of the Rx Descriptor Ring */
  10.914 +
  10.915 +	E1000_WRITE_REG(&adapter->hw, RDBAL, (rdba & 0x00000000ffffffffULL));
  10.916 +	E1000_WRITE_REG(&adapter->hw, RDBAH, (rdba >> 32));
  10.917 +
  10.918 +	E1000_WRITE_REG(&adapter->hw, RDLEN, rdlen);
  10.919 +
  10.920 +	/* Setup the HW Rx Head and Tail Descriptor Pointers */
  10.921 +	E1000_WRITE_REG(&adapter->hw, RDH, 0);
  10.922 +	E1000_WRITE_REG(&adapter->hw, RDT, 0);
  10.923 +
  10.924 +	/* Enable 82543 Receive Checksum Offload for TCP and UDP */
  10.925 +	if((adapter->hw.mac_type >= e1000_82543) &&
  10.926 +	   (adapter->rx_csum == TRUE)) {
  10.927 +		rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
  10.928 +		rxcsum |= E1000_RXCSUM_TUOFL;
  10.929 +		E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
  10.930 +	}
  10.931 +
  10.932 +	/* Enable Receives */
  10.933 +
  10.934 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  10.935 +}
  10.936 +
  10.937 +/**
  10.938 + * e1000_free_tx_resources - Free Tx Resources
  10.939 + * @adapter: board private structure
  10.940 + *
  10.941 + * Free all transmit software resources
  10.942 + **/
  10.943 +
  10.944 +static void
  10.945 +e1000_free_tx_resources(struct e1000_adapter *adapter)
  10.946 +{
  10.947 +	struct pci_dev *pdev = adapter->pdev;
  10.948 +
  10.949 +	e1000_clean_tx_ring(adapter);
  10.950 +
  10.951 +	kfree(adapter->tx_ring.buffer_info);
  10.952 +	adapter->tx_ring.buffer_info = NULL;
  10.953 +
  10.954 +	pci_free_consistent(pdev, adapter->tx_ring.size,
  10.955 +	                    adapter->tx_ring.desc, adapter->tx_ring.dma);
  10.956 +
  10.957 +	adapter->tx_ring.desc = NULL;
  10.958 +}
  10.959 +
  10.960 +/**
  10.961 + * e1000_clean_tx_ring - Free Tx Buffers
  10.962 + * @adapter: board private structure
  10.963 + **/
  10.964 +
  10.965 +static void
  10.966 +e1000_clean_tx_ring(struct e1000_adapter *adapter)
  10.967 +{
  10.968 +	struct pci_dev *pdev = adapter->pdev;
  10.969 +	unsigned long size;
  10.970 +	int i;
  10.971 +
  10.972 +	/* Free all the Tx ring sk_buffs */
  10.973 +
  10.974 +	for(i = 0; i < adapter->tx_ring.count; i++) {
  10.975 +		if(adapter->tx_ring.buffer_info[i].skb) {
  10.976 +
  10.977 +			pci_unmap_page(pdev,
  10.978 +			               adapter->tx_ring.buffer_info[i].dma,
  10.979 +			               adapter->tx_ring.buffer_info[i].length,
  10.980 +			               PCI_DMA_TODEVICE);
  10.981 +
  10.982 +			dev_kfree_skb(adapter->tx_ring.buffer_info[i].skb);
  10.983 +
  10.984 +			adapter->tx_ring.buffer_info[i].skb = NULL;
  10.985 +		}
  10.986 +	}
  10.987 +
  10.988 +	size = sizeof(struct e1000_buffer) * adapter->tx_ring.count;
  10.989 +	memset(adapter->tx_ring.buffer_info, 0, size);
  10.990 +
  10.991 +	/* Zero out the descriptor ring */
  10.992 +
  10.993 +	memset(adapter->tx_ring.desc, 0, adapter->tx_ring.size);
  10.994 +
  10.995 +	adapter->tx_ring.next_to_use = 0;
  10.996 +	adapter->tx_ring.next_to_clean = 0;
  10.997 +
  10.998 +	E1000_WRITE_REG(&adapter->hw, TDH, 0);
  10.999 +	E1000_WRITE_REG(&adapter->hw, TDT, 0);
 10.1000 +}
 10.1001 +
 10.1002 +/**
 10.1003 + * e1000_free_rx_resources - Free Rx Resources
 10.1004 + * @adapter: board private structure
 10.1005 + *
 10.1006 + * Free all receive software resources
 10.1007 + **/
 10.1008 +
 10.1009 +static void
 10.1010 +e1000_free_rx_resources(struct e1000_adapter *adapter)
 10.1011 +{
 10.1012 +	struct pci_dev *pdev = adapter->pdev;
 10.1013 +
 10.1014 +	e1000_clean_rx_ring(adapter);
 10.1015 +
 10.1016 +	kfree(adapter->rx_ring.buffer_info);
 10.1017 +	adapter->rx_ring.buffer_info = NULL;
 10.1018 +
 10.1019 +	pci_free_consistent(pdev, adapter->rx_ring.size,
 10.1020 +	                    adapter->rx_ring.desc, adapter->rx_ring.dma);
 10.1021 +
 10.1022 +	adapter->rx_ring.desc = NULL;
 10.1023 +}
 10.1024 +
 10.1025 +/**
 10.1026 + * e1000_clean_rx_ring - Free Rx Buffers
 10.1027 + * @adapter: board private structure
 10.1028 + **/
 10.1029 +
 10.1030 +static void
 10.1031 +e1000_clean_rx_ring(struct e1000_adapter *adapter)
 10.1032 +{
 10.1033 +	struct pci_dev *pdev = adapter->pdev;
 10.1034 +	unsigned long size;
 10.1035 +	int i;
 10.1036 +
 10.1037 +	/* Free all the Rx ring sk_buffs */
 10.1038 +
 10.1039 +	for(i = 0; i < adapter->rx_ring.count; i++) {
 10.1040 +		if(adapter->rx_ring.buffer_info[i].skb) {
 10.1041 +
 10.1042 +			pci_unmap_single(pdev,
 10.1043 +			                 adapter->rx_ring.buffer_info[i].dma,
 10.1044 +			                 adapter->rx_ring.buffer_info[i].length,
 10.1045 +			                 PCI_DMA_FROMDEVICE);
 10.1046 +
 10.1047 +			dev_kfree_skb(adapter->rx_ring.buffer_info[i].skb);
 10.1048 +
 10.1049 +			adapter->rx_ring.buffer_info[i].skb = NULL;
 10.1050 +		}
 10.1051 +	}
 10.1052 +
 10.1053 +	size = sizeof(struct e1000_buffer) * adapter->rx_ring.count;
 10.1054 +	memset(adapter->rx_ring.buffer_info, 0, size);
 10.1055 +
 10.1056 +	/* Zero out the descriptor ring */
 10.1057 +
 10.1058 +	memset(adapter->rx_ring.desc, 0, adapter->rx_ring.size);
 10.1059 +
 10.1060 +	adapter->rx_ring.next_to_clean = 0;
 10.1061 +	adapter->rx_ring.next_to_use = 0;
 10.1062 +
 10.1063 +	E1000_WRITE_REG(&adapter->hw, RDH, 0);
 10.1064 +	E1000_WRITE_REG(&adapter->hw, RDT, 0);
 10.1065 +}
 10.1066 +
 10.1067 +/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
 10.1068 + * and memory write and invalidate disabled for certain operations
 10.1069 + */
 10.1070 +static void
 10.1071 +e1000_enter_82542_rst(struct e1000_adapter *adapter)
 10.1072 +{
 10.1073 +	struct net_device *netdev = adapter->netdev;
 10.1074 +	uint32_t rctl;
 10.1075 +
 10.1076 +	e1000_pci_clear_mwi(&adapter->hw);
 10.1077 +
 10.1078 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
 10.1079 +	rctl |= E1000_RCTL_RST;
 10.1080 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 10.1081 +	E1000_WRITE_FLUSH(&adapter->hw);
 10.1082 +	mdelay(5);
 10.1083 +
 10.1084 +	if(netif_running(netdev))
 10.1085 +		e1000_clean_rx_ring(adapter);
 10.1086 +}
 10.1087 +
 10.1088 +static void
 10.1089 +e1000_leave_82542_rst(struct e1000_adapter *adapter)
 10.1090 +{
 10.1091 +	struct net_device *netdev = adapter->netdev;
 10.1092 +	uint32_t rctl;
 10.1093 +
 10.1094 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
 10.1095 +	rctl &= ~E1000_RCTL_RST;
 10.1096 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 10.1097 +	E1000_WRITE_FLUSH(&adapter->hw);
 10.1098 +	mdelay(5);
 10.1099 +
 10.1100 +	if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
 10.1101 +		e1000_pci_set_mwi(&adapter->hw);
 10.1102 +
 10.1103 +	if(netif_running(netdev)) {
 10.1104 +		e1000_configure_rx(adapter);
 10.1105 +		e1000_alloc_rx_buffers(adapter);
 10.1106 +	}
 10.1107 +}
 10.1108 +
 10.1109 +/**
 10.1110 + * e1000_set_mac - Change the Ethernet Address of the NIC
 10.1111 + * @netdev: network interface device structure
 10.1112 + * @p: pointer to an address structure
 10.1113 + *
 10.1114 + * Returns 0 on success, negative on failure
 10.1115 + **/
 10.1116 +
 10.1117 +static int
 10.1118 +e1000_set_mac(struct net_device *netdev, void *p)
 10.1119 +{
 10.1120 +	struct e1000_adapter *adapter = netdev->priv;
 10.1121 +	struct sockaddr *addr = p;
 10.1122 +
 10.1123 +	if(!is_valid_ether_addr(addr->sa_data))
 10.1124 +		return -EADDRNOTAVAIL;
 10.1125 +
 10.1126 +	/* 82542 2.0 needs to be in reset to write receive address registers */
 10.1127 +
 10.1128 +	if(adapter->hw.mac_type == e1000_82542_rev2_0)
 10.1129 +		e1000_enter_82542_rst(adapter);
 10.1130 +
 10.1131 +	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 10.1132 +	memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
 10.1133 +
 10.1134 +	e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
 10.1135 +
 10.1136 +	if(adapter->hw.mac_type == e1000_82542_rev2_0)
 10.1137 +		e1000_leave_82542_rst(adapter);
 10.1138 +
 10.1139 +	return 0;
 10.1140 +}
 10.1141 +
 10.1142 +/**
 10.1143 + * e1000_set_multi - Multicast and Promiscuous mode set
 10.1144 + * @netdev: network interface device structure
 10.1145 + *
 10.1146 + * The set_multi entry point is called whenever the multicast address
 10.1147 + * list or the network interface flags are updated.  This routine is
 10.1148 + * resposible for configuring the hardware for proper multicast,
 10.1149 + * promiscuous mode, and all-multi behavior.
 10.1150 + **/
 10.1151 +
 10.1152 +static void
 10.1153 +e1000_set_multi(struct net_device *netdev)
 10.1154 +{
 10.1155 +	struct e1000_adapter *adapter = netdev->priv;
 10.1156 +	struct e1000_hw *hw = &adapter->hw;
 10.1157 +	struct dev_mc_list *mc_ptr;
 10.1158 +	uint32_t rctl;
 10.1159 +	uint32_t hash_value;
 10.1160 +	int i;
 10.1161 +
 10.1162 +	/* Check for Promiscuous and All Multicast modes */
 10.1163 +
 10.1164 +	rctl = E1000_READ_REG(hw, RCTL);
 10.1165 +
 10.1166 +	if(netdev->flags & IFF_PROMISC) {
 10.1167 +		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
 10.1168 +	} else if(netdev->flags & IFF_ALLMULTI) {
 10.1169 +		rctl |= E1000_RCTL_MPE;
 10.1170 +		rctl &= ~E1000_RCTL_UPE;
 10.1171 +	} else {
 10.1172 +		rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
 10.1173 +	}
 10.1174 +
 10.1175 +	E1000_WRITE_REG(hw, RCTL, rctl);
 10.1176 +
 10.1177 +	/* 82542 2.0 needs to be in reset to write receive address registers */
 10.1178 +
 10.1179 +	if(hw->mac_type == e1000_82542_rev2_0)
 10.1180 +		e1000_enter_82542_rst(adapter);
 10.1181 +
 10.1182 +	/* load the first 15 multicast address into the exact filters 1-15
 10.1183 +	 * RAR 0 is used for the station MAC adddress
 10.1184 +	 * if there are not 15 addresses, go ahead and clear the filters
 10.1185 +	 */
 10.1186 +	mc_ptr = netdev->mc_list;
 10.1187 +
 10.1188 +	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
 10.1189 +		if(mc_ptr) {
 10.1190 +			e1000_rar_set(hw, mc_ptr->dmi_addr, i);
 10.1191 +			mc_ptr = mc_ptr->next;
 10.1192 +		} else {
 10.1193 +			E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
 10.1194 +			E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
 10.1195 +		}
 10.1196 +	}
 10.1197 +
 10.1198 +	/* clear the old settings from the multicast hash table */
 10.1199 +
 10.1200 +	for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
 10.1201 +		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
 10.1202 +
 10.1203 +	/* load any remaining addresses into the hash table */
 10.1204 +
 10.1205 +	for(; mc_ptr; mc_ptr = mc_ptr->next) {
 10.1206 +		hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
 10.1207 +		e1000_mta_set(hw, hash_value);
 10.1208 +	}
 10.1209 +
 10.1210 +	if(hw->mac_type == e1000_82542_rev2_0)
 10.1211 +		e1000_leave_82542_rst(adapter);
 10.1212 +}
 10.1213 +
 10.1214 +
 10.1215 +/* need to wait a few seconds after link up to get diagnostic information from the phy */
 10.1216 +
 10.1217 +static void
 10.1218 +e1000_update_phy_info(unsigned long data)
 10.1219 +{
 10.1220 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
 10.1221 +	e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
 10.1222 +}
 10.1223 +
 10.1224 +/**
 10.1225 + * e1000_watchdog - Timer Call-back
 10.1226 + * @data: pointer to netdev cast into an unsigned long
 10.1227 + **/
 10.1228 +
 10.1229 +static void
 10.1230 +e1000_watchdog(unsigned long data)
 10.1231 +{
 10.1232 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
 10.1233 +	struct net_device *netdev = adapter->netdev;
 10.1234 +	struct e1000_desc_ring *txdr = &adapter->tx_ring;
 10.1235 +	int i;
 10.1236 +
 10.1237 +	e1000_check_for_link(&adapter->hw);
 10.1238 +
 10.1239 +	if(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
 10.1240 +		if(!netif_carrier_ok(netdev)) {
 10.1241 +			e1000_get_speed_and_duplex(&adapter->hw,
 10.1242 +			                           &adapter->link_speed,
 10.1243 +			                           &adapter->link_duplex);
 10.1244 +
 10.1245 +			printk(KERN_INFO
 10.1246 +			       "e1000: %s NIC Link is Up %d Mbps %s\n",
 10.1247 +			       netdev->name, adapter->link_speed,
 10.1248 +			       adapter->link_duplex == FULL_DUPLEX ?
 10.1249 +			       "Full Duplex" : "Half Duplex");
 10.1250 +
 10.1251 +			netif_carrier_on(netdev);
 10.1252 +			netif_wake_queue(netdev);
 10.1253 +			mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
 10.1254 +		}
 10.1255 +	} else {
 10.1256 +		if(netif_carrier_ok(netdev)) {
 10.1257 +			adapter->link_speed = 0;
 10.1258 +			adapter->link_duplex = 0;
 10.1259 +			printk(KERN_INFO
 10.1260 +			       "e1000: %s NIC Link is Down\n",
 10.1261 +			       netdev->name);
 10.1262 +			netif_carrier_off(netdev);
 10.1263 +			netif_stop_queue(netdev);
 10.1264 +			mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
 10.1265 +		}
 10.1266 +	}
 10.1267 +
 10.1268 +	e1000_update_stats(adapter);
 10.1269 +	e1000_update_adaptive(&adapter->hw);
 10.1270 +
 10.1271 +
 10.1272 +	/* Cause software interrupt to ensure rx ring is cleaned */
 10.1273 +	E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
 10.1274 +
 10.1275 +	/* Early detection of hung controller */
 10.1276 +	i = txdr->next_to_clean;
 10.1277 +	if(txdr->buffer_info[i].dma &&
 10.1278 +	   time_after(jiffies, txdr->buffer_info[i].time_stamp + HZ) &&
 10.1279 +	   !(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF))
 10.1280 +		netif_stop_queue(netdev);
 10.1281 +
 10.1282 +	/* Reset the timer */
 10.1283 +	mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
 10.1284 +}
 10.1285 +
 10.1286 +#define E1000_TX_FLAGS_CSUM		0x00000001
 10.1287 +#define E1000_TX_FLAGS_VLAN		0x00000002
 10.1288 +#define E1000_TX_FLAGS_VLAN_MASK	0xffff0000
 10.1289 +#define E1000_TX_FLAGS_VLAN_SHIFT	16
 10.1290 +
 10.1291 +static inline boolean_t
 10.1292 +e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
 10.1293 +{
 10.1294 +	struct e1000_context_desc *context_desc;
 10.1295 +	int i;
 10.1296 +	uint8_t css, cso;
 10.1297 +
 10.1298 +	if(skb->ip_summed == CHECKSUM_HW) {
 10.1299 +		css = skb->h.raw - skb->data;
 10.1300 +		cso = (skb->h.raw + skb->csum) - skb->data;
 10.1301 +
 10.1302 +		i = adapter->tx_ring.next_to_use;
 10.1303 +		context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
 10.1304 +
 10.1305 +		context_desc->upper_setup.tcp_fields.tucss = css;
 10.1306 +		context_desc->upper_setup.tcp_fields.tucso = cso;
 10.1307 +		context_desc->upper_setup.tcp_fields.tucse = 0;
 10.1308 +		context_desc->tcp_seg_setup.data = 0;
 10.1309 +		context_desc->cmd_and_length =
 10.1310 +			cpu_to_le32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
 10.1311 +
 10.1312 +		i = (i + 1) % adapter->tx_ring.count;
 10.1313 +		adapter->tx_ring.next_to_use = i;
 10.1314 +
 10.1315 +		return TRUE;
 10.1316 +	}
 10.1317 +
 10.1318 +	return FALSE;
 10.1319 +}
 10.1320 +
 10.1321 +static inline int
 10.1322 +e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb)
 10.1323 +{
 10.1324 +	struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
 10.1325 +	int len, offset, size, count, i;
 10.1326 +
 10.1327 +	int f;
 10.1328 +	len = skb->len - skb->data_len;
 10.1329 +	i = (tx_ring->next_to_use + tx_ring->count - 1) % tx_ring->count;
 10.1330 +	count = 0;
 10.1331 +
 10.1332 +	offset = 0;
 10.1333 +
 10.1334 +	while(len) {
 10.1335 +		i = (i + 1) % tx_ring->count;
 10.1336 +		size = min(len, adapter->max_data_per_txd);
 10.1337 +		tx_ring->buffer_info[i].length = size;
 10.1338 +		tx_ring->buffer_info[i].dma =
 10.1339 +			pci_map_single(adapter->pdev,
 10.1340 +				skb->data + offset,
 10.1341 +				size,
 10.1342 +				PCI_DMA_TODEVICE);
 10.1343 +		tx_ring->buffer_info[i].time_stamp = jiffies;
 10.1344 +
 10.1345 +		len -= size;
 10.1346 +		offset += size;
 10.1347 +		count++;
 10.1348 +	}
 10.1349 +
 10.1350 +	for(f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
 10.1351 +		struct skb_frag_struct *frag;
 10.1352 +
 10.1353 +		frag = &skb_shinfo(skb)->frags[f];
 10.1354 +		len = frag->size;
 10.1355 +		offset = 0;
 10.1356 +
 10.1357 +		while(len) {
 10.1358 +			i = (i + 1) % tx_ring->count;
 10.1359 +			size = min(len, adapter->max_data_per_txd);
 10.1360 +			tx_ring->buffer_info[i].length = size;
 10.1361 +			tx_ring->buffer_info[i].dma =
 10.1362 +				pci_map_page(adapter->pdev,
 10.1363 +					frag->page,
 10.1364 +					frag->page_offset + offset,
 10.1365 +					size,
 10.1366 +					PCI_DMA_TODEVICE);
 10.1367 +
 10.1368 +			len -= size;
 10.1369 +			offset += size;
 10.1370 +			count++;
 10.1371 +		}
 10.1372 +	}
 10.1373 +	tx_ring->buffer_info[i].skb = skb;
 10.1374 +
 10.1375 +	return count;
 10.1376 +}
 10.1377 +
 10.1378 +static inline void
 10.1379 +e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
 10.1380 +{
 10.1381 +	struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
 10.1382 +	struct e1000_tx_desc *tx_desc = NULL;
 10.1383 +	uint32_t txd_upper, txd_lower;
 10.1384 +	int i;
 10.1385 +
 10.1386 +	txd_upper = 0;
 10.1387 +	txd_lower = adapter->txd_cmd;
 10.1388 +
 10.1389 +	if(tx_flags & E1000_TX_FLAGS_CSUM) {
 10.1390 +		txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
 10.1391 +		txd_upper |= E1000_TXD_POPTS_TXSM << 8;
 10.1392 +	}
 10.1393 +
 10.1394 +	if(tx_flags & E1000_TX_FLAGS_VLAN) {
 10.1395 +		txd_lower |= E1000_TXD_CMD_VLE;
 10.1396 +		txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
 10.1397 +	}
 10.1398 +
 10.1399 +	i = tx_ring->next_to_use;
 10.1400 +
 10.1401 +	while(count--) {
 10.1402 +		tx_desc = E1000_TX_DESC(*tx_ring, i);
 10.1403 +		tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
 10.1404 +		tx_desc->lower.data =
 10.1405 +			cpu_to_le32(txd_lower | tx_ring->buffer_info[i].length);
 10.1406 +		tx_desc->upper.data = cpu_to_le32(txd_upper);
 10.1407 +		i = (i + 1) % tx_ring->count;
 10.1408 +	}
 10.1409 +
 10.1410 +	tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP);
 10.1411 +
 10.1412 +	/* Force memory writes to complete before letting h/w
 10.1413 +	 * know there are new descriptors to fetch.  (Only
 10.1414 +	 * applicable for weak-ordered memory model archs,
 10.1415 +	 * such as IA-64). */
 10.1416 +	wmb();
 10.1417 +
 10.1418 +	tx_ring->next_to_use = i;
 10.1419 +	E1000_WRITE_REG(&adapter->hw, TDT, i);
 10.1420 +}
 10.1421 +
 10.1422 +#define TXD_USE_COUNT(S, X) (((S) / (X)) + (((S) % (X)) ? 1 : 0))
 10.1423 +
 10.1424 +static int
 10.1425 +e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
 10.1426 +{
 10.1427 +	struct e1000_adapter *adapter = netdev->priv;
 10.1428 +	int tx_flags = 0, count;
 10.1429 +	int f;
 10.1430 +
 10.1431 +	count = TXD_USE_COUNT(skb->len - skb->data_len,
 10.1432 +	                      adapter->max_data_per_txd);
 10.1433 +
 10.1434 +	if(count == 0) {
 10.1435 +		dev_kfree_skb_any(skb);
 10.1436 +		return 0;
 10.1437 +	}
 10.1438 +
 10.1439 +	for(f = 0; f < skb_shinfo(skb)->nr_frags; f++)
 10.1440 +		count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
 10.1441 +		                       adapter->max_data_per_txd);
 10.1442 +
 10.1443 +	if(skb->ip_summed == CHECKSUM_HW)
 10.1444 +		count++;
 10.1445 +
 10.1446 +	if(E1000_DESC_UNUSED(&adapter->tx_ring) < count) {
 10.1447 +		netif_stop_queue(netdev);
 10.1448 +		return 1;
 10.1449 +	}
 10.1450 +
 10.1451 +	if(e1000_tx_csum(adapter, skb))
 10.1452 +		tx_flags |= E1000_TX_FLAGS_CSUM;
 10.1453 +
 10.1454 +	if(adapter->vlgrp && vlan_tx_tag_present(skb)) {
 10.1455 +		tx_flags |= E1000_TX_FLAGS_VLAN;
 10.1456 +		tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
 10.1457 +	}
 10.1458 +
 10.1459 +	count = e1000_tx_map(adapter, skb);
 10.1460 +
 10.1461 +	e1000_tx_queue(adapter, count, tx_flags);
 10.1462 +
 10.1463 +	netdev->trans_start = jiffies;
 10.1464 +
 10.1465 +	return 0;
 10.1466 +}
 10.1467 +
 10.1468 +/**
 10.1469 + * e1000_tx_timeout - Respond to a Tx Hang
 10.1470 + * @netdev: network interface device structure
 10.1471 + **/
 10.1472 +
 10.1473 +static void
 10.1474 +e1000_tx_timeout(struct net_device *netdev)
 10.1475 +{
 10.1476 +	struct e1000_adapter *adapter = netdev->priv;
 10.1477 +
 10.1478 +	/* Do the reset outside of interrupt context */
 10.1479 +	//schedule_task(&adapter->tx_timeout_task); XXXX Not in Xen!!!
 10.1480 +	e1000_tx_timeout_task(netdev);  // XXX HACK
 10.1481 +}
 10.1482 +
 10.1483 +static void
 10.1484 +e1000_tx_timeout_task(struct net_device *netdev)
 10.1485 +{
 10.1486 +	struct e1000_adapter *adapter = netdev->priv;
 10.1487 +
 10.1488 +	netif_device_detach(netdev);
 10.1489 +	e1000_down(adapter);
 10.1490 +	e1000_up(adapter);
 10.1491 +	netif_device_attach(netdev);
 10.1492 +}
 10.1493 +
 10.1494 +/**
 10.1495 + * e1000_get_stats - Get System Network Statistics
 10.1496 + * @netdev: network interface device structure
 10.1497 + *
 10.1498 + * Returns the address of the device statistics structure.
 10.1499 + * The statistics are actually updated from the timer callback.
 10.1500 + **/
 10.1501 +
 10.1502 +static struct net_device_stats *
 10.1503 +e1000_get_stats(struct net_device *netdev)
 10.1504 +{
 10.1505 +	struct e1000_adapter *adapter = netdev->priv;
 10.1506 +
 10.1507 +	return &adapter->net_stats;
 10.1508 +}
 10.1509 +
 10.1510 +/**
 10.1511 + * e1000_change_mtu - Change the Maximum Transfer Unit
 10.1512 + * @netdev: network interface device structure
 10.1513 + * @new_mtu: new value for maximum frame size
 10.1514 + *
 10.1515 + * Returns 0 on success, negative on failure
 10.1516 + **/
 10.1517 +
 10.1518 +static int
 10.1519 +e1000_change_mtu(struct net_device *netdev, int new_mtu)
 10.1520 +{
 10.1521 +	struct e1000_adapter *adapter = netdev->priv;
 10.1522 +	int old_mtu = adapter->rx_buffer_len;
 10.1523 +	int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
 10.1524 +
 10.1525 +	if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
 10.1526 +	   (max_frame > MAX_JUMBO_FRAME_SIZE)) {
 10.1527 +		E1000_ERR("Invalid MTU setting\n");
 10.1528 +		return -EINVAL;
 10.1529 +	}
 10.1530 +
 10.1531 +	if(max_frame <= MAXIMUM_ETHERNET_FRAME_SIZE) {
 10.1532 +		adapter->rx_buffer_len = E1000_RXBUFFER_2048;
 10.1533 +
 10.1534 +	} else if(adapter->hw.mac_type < e1000_82543) {
 10.1535 +		E1000_ERR("Jumbo Frames not supported on 82542\n");
 10.1536 +		return -EINVAL;
 10.1537 +
 10.1538 +	} else if(max_frame <= E1000_RXBUFFER_4096) {
 10.1539 +		adapter->rx_buffer_len = E1000_RXBUFFER_4096;
 10.1540 +
 10.1541 +	} else if(max_frame <= E1000_RXBUFFER_8192) {
 10.1542 +		adapter->rx_buffer_len = E1000_RXBUFFER_8192;
 10.1543 +
 10.1544 +	} else {
 10.1545 +		adapter->rx_buffer_len = E1000_RXBUFFER_16384;
 10.1546 +	}
 10.1547 +
 10.1548 +	if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) {
 10.1549 +
 10.1550 +		e1000_down(adapter);
 10.1551 +		e1000_up(adapter);
 10.1552 +	}
 10.1553 +
 10.1554 +	netdev->mtu = new_mtu;
 10.1555 +	adapter->hw.max_frame_size = max_frame;
 10.1556 +
 10.1557 +	return 0;
 10.1558 +}
 10.1559 +
 10.1560 +/**
 10.1561 + * e1000_update_stats - Update the board statistics counters
 10.1562 + * @adapter: board private structure
 10.1563 + **/
 10.1564 +
 10.1565 +static void
 10.1566 +e1000_update_stats(struct e1000_adapter *adapter)
 10.1567 +{
 10.1568 +	struct e1000_hw *hw = &adapter->hw;
 10.1569 +	unsigned long flags;
 10.1570 +	uint16_t phy_tmp;
 10.1571 +
 10.1572 +#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
 10.1573 +
 10.1574 +	spin_lock_irqsave(&adapter->stats_lock, flags);
 10.1575 +
 10.1576 +	/* these counters are modified from e1000_adjust_tbi_stats,
 10.1577 +	 * called from the interrupt context, so they must only
 10.1578 +	 * be written while holding adapter->stats_lock
 10.1579 +	 */
 10.1580 +
 10.1581 +	adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
 10.1582 +	adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
 10.1583 +	adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
 10.1584 +	adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
 10.1585 +	adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
 10.1586 +	adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
 10.1587 +	adapter->stats.roc += E1000_READ_REG(hw, ROC);
 10.1588 +	adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
 10.1589 +	adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
 10.1590 +	adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
 10.1591 +	adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
 10.1592 +	adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
 10.1593 +	adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
 10.1594 +
 10.1595 +	spin_unlock_irqrestore(&adapter->stats_lock, flags);
 10.1596 +
 10.1597 +	/* the rest of the counters are only modified here */
 10.1598 +
 10.1599 +	adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
 10.1600 +	adapter->stats.mpc += E1000_READ_REG(hw, MPC);
 10.1601 +	adapter->stats.scc += E1000_READ_REG(hw, SCC);
 10.1602 +	adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
 10.1603 +	adapter->stats.mcc += E1000_READ_REG(hw, MCC);
 10.1604 +	adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
 10.1605 +	adapter->stats.dc += E1000_READ_REG(hw, DC);
 10.1606 +	adapter->stats.sec += E1000_READ_REG(hw, SEC);
 10.1607 +	adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
 10.1608 +	adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
 10.1609 +	adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
 10.1610 +	adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
 10.1611 +	adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
 10.1612 +	adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
 10.1613 +	adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
 10.1614 +	adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
 10.1615 +	adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
 10.1616 +	adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
 10.1617 +	adapter->stats.ruc += E1000_READ_REG(hw, RUC);
 10.1618 +	adapter->stats.rfc += E1000_READ_REG(hw, RFC);
 10.1619 +	adapter->stats.rjc += E1000_READ_REG(hw, RJC);
 10.1620 +	adapter->stats.torl += E1000_READ_REG(hw, TORL);
 10.1621 +	adapter->stats.torh += E1000_READ_REG(hw, TORH);
 10.1622 +	adapter->stats.totl += E1000_READ_REG(hw, TOTL);
 10.1623 +	adapter->stats.toth += E1000_READ_REG(hw, TOTH);
 10.1624 +	adapter->stats.tpr += E1000_READ_REG(hw, TPR);
 10.1625 +	adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
 10.1626 +	adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
 10.1627 +	adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
 10.1628 +	adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
 10.1629 +	adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
 10.1630 +	adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
 10.1631 +	adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
 10.1632 +	adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
 10.1633 +
 10.1634 +	/* used for adaptive IFS */
 10.1635 +
 10.1636 +	hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
 10.1637 +	adapter->stats.tpt += hw->tx_packet_delta;
 10.1638 +	hw->collision_delta = E1000_READ_REG(hw, COLC);
 10.1639 +	adapter->stats.colc += hw->collision_delta;
 10.1640 +
 10.1641 +	if(hw->mac_type >= e1000_82543) {
 10.1642 +		adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
 10.1643 +		adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
 10.1644 +		adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
 10.1645 +		adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
 10.1646 +		adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
 10.1647 +		adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
 10.1648 +	}
 10.1649 +
 10.1650 +	/* Fill out the OS statistics structure */
 10.1651 +
 10.1652 +	adapter->net_stats.rx_packets = adapter->stats.gprc;
 10.1653 +	adapter->net_stats.tx_packets = adapter->stats.gptc;
 10.1654 +	adapter->net_stats.rx_bytes = adapter->stats.gorcl;
 10.1655 +	adapter->net_stats.tx_bytes = adapter->stats.gotcl;
 10.1656 +	adapter->net_stats.multicast = adapter->stats.mprc;
 10.1657 +	adapter->net_stats.collisions = adapter->stats.colc;
 10.1658 +
 10.1659 +	/* Rx Errors */
 10.1660 +
 10.1661 +	adapter->net_stats.rx_errors = adapter->stats.rxerrc +
 10.1662 +		adapter->stats.crcerrs + adapter->stats.algnerrc +
 10.1663 +		adapter->stats.rlec + adapter->stats.rnbc +
 10.1664 +		adapter->stats.mpc + adapter->stats.cexterr;
 10.1665 +	adapter->net_stats.rx_dropped = adapter->stats.rnbc;
 10.1666 +	adapter->net_stats.rx_length_errors = adapter->stats.rlec;
 10.1667 +	adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
 10.1668 +	adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
 10.1669 +	adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
 10.1670 +	adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
 10.1671 +
 10.1672 +	/* Tx Errors */
 10.1673 +
 10.1674 +	adapter->net_stats.tx_errors = adapter->stats.ecol +
 10.1675 +	                               adapter->stats.latecol;
 10.1676 +	adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
 10.1677 +	adapter->net_stats.tx_window_errors = adapter->stats.latecol;
 10.1678 +	adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
 10.1679 +
 10.1680 +	/* Tx Dropped needs to be maintained elsewhere */
 10.1681 +
 10.1682 +	/* Phy Stats */
 10.1683 +
 10.1684 +	if(hw->media_type == e1000_media_type_copper) {
 10.1685 +		if((adapter->link_speed == SPEED_1000) &&
 10.1686 +		   (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
 10.1687 +			phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
 10.1688 +			adapter->phy_stats.idle_errors += phy_tmp;
 10.1689 +		}
 10.1690 +
 10.1691 +		if((hw->mac_type <= e1000_82546) &&
 10.1692 +		   !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
 10.1693 +			adapter->phy_stats.receive_errors += phy_tmp;
 10.1694 +	}
 10.1695 +}
 10.1696 +
 10.1697 +/**
 10.1698 + * e1000_irq_disable - Mask off interrupt generation on the NIC
 10.1699 + * @adapter: board private structure
 10.1700 + **/
 10.1701 +
 10.1702 +static inline void
 10.1703 +e1000_irq_disable(struct e1000_adapter *adapter)
 10.1704 +{
 10.1705 +	atomic_inc(&adapter->irq_sem);
 10.1706 +	E1000_WRITE_REG(&adapter->hw, IMC, ~0);
 10.1707 +	E1000_WRITE_FLUSH(&adapter->hw);
 10.1708 +	synchronize_irq();
 10.1709 +}
 10.1710 +
 10.1711 +/**
 10.1712 + * e1000_irq_enable - Enable default interrupt generation settings
 10.1713 + * @adapter: board private structure
 10.1714 + **/
 10.1715 +
 10.1716 +static inline void
 10.1717 +e1000_irq_enable(struct e1000_adapter *adapter)
 10.1718 +{
 10.1719 +	if(atomic_dec_and_test(&adapter->irq_sem)) {
 10.1720 +		E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
 10.1721 +		E1000_WRITE_FLUSH(&adapter->hw);
 10.1722 +	}
 10.1723 +}
 10.1724 +
 10.1725 +/**
 10.1726 + * e1000_intr - Interrupt Handler
 10.1727 + * @irq: interrupt number
 10.1728 + * @data: pointer to a network interface device structure
 10.1729 + * @pt_regs: CPU registers structure
 10.1730 + **/
 10.1731 +
 10.1732 +static void
 10.1733 +e1000_intr(int irq, void *data, struct pt_regs *regs)
 10.1734 +{
 10.1735 +	struct net_device *netdev = data;
 10.1736 +	struct e1000_adapter *adapter = netdev->priv;
 10.1737 +	uint32_t icr;
 10.1738 +	int i = E1000_MAX_INTR;
 10.1739 +
 10.1740 +	while(i && (icr = E1000_READ_REG(&adapter->hw, ICR))) {
 10.1741 +
 10.1742 +		if(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
 10.1743 +			adapter->hw.get_link_status = 1;
 10.1744 +			mod_timer(&adapter->watchdog_timer, jiffies);
 10.1745 +		}
 10.1746 +
 10.1747 +		e1000_clean_rx_irq(adapter);
 10.1748 +		e1000_clean_tx_irq(adapter);
 10.1749 +		i--;
 10.1750 +
 10.1751 +	}
 10.1752 +}
 10.1753 +
 10.1754 +/**
 10.1755 + * e1000_clean_tx_irq - Reclaim resources after transmit completes
 10.1756 + * @adapter: board private structure
 10.1757 + **/
 10.1758 +
 10.1759 +static void
 10.1760 +e1000_clean_tx_irq(struct e1000_adapter *adapter)
 10.1761 +{
 10.1762 +	struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
 10.1763 +	struct net_device *netdev = adapter->netdev;
 10.1764 +	struct pci_dev *pdev = adapter->pdev;
 10.1765 +	struct e1000_tx_desc *tx_desc;
 10.1766 +	int i;
 10.1767 +
 10.1768 +	i = tx_ring->next_to_clean;
 10.1769 +	tx_desc = E1000_TX_DESC(*tx_ring, i);
 10.1770 +
 10.1771 +	while(tx_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
 10.1772 +
 10.1773 +		if(tx_ring->buffer_info[i].dma) {
 10.1774 +
 10.1775 +			pci_unmap_page(pdev,
 10.1776 +			               tx_ring->buffer_info[i].dma,
 10.1777 +			               tx_ring->buffer_info[i].length,
 10.1778 +			               PCI_DMA_TODEVICE);
 10.1779 +
 10.1780 +			tx_ring->buffer_info[i].dma = 0;
 10.1781 +		}
 10.1782 +
 10.1783 +		if(tx_ring->buffer_info[i].skb) {
 10.1784 +
 10.1785 +			dev_kfree_skb_any(tx_ring->buffer_info[i].skb);
 10.1786 +
 10.1787 +			tx_ring->buffer_info[i].skb = NULL;
 10.1788 +		}
 10.1789 +
 10.1790 +		tx_desc->upper.data = 0;
 10.1791 +
 10.1792 +		i = (i + 1) % tx_ring->count;
 10.1793 +		tx_desc = E1000_TX_DESC(*tx_ring, i);
 10.1794 +	}
 10.1795 +
 10.1796 +	tx_ring->next_to_clean = i;
 10.1797 +
 10.1798 +	if(netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
 10.1799 +	   (E1000_DESC_UNUSED(tx_ring) > E1000_TX_QUEUE_WAKE)) {
 10.1800 +
 10.1801 +		netif_wake_queue(netdev);
 10.1802 +	}
 10.1803 +}
 10.1804 +
 10.1805 +/**
 10.1806 + * e1000_clean_rx_irq - Send received data up the network stack,
 10.1807 + * @adapter: board private structure
 10.1808 + **/
 10.1809 +
 10.1810 +static void
 10.1811 +e1000_clean_rx_irq(struct e1000_adapter *adapter)
 10.1812 +{
 10.1813 +	struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
 10.1814 +	struct net_device *netdev = adapter->netdev;
 10.1815 +	struct pci_dev *pdev = adapter->pdev;
 10.1816 +	struct e1000_rx_desc *rx_desc;
 10.1817 +	struct sk_buff *skb;
 10.1818 +	unsigned long flags;
 10.1819 +	uint32_t length;
 10.1820 +	uint8_t last_byte;
 10.1821 +	int i;
 10.1822 +
 10.1823 +	i = rx_ring->next_to_clean;
 10.1824 +	rx_desc = E1000_RX_DESC(*rx_ring, i);
 10.1825 +
 10.1826 +	while(rx_desc->status & E1000_RXD_STAT_DD) {
 10.1827 +
 10.1828 +		pci_unmap_single(pdev,
 10.1829 +		                 rx_ring->buffer_info[i].dma,
 10.1830 +		                 rx_ring->buffer_info[i].length,
 10.1831 +		                 PCI_DMA_FROMDEVICE);
 10.1832 +
 10.1833 +		skb = rx_ring->buffer_info[i].skb;
 10.1834 +		length = le16_to_cpu(rx_desc->length);
 10.1835 +
 10.1836 +		if(!(rx_desc->status & E1000_RXD_STAT_EOP)) {
 10.1837 +
 10.1838 +			/* All receives must fit into a single buffer */
 10.1839 +
 10.1840 +			E1000_DBG("Receive packet consumed multiple buffers\n");
 10.1841 +
 10.1842 +			dev_kfree_skb_irq(skb);
 10.1843 +			rx_desc->status = 0;
 10.1844 +			rx_ring->buffer_info[i].skb = NULL;
 10.1845 +
 10.1846 +			i = (i + 1) % rx_ring->count;
 10.1847 +
 10.1848 +			rx_desc = E1000_RX_DESC(*rx_ring, i);
 10.1849 +			continue;
 10.1850 +		}
 10.1851 +
 10.1852 +		if(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
 10.1853 +
 10.1854 +			last_byte = *(skb->data + length - 1);
 10.1855 +
 10.1856 +			if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
 10.1857 +			              rx_desc->errors, length, last_byte)) {
 10.1858 +
 10.1859 +				spin_lock_irqsave(&adapter->stats_lock, flags);
 10.1860 +
 10.1861 +				e1000_tbi_adjust_stats(&adapter->hw,
 10.1862 +				                       &adapter->stats,
 10.1863 +				                       length, skb->data);
 10.1864 +
 10.1865 +				spin_unlock_irqrestore(&adapter->stats_lock,
 10.1866 +				                       flags);
 10.1867 +				length--;
 10.1868 +			} else {
 10.1869 +
 10.1870 +				dev_kfree_skb_irq(skb);
 10.1871 +				rx_desc->status = 0;
 10.1872 +				rx_ring->buffer_info[i].skb = NULL;
 10.1873 +
 10.1874 +				i = (i + 1) % rx_ring->count;
 10.1875 +
 10.1876 +				rx_desc = E1000_RX_DESC(*rx_ring, i);
 10.1877 +				continue;
 10.1878 +			}
 10.1879 +		}
 10.1880 +
 10.1881 +		/* Good Receive */
 10.1882 +		skb_put(skb, length - ETHERNET_FCS_SIZE);
 10.1883 +
 10.1884 +		/* Receive Checksum Offload */
 10.1885 +		e1000_rx_checksum(adapter, rx_desc, skb);
 10.1886 +
 10.1887 +		skb->protocol = eth_type_trans(skb, netdev);
 10.1888 +		if(adapter->vlgrp && (rx_desc->status & E1000_RXD_STAT_VP)) {
 10.1889 +			vlan_hwaccel_rx(skb, adapter->vlgrp,
 10.1890 +				(rx_desc->special & E1000_RXD_SPC_VLAN_MASK));
 10.1891 +		} else {
 10.1892 +			netif_rx(skb);
 10.1893 +		}
 10.1894 +		netdev->last_rx = jiffies;
 10.1895 +
 10.1896 +		rx_desc->status = 0;
 10.1897 +		rx_ring->buffer_info[i].skb = NULL;
 10.1898 +
 10.1899 +		i = (i + 1) % rx_ring->count;
 10.1900 +
 10.1901 +		rx_desc = E1000_RX_DESC(*rx_ring, i);
 10.1902 +	}
 10.1903 +
 10.1904 +	rx_ring->next_to_clean = i;
 10.1905 +
 10.1906 +	e1000_alloc_rx_buffers(adapter);
 10.1907 +}
 10.1908 +
 10.1909 +/**
 10.1910 + * e1000_alloc_rx_buffers - Replace used receive buffers
 10.1911 + * @data: address of board private structure
 10.1912 + **/
 10.1913 +
 10.1914 +static void
 10.1915 +e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
 10.1916 +{
 10.1917 +	struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
 10.1918 +	struct net_device *netdev = adapter->netdev;
 10.1919 +	struct pci_dev *pdev = adapter->pdev;
 10.1920 +	struct e1000_rx_desc *rx_desc;
 10.1921 +	struct sk_buff *skb;
 10.1922 +	int reserve_len;
 10.1923 +	int i;
 10.1924 +
 10.1925 +	reserve_len = 2;
 10.1926 +
 10.1927 +	i = rx_ring->next_to_use;
 10.1928 +
 10.1929 +	while(!rx_ring->buffer_info[i].skb) {
 10.1930 +		rx_desc = E1000_RX_DESC(*rx_ring, i);
 10.1931 +
 10.1932 +		skb = dev_alloc_skb(adapter->rx_buffer_len + reserve_len);
 10.1933 +
 10.1934 +		if(!skb) {
 10.1935 +			/* Better luck next round */
 10.1936 +			break;
 10.1937 +		}
 10.1938 +
 10.1939 +		/* Make buffer alignment 2 beyond a 16 byte boundary
 10.1940 +		 * this will result in a 16 byte aligned IP header after
 10.1941 +		 * the 14 byte MAC header is removed
 10.1942 +		 */
 10.1943 +		skb_reserve(skb, reserve_len);
 10.1944 +
 10.1945 +		skb->dev = netdev;
 10.1946 +
 10.1947 +		rx_ring->buffer_info[i].skb = skb;
 10.1948 +		rx_ring->buffer_info[i].length = adapter->rx_buffer_len;
 10.1949 +		rx_ring->buffer_info[i].dma =
 10.1950 +			pci_map_single(pdev,
 10.1951 +			               skb->data,
 10.1952 +			               adapter->rx_buffer_len,
 10.1953 +			               PCI_DMA_FROMDEVICE);
 10.1954 +
 10.1955 +		rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
 10.1956 +
 10.1957 +		if(!(i % E1000_RX_BUFFER_WRITE)) {
 10.1958 +			/* Force memory writes to complete before letting h/w
 10.1959 +			 * know there are new descriptors to fetch.  (Only
 10.1960 +			 * applicable for weak-ordered memory model archs,
 10.1961 +			 * such as IA-64). */
 10.1962 +			wmb();
 10.1963 +
 10.1964 +			E1000_WRITE_REG(&adapter->hw, RDT, i);
 10.1965 +		}
 10.1966 +
 10.1967 +		i = (i + 1) % rx_ring->count;
 10.1968 +	}
 10.1969 +
 10.1970 +	rx_ring->next_to_use = i;
 10.1971 +}
 10.1972 +
 10.1973 +/**
 10.1974 + * e1000_ioctl -
 10.1975 + * @netdev:
 10.1976 + * @ifreq:
 10.1977 + * @cmd:
 10.1978 + **/
 10.1979 +
 10.1980 +static int
 10.1981 +e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 10.1982 +{
 10.1983 +	switch (cmd) {
 10.1984 +	case SIOCETHTOOL:
 10.1985 +		return e1000_ethtool_ioctl(netdev, ifr);
 10.1986 +	default:
 10.1987 +		return -EOPNOTSUPP;
 10.1988 +	}
 10.1989 +}
 10.1990 +
 10.1991 +/**
 10.1992 + * e1000_rx_checksum - Receive Checksum Offload for 82543
 10.1993 + * @adapter: board private structure
 10.1994 + * @rx_desc: receive descriptor
 10.1995 + * @sk_buff: socket buffer with received data
 10.1996 + **/
 10.1997 +
 10.1998 +static inline void
 10.1999 +e1000_rx_checksum(struct e1000_adapter *adapter,
 10.2000 +                  struct e1000_rx_desc *rx_desc,
 10.2001 +                  struct sk_buff *skb)
 10.2002 +{
 10.2003 +	/* 82543 or newer only */
 10.2004 +	if((adapter->hw.mac_type < e1000_82543) ||
 10.2005 +	/* Ignore Checksum bit is set */
 10.2006 +	(rx_desc->status & E1000_RXD_STAT_IXSM) ||
 10.2007 +	/* TCP Checksum has not been calculated */
 10.2008 +	(!(rx_desc->status & E1000_RXD_STAT_TCPCS))) {
 10.2009 +		skb->ip_summed = CHECKSUM_NONE;
 10.2010 +		return;
 10.2011 +	}
 10.2012 +
 10.2013 +	/* At this point we know the hardware did the TCP checksum */
 10.2014 +	/* now look at the TCP checksum error bit */
 10.2015 +	if(rx_desc->errors & E1000_RXD_ERR_TCPE) {
 10.2016 +		/* let the stack verify checksum errors */
 10.2017 +		skb->ip_summed = CHECKSUM_NONE;
 10.2018 +		adapter->hw_csum_err++;
 10.2019 +	} else {
 10.2020 +	/* TCP checksum is good */
 10.2021 +		skb->ip_summed = CHECKSUM_UNNECESSARY;
 10.2022 +		adapter->hw_csum_good++;
 10.2023 +	}
 10.2024 +}
 10.2025 +
 10.2026 +void
 10.2027 +e1000_pci_set_mwi(struct e1000_hw *hw)
 10.2028 +{
 10.2029 +	struct e1000_adapter *adapter = hw->back;
 10.2030 +
 10.2031 +	pci_set_mwi(adapter->pdev);
 10.2032 +}
 10.2033 +
 10.2034 +void
 10.2035 +e1000_pci_clear_mwi(struct e1000_hw *hw)
 10.2036 +{
 10.2037 +	struct e1000_adapter *adapter = hw->back;
 10.2038 +
 10.2039 +	pci_clear_mwi(adapter->pdev);
 10.2040 +}
 10.2041 +
 10.2042 +void
 10.2043 +e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
 10.2044 +{
 10.2045 +	struct e1000_adapter *adapter = hw->back;
 10.2046 +
 10.2047 +	pci_read_config_word(adapter->pdev, reg, value);
 10.2048 +}
 10.2049 +
 10.2050 +void
 10.2051 +e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
 10.2052 +{
 10.2053 +	struct e1000_adapter *adapter = hw->back;
 10.2054 +
 10.2055 +	pci_write_config_word(adapter->pdev, reg, *value);
 10.2056 +}
 10.2057 +
 10.2058 +uint32_t
 10.2059 +e1000_io_read(struct e1000_hw *hw, uint32_t port)
 10.2060 +{
 10.2061 +	return inl(port);
 10.2062 +}
 10.2063 +
 10.2064 +void
 10.2065 +e1000_io_write(struct e1000_hw *hw, uint32_t port, uint32_t value)
 10.2066 +{
 10.2067 +	outl(value, port);
 10.2068 +}
 10.2069 +
 10.2070 +static void
 10.2071 +e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
 10.2072 +{
 10.2073 +	struct e1000_adapter *adapter = netdev->priv;
 10.2074 +	uint32_t ctrl, rctl;
 10.2075 +
 10.2076 +	e1000_irq_disable(adapter);
 10.2077 +	adapter->vlgrp = grp;
 10.2078 +
 10.2079 +	if(grp) {
 10.2080 +		/* enable VLAN tag insert/strip */
 10.2081 +
 10.2082 +		E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
 10.2083 +
 10.2084 +		ctrl = E1000_READ_REG(&adapter->hw, CTRL);
 10.2085 +		ctrl |= E1000_CTRL_VME;
 10.2086 +		E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
 10.2087 +
 10.2088 +		/* enable VLAN receive filtering */
 10.2089 +
 10.2090 +		rctl = E1000_READ_REG(&adapter->hw, RCTL);
 10.2091 +		rctl |= E1000_RCTL_VFE;
 10.2092 +		rctl &= ~E1000_RCTL_CFIEN;
 10.2093 +		E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 10.2094 +	} else {
 10.2095 +		/* disable VLAN tag insert/strip */
 10.2096 +
 10.2097 +		ctrl = E1000_READ_REG(&adapter->hw, CTRL);
 10.2098 +		ctrl &= ~E1000_CTRL_VME;
 10.2099 +		E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
 10.2100 +
 10.2101 +		/* disable VLAN filtering */
 10.2102 +
 10.2103 +		rctl = E1000_READ_REG(&adapter->hw, RCTL);
 10.2104 +		rctl &= ~E1000_RCTL_VFE;
 10.2105 +		E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 10.2106 +	}
 10.2107 +
 10.2108 +	e1000_irq_enable(adapter);
 10.2109 +}
 10.2110 +
 10.2111 +static void
 10.2112 +e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
 10.2113 +{
 10.2114 +	struct e1000_adapter *adapter = netdev->priv;
 10.2115 +	uint32_t vfta, index;
 10.2116 +
 10.2117 +	/* add VID to filter table */
 10.2118 +
 10.2119 +	index = (vid >> 5) & 0x7F;
 10.2120 +	vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
 10.2121 +	vfta |= (1 << (vid & 0x1F));
 10.2122 +	e1000_write_vfta(&adapter->hw, index, vfta);
 10.2123 +}
 10.2124 +
 10.2125 +static void
 10.2126 +e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
 10.2127 +{
 10.2128 +	struct e1000_adapter *adapter = netdev->priv;
 10.2129 +	uint32_t vfta, index;
 10.2130 +
 10.2131 +	e1000_irq_disable(adapter);
 10.2132 +
 10.2133 +	if(adapter->vlgrp)
 10.2134 +		adapter->vlgrp->vlan_devices[vid] = NULL;
 10.2135 +
 10.2136 +	e1000_irq_enable(adapter);
 10.2137 +
 10.2138 +	/* remove VID from filter table*/
 10.2139 +
 10.2140 +	index = (vid >> 5) & 0x7F;
 10.2141 +	vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
 10.2142 +	vfta &= ~(1 << (vid & 0x1F));
 10.2143 +	e1000_write_vfta(&adapter->hw, index, vfta);
 10.2144 +}
 10.2145 +
 10.2146 +static void
 10.2147 +e1000_restore_vlan(struct e1000_adapter *adapter)
 10.2148 +{
 10.2149 +	e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
 10.2150 +
 10.2151 +	if(adapter->vlgrp) {
 10.2152 +		uint16_t vid;
 10.2153 +		for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
 10.2154 +			if(!adapter->vlgrp->vlan_devices[vid])
 10.2155 +				continue;
 10.2156 +			e1000_vlan_rx_add_vid(adapter->netdev, vid);
 10.2157 +		}
 10.2158 +	}
 10.2159 +}
 10.2160 +
 10.2161 +static int
 10.2162 +e1000_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
 10.2163 +{
 10.2164 +	struct pci_dev *pdev = NULL;
 10.2165 +
 10.2166 +	switch(event) {
 10.2167 +	case SYS_DOWN:
 10.2168 +	case SYS_HALT:
 10.2169 +	case SYS_POWER_OFF:
 10.2170 +		pci_for_each_dev(pdev) {
 10.2171 +			if(pci_dev_driver(pdev) == &e1000_driver)
 10.2172 +				e1000_suspend(pdev, 3);
 10.2173 +		}
 10.2174 +	}
 10.2175 +	return NOTIFY_DONE;
 10.2176 +}
 10.2177 +
 10.2178 +static int
 10.2179 +e1000_suspend(struct pci_dev *pdev, uint32_t state)
 10.2180 +{
 10.2181 +	struct net_device *netdev = pci_get_drvdata(pdev);
 10.2182 +	struct e1000_adapter *adapter = netdev->priv;
 10.2183 +	uint32_t ctrl, ctrl_ext, rctl, manc, status;
 10.2184 +	uint32_t wufc = adapter->wol;
 10.2185 +
 10.2186 +	netif_device_detach(netdev);
 10.2187 +
 10.2188 +	if(netif_running(netdev))
 10.2189 +		e1000_down(adapter);
 10.2190 +
 10.2191 +	status = E1000_READ_REG(&adapter->hw, STATUS);
 10.2192 +	if(status & E1000_STATUS_LU)
 10.2193 +		wufc &= ~E1000_WUFC_LNKC;
 10.2194 +
 10.2195 +	if(wufc) {
 10.2196 +		e1000_setup_rctl(adapter);
 10.2197 +		e1000_set_multi(netdev);
 10.2198 +
 10.2199 +		/* turn on all-multi mode if wake on multicast is enabled */
 10.2200 +		if(adapter->wol & E1000_WUFC_MC) {
 10.2201 +			rctl = E1000_READ_REG(&adapter->hw, RCTL);
 10.2202 +			rctl |= E1000_RCTL_MPE;
 10.2203 +			E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 10.2204 +		}
 10.2205 +
 10.2206 +		if(adapter->hw.mac_type >= e1000_82540) {
 10.2207 +			ctrl = E1000_READ_REG(&adapter->hw, CTRL);
 10.2208 +			/* advertise wake from D3Cold */
 10.2209 +			#define E1000_CTRL_ADVD3WUC 0x00100000
 10.2210 +			/* phy power management enable */
 10.2211 +			#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
 10.2212 +			ctrl |= E1000_CTRL_ADVD3WUC |
 10.2213 +				E1000_CTRL_EN_PHY_PWR_MGMT;
 10.2214 +			E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
 10.2215 +		}
 10.2216 +
 10.2217 +		if(adapter->hw.media_type == e1000_media_type_fiber) {
 10.2218 +			/* keep the laser running in D3 */
 10.2219 +			ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
 10.2220 +			ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
 10.2221 +			E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
 10.2222 +		}
 10.2223 +
 10.2224 +		E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
 10.2225 +		E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
 10.2226 +		pci_enable_wake(pdev, 3, 1);
 10.2227 +		pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
 10.2228 +	} else {
 10.2229 +		E1000_WRITE_REG(&adapter->hw, WUC, 0);
 10.2230 +		E1000_WRITE_REG(&adapter->hw, WUFC, 0);
 10.2231 +		pci_enable_wake(pdev, 3, 0);
 10.2232 +		pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
 10.2233 +	}
 10.2234 +
 10.2235 +	pci_save_state(pdev, adapter->pci_state);
 10.2236 +
 10.2237 +	if(adapter->hw.mac_type >= e1000_82540) {
 10.2238 +		manc = E1000_READ_REG(&adapter->hw, MANC);
 10.2239 +		if(manc & E1000_MANC_SMBUS_EN) {
 10.2240 +			manc |= E1000_MANC_ARP_EN;
 10.2241 +			E1000_WRITE_REG(&adapter->hw, MANC, manc);
 10.2242 +			state = 0;
 10.2243 +		}
 10.2244 +	}
 10.2245 +
 10.2246 +	state = (state > 0) ? 3 : 0;
 10.2247 +	pci_set_power_state(pdev, state);
 10.2248 +
 10.2249 +	return 0;
 10.2250 +}
 10.2251 +
 10.2252 +#ifdef CONFIG_PM
 10.2253 +static int
 10.2254 +e1000_resume(struct pci_dev *pdev)
 10.2255 +{
 10.2256 +	struct net_device *netdev = pci_get_drvdata(pdev);
 10.2257 +	struct e1000_adapter *adapter = netdev->priv;
 10.2258 +	uint32_t manc;
 10.2259 +
 10.2260 +	pci_set_power_state(pdev, 0);
 10.2261 +	pci_restore_state(pdev, adapter->pci_state);
 10.2262 +
 10.2263 +	pci_enable_wake(pdev, 3, 0);
 10.2264 +	pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
 10.2265 +
 10.2266 +	e1000_reset(adapter);
 10.2267 +	E1000_WRITE_REG(&adapter->hw, WUS, ~0);
 10.2268 +
 10.2269 +	if(netif_running(netdev))
 10.2270 +		e1000_up(adapter);
 10.2271 +
 10.2272 +	netif_device_attach(netdev);
 10.2273 +
 10.2274 +	if(adapter->hw.mac_type >= e1000_82540) {
 10.2275 +		manc = E1000_READ_REG(&adapter->hw, MANC);
 10.2276 +		manc &= ~(E1000_MANC_ARP_EN);
 10.2277 +		E1000_WRITE_REG(&adapter->hw, MANC, manc);
 10.2278 +	}
 10.2279 +
 10.2280 +	return 0;
 10.2281 +}
 10.2282 +#endif
 10.2283 +
 10.2284 +/* e1000_main.c */
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_osdep.h	Sat Feb 08 17:39:26 2003 +0000
    11.3 @@ -0,0 +1,114 @@
    11.4 +/*******************************************************************************
    11.5 +
    11.6 +  
    11.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    11.8 +  
    11.9 +  This program is free software; you can redistribute it and/or modify it 
   11.10 +  under the terms of the GNU General Public License as published by the Free 
   11.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   11.12 +  any later version.
   11.13 +  
   11.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   11.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   11.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   11.17 +  more details.
   11.18 +  
   11.19 +  You should have received a copy of the GNU General Public License along with
   11.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   11.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   11.22 +  
   11.23 +  The full GNU General Public License is included in this distribution in the
   11.24 +  file called LICENSE.
   11.25 +  
   11.26 +  Contact Information:
   11.27 +  Linux NICS <linux.nics@intel.com>
   11.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   11.29 +
   11.30 +*******************************************************************************/
   11.31 +
   11.32 +
   11.33 +/* glue for the OS independant part of e1000
   11.34 + * includes register access macros
   11.35 + */
   11.36 +
   11.37 +#ifndef _E1000_OSDEP_H_
   11.38 +#define _E1000_OSDEP_H_
   11.39 +
   11.40 +#include <linux/types.h>
   11.41 +#include <linux/pci.h>
   11.42 +#include <linux/delay.h>
   11.43 +#include <asm/io.h>
   11.44 +#include <linux/interrupt.h>
   11.45 +#include <linux/sched.h>
   11.46 +
   11.47 +#ifndef msec_delay
   11.48 +#define msec_delay(x) {\
   11.49 + 	int s=jiffies+1+((x*HZ)/1000); \
   11.50 +	printk("mdelay(%d) called -- spin\n",x); \
   11.51 +	while(jiffies<s); printk("mdelay over\n");}
   11.52 +
   11.53 +#if 0
   11.54 +/********************  NOT in XEN ! *******/
   11.55 +#define XXXXmsec_delay(x)	do { if(in_interrupt()) { \
   11.56 +				/* Don't mdelay in interrupt context! */ \
   11.57 +	                	BUG(); \
   11.58 +			} else { \
   11.59 +				set_current_state(TASK_UNINTERRUPTIBLE); \
   11.60 +				schedule_timeout((x * HZ)/1000); \
   11.61 +			} } while(0)
   11.62 +#endif
   11.63 +
   11.64 +#else
   11.65 +#error "msec already defined!"
   11.66 +#endif
   11.67 +
   11.68 +#define PCI_COMMAND_REGISTER   PCI_COMMAND
   11.69 +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
   11.70 +
   11.71 +typedef enum {
   11.72 +    FALSE = 0,
   11.73 +    TRUE = 1
   11.74 +} boolean_t;
   11.75 +
   11.76 +#define ASSERT(x)	if(!(x)) BUG()
   11.77 +#define MSGOUT(S, A, B)	printk(KERN_DEBUG S "\n", A, B)
   11.78 +
   11.79 +#define DBG 1
   11.80 +
   11.81 +#if DBG
   11.82 +#define DEBUGOUT(S)		printk(KERN_DEBUG S "\n")
   11.83 +#define DEBUGOUT1(S, A...)	printk(KERN_DEBUG S "\n", A)
   11.84 +#else
   11.85 +#define DEBUGOUT(S)
   11.86 +#define DEBUGOUT1(S, A...)
   11.87 +#endif
   11.88 +
   11.89 +#define DEBUGFUNC(F) DEBUGOUT(F)
   11.90 +#define DEBUGOUT2 DEBUGOUT1
   11.91 +#define DEBUGOUT3 DEBUGOUT2
   11.92 +#define DEBUGOUT7 DEBUGOUT3
   11.93 +
   11.94 +
   11.95 +#define E1000_WRITE_REG(a, reg, value) ( \
   11.96 +    ((a)->mac_type >= e1000_82543) ? \
   11.97 +        (writel((value), ((a)->hw_addr + E1000_##reg))) : \
   11.98 +        (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
   11.99 +
  11.100 +#define E1000_READ_REG(a, reg) ( \
  11.101 +    ((a)->mac_type >= e1000_82543) ? \
  11.102 +        readl((a)->hw_addr + E1000_##reg) : \
  11.103 +        readl((a)->hw_addr + E1000_82542_##reg))
  11.104 +
  11.105 +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
  11.106 +    ((a)->mac_type >= e1000_82543) ? \
  11.107 +        writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
  11.108 +        writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
  11.109 +
  11.110 +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
  11.111 +    ((a)->mac_type >= e1000_82543) ? \
  11.112 +        readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
  11.113 +        readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
  11.114 +
  11.115 +#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
  11.116 +
  11.117 +#endif /* _E1000_OSDEP_H_ */
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_param.c	Sat Feb 08 17:39:26 2003 +0000
    12.3 @@ -0,0 +1,655 @@
    12.4 +/*******************************************************************************
    12.5 +
    12.6 +  
    12.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    12.8 +  
    12.9 +  This program is free software; you can redistribute it and/or modify it 
   12.10 +  under the terms of the GNU General Public License as published by the Free 
   12.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   12.12 +  any later version.
   12.13 +  
   12.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   12.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   12.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   12.17 +  more details.
   12.18 +  
   12.19 +  You should have received a copy of the GNU General Public License along with
   12.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   12.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   12.22 +  
   12.23 +  The full GNU General Public License is included in this distribution in the
   12.24 +  file called LICENSE.
   12.25 +  
   12.26 +  Contact Information:
   12.27 +  Linux NICS <linux.nics@intel.com>
   12.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   12.29 +
   12.30 +*******************************************************************************/
   12.31 +
   12.32 +#include "e1000.h"
   12.33 +
   12.34 +/* This is the only thing that needs to be changed to adjust the
   12.35 + * maximum number of ports that the driver can manage.
   12.36 + */
   12.37 +
   12.38 +#define E1000_MAX_NIC 32
   12.39 +
   12.40 +#define OPTION_UNSET    -1
   12.41 +#define OPTION_DISABLED 0
   12.42 +#define OPTION_ENABLED  1
   12.43 +
   12.44 +/* Module Parameters are always initialized to -1, so that the driver
   12.45 + * can tell the difference between no user specified value or the
   12.46 + * user asking for the default value.
   12.47 + * The true default values are loaded in when e1000_check_options is called.
   12.48 + *
   12.49 + * This is a GCC extension to ANSI C.
   12.50 + * See the item "Labeled Elements in Initializers" in the section
   12.51 + * "Extensions to the C Language Family" of the GCC documentation.
   12.52 + */
   12.53 +
   12.54 +#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
   12.55 +
   12.56 +/* All parameters are treated the same, as an integer array of values.
   12.57 + * This macro just reduces the need to repeat the same declaration code
   12.58 + * over and over (plus this helps to avoid typo bugs).
   12.59 + */
   12.60 +
   12.61 +#define E1000_PARAM(X, S) \
   12.62 +static const int __devinitdata X[E1000_MAX_NIC + 1] = E1000_PARAM_INIT; \
   12.63 +MODULE_PARM(X, "1-" __MODULE_STRING(E1000_MAX_NIC) "i"); \
   12.64 +MODULE_PARM_DESC(X, S);
   12.65 +
   12.66 +/* Transmit Descriptor Count
   12.67 + *
   12.68 + * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
   12.69 + * Valid Range: 80-4096 for 82544
   12.70 + *
   12.71 + * Default Value: 256
   12.72 + */
   12.73 +
   12.74 +E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
   12.75 +
   12.76 +/* Receive Descriptor Count
   12.77 + *
   12.78 + * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
   12.79 + * Valid Range: 80-4096 for 82544
   12.80 + *
   12.81 + * Default Value: 80
   12.82 + */
   12.83 +
   12.84 +E1000_PARAM(RxDescriptors, "Number of receive descriptors");
   12.85 +
   12.86 +/* User Specified Speed Override
   12.87 + *
   12.88 + * Valid Range: 0, 10, 100, 1000
   12.89 + *  - 0    - auto-negotiate at all supported speeds
   12.90 + *  - 10   - only link at 10 Mbps
   12.91 + *  - 100  - only link at 100 Mbps
   12.92 + *  - 1000 - only link at 1000 Mbps
   12.93 + *
   12.94 + * Default Value: 0
   12.95 + */
   12.96 +
   12.97 +E1000_PARAM(Speed, "Speed setting");
   12.98 +
   12.99 +/* User Specified Duplex Override
  12.100 + *
  12.101 + * Valid Range: 0-2
  12.102 + *  - 0 - auto-negotiate for duplex
  12.103 + *  - 1 - only link at half duplex
  12.104 + *  - 2 - only link at full duplex
  12.105 + *
  12.106 + * Default Value: 0
  12.107 + */
  12.108 +
  12.109 +E1000_PARAM(Duplex, "Duplex setting");
  12.110 +
  12.111 +/* Auto-negotiation Advertisement Override
  12.112 + *
  12.113 + * Valid Range: 0x01-0x0F, 0x20-0x2F
  12.114 + *
  12.115 + * The AutoNeg value is a bit mask describing which speed and duplex
  12.116 + * combinations should be advertised during auto-negotiation.
  12.117 + * The supported speed and duplex modes are listed below
  12.118 + *
  12.119 + * Bit           7     6     5      4      3     2     1      0
  12.120 + * Speed (Mbps)  N/A   N/A   1000   N/A    100   100   10     10
  12.121 + * Duplex                    Full          Full  Half  Full   Half
  12.122 + *
  12.123 + * Default Value: 0x2F
  12.124 + */
  12.125 +
  12.126 +E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
  12.127 +
  12.128 +/* User Specified Flow Control Override
  12.129 + *
  12.130 + * Valid Range: 0-3
  12.131 + *  - 0 - No Flow Control
  12.132 + *  - 1 - Rx only, respond to PAUSE frames but do not generate them
  12.133 + *  - 2 - Tx only, generate PAUSE frames but ignore them on receive
  12.134 + *  - 3 - Full Flow Control Support
  12.135 + *
  12.136 + * Default Value: Read flow control settings from the EEPROM
  12.137 + */
  12.138 +
  12.139 +E1000_PARAM(FlowControl, "Flow Control setting");
  12.140 +
  12.141 +/* XsumRX - Receive Checksum Offload Enable/Disable
  12.142 + *
  12.143 + * Valid Range: 0, 1
  12.144 + *  - 0 - disables all checksum offload
  12.145 + *  - 1 - enables receive IP/TCP/UDP checksum offload
  12.146 + *        on 82543 based NICs
  12.147 + *
  12.148 + * Default Value: 1
  12.149 + */
  12.150 +
  12.151 +E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
  12.152 +
  12.153 +/* Transmit Interrupt Delay in units of 1.024 microseconds
  12.154 + *
  12.155 + * Valid Range: 0-65535
  12.156 + *
  12.157 + * Default Value: 64
  12.158 + */
  12.159 +
  12.160 +E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
  12.161 +
  12.162 +/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
  12.163 + *
  12.164 + * Valid Range: 0-65535
  12.165 + *
  12.166 + * Default Value: 0
  12.167 + */
  12.168 +
  12.169 +E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
  12.170 +
  12.171 +/* Receive Interrupt Delay in units of 1.024 microseconds
  12.172 + *
  12.173 + * Valid Range: 0-65535
  12.174 + *
  12.175 + * Default Value: 0/128
  12.176 + */
  12.177 +
  12.178 +E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
  12.179 +
  12.180 +/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
  12.181 + *
  12.182 + * Valid Range: 0-65535
  12.183 + *
  12.184 + * Default Value: 128
  12.185 + */
  12.186 +
  12.187 +E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
  12.188 +
  12.189 +#define AUTONEG_ADV_DEFAULT  0x2F
  12.190 +#define AUTONEG_ADV_MASK     0x2F
  12.191 +#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
  12.192 +
  12.193 +#define DEFAULT_TXD                  256
  12.194 +#define MAX_TXD                      256
  12.195 +#define MIN_TXD                       80
  12.196 +#define MAX_82544_TXD               4096
  12.197 +
  12.198 +#define DEFAULT_RXD                   80
  12.199 +#define MAX_RXD                      256
  12.200 +#define MIN_RXD                       80
  12.201 +#define MAX_82544_RXD               4096
  12.202 +
  12.203 +#define DEFAULT_RDTR                   0
  12.204 +#define MAX_RXDELAY               0xFFFF
  12.205 +#define MIN_RXDELAY                    0
  12.206 +
  12.207 +#define DEFAULT_RADV                 128
  12.208 +#define MAX_RXABSDELAY            0xFFFF
  12.209 +#define MIN_RXABSDELAY                 0
  12.210 +
  12.211 +#define DEFAULT_TIDV                  64
  12.212 +#define MAX_TXDELAY               0xFFFF
  12.213 +#define MIN_TXDELAY                    0
  12.214 +
  12.215 +#define DEFAULT_TADV                  64
  12.216 +#define MAX_TXABSDELAY            0xFFFF
  12.217 +#define MIN_TXABSDELAY                 0
  12.218 +
  12.219 +struct e1000_option {
  12.220 +	enum { enable_option, range_option, list_option } type;
  12.221 +	char *name;
  12.222 +	char *err;
  12.223 +	int  def;
  12.224 +	union {
  12.225 +		struct { /* range_option info */
  12.226 +			int min;
  12.227 +			int max;
  12.228 +		} r;
  12.229 +		struct { /* list_option info */
  12.230 +			int nr;
  12.231 +			struct e1000_opt_list { int i; char *str; } *p;
  12.232 +		} l;
  12.233 +	} arg;
  12.234 +};
  12.235 +
  12.236 +static int __devinit
  12.237 +e1000_validate_option(int *value, struct e1000_option *opt)
  12.238 +{
  12.239 +	if(*value == OPTION_UNSET) {
  12.240 +		*value = opt->def;
  12.241 +		return 0;
  12.242 +	}
  12.243 +
  12.244 +	switch (opt->type) {
  12.245 +	case enable_option:
  12.246 +		switch (*value) {
  12.247 +		case OPTION_ENABLED:
  12.248 +			printk(KERN_INFO "%s Enabled\n", opt->name);
  12.249 +			return 0;
  12.250 +		case OPTION_DISABLED:
  12.251 +			printk(KERN_INFO "%s Disabled\n", opt->name);
  12.252 +			return 0;
  12.253 +		}
  12.254 +		break;
  12.255 +	case range_option:
  12.256 +		if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
  12.257 +			printk(KERN_INFO "%s set to %i\n", opt->name, *value);
  12.258 +			return 0;
  12.259 +		}
  12.260 +		break;
  12.261 +	case list_opt