ia64/xen-unstable

changeset 198:db73fd255933

bitkeeper revision 1.59 (3e4fde99RPNgqKfeXcO9RFD8kcDohQ)

Further PCI upgrade to 2.4.21-pre4. moonraider boots with UDMA-100 enabled for IDE discs.
author kaf24@labyrinth.cl.cam.ac.uk
date Sun Feb 16 18:55:21 2003 +0000 (2003-02-16)
parents d35939d8ec52
children fa8759fd4b27
files xen-2.4.16/drivers/pci/pci.c xen-2.4.16/drivers/pci/pci.ids xen-2.4.16/drivers/pci/quirks.c xen-2.4.16/include/xeno/pci.h xen-2.4.16/include/xeno/pci_ids.h
line diff
     1.1 --- a/xen-2.4.16/drivers/pci/pci.c	Sun Feb 16 18:08:23 2003 +0000
     1.2 +++ b/xen-2.4.16/drivers/pci/pci.c	Sun Feb 16 18:55:21 2003 +0000
     1.3 @@ -164,6 +164,8 @@ pci_find_class(unsigned int class, const
     1.4   *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
     1.5   *
     1.6   *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap 
     1.7 + *
     1.8 + *  %PCI_CAP_ID_PCIX         PCI-X
     1.9   */
    1.10  int
    1.11  pci_find_capability(struct pci_dev *dev, int cap)
    1.12 @@ -931,14 +933,13 @@ pdev_set_mwi(struct pci_dev *dev)
    1.13  	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cache_size);
    1.14  	cache_size <<= 2;
    1.15  	if (cache_size != SMP_CACHE_BYTES) {
    1.16 -		printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly "
    1.17 -		       "(%i bytes) by BIOS/FW, ",
    1.18 +		printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly (%i bytes) by BIOS/FW.\n",
    1.19  		       dev->slot_name, cache_size);
    1.20  		if (cache_size > SMP_CACHE_BYTES) {
    1.21 -			printk("expecting %i\n", SMP_CACHE_BYTES);
    1.22 +			printk("PCI: %s cache line size too large - expecting %i.\n", dev->slot_name, SMP_CACHE_BYTES);
    1.23  			rc = -EINVAL;
    1.24  		} else {
    1.25 -			printk("correcting to %i\n", SMP_CACHE_BYTES);
    1.26 +			printk("PCI: %s PCI cache line size corrected to %i.\n", dev->slot_name, SMP_CACHE_BYTES);
    1.27  			pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
    1.28  					      SMP_CACHE_BYTES >> 2);
    1.29  		}
    1.30 @@ -1038,13 +1039,20 @@ static inline unsigned int pci_calc_reso
    1.31  }
    1.32  
    1.33  /*
    1.34 - * Find the extent of a PCI decode..
    1.35 + * Find the extent of a PCI decode, do sanity checks.
    1.36   */
    1.37 -static u32 pci_size(u32 base, unsigned long mask)
    1.38 +static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
    1.39  {
    1.40 -	u32 size = mask & base;		/* Find the significant bits */
    1.41 +	u32 size = mask & maxbase;	/* Find the significant bits */
    1.42 +	if (!size)
    1.43 +		return 0;
    1.44  	size = size & ~(size-1);	/* Get the lowest of them to find the decode size */
    1.45 -	return size-1;			/* extent = size - 1 */
    1.46 +	size -= 1;			/* extent = size - 1 */
    1.47 +	if (base == maxbase && ((base | size) & mask) != mask)
    1.48 +		return 0;		/* base == maxbase can be valid only
    1.49 +					   if the BAR has been already
    1.50 +					   programmed with all 1s */
    1.51 +	return size;
    1.52  }
    1.53  
    1.54  static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
    1.55 @@ -1067,13 +1075,17 @@ static void pci_read_bases(struct pci_de
    1.56  		if (l == 0xffffffff)
    1.57  			l = 0;
    1.58  		if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
    1.59 +			sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
    1.60 +			if (!sz)
    1.61 +				continue;
    1.62  			res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
    1.63  			res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
    1.64 -			sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
    1.65  		} else {
    1.66 +			sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
    1.67 +			if (!sz)
    1.68 +				continue;
    1.69  			res->start = l & PCI_BASE_ADDRESS_IO_MASK;
    1.70  			res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
    1.71 -			sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
    1.72  		}
    1.73  		res->end = res->start + (unsigned long) sz;
    1.74  		res->flags |= pci_calc_resource_flags(l);
    1.75 @@ -1103,6 +1115,7 @@ static void pci_read_bases(struct pci_de
    1.76  	if (rom) {
    1.77  		dev->rom_base_reg = rom;
    1.78  		res = &dev->resource[PCI_ROM_RESOURCE];
    1.79 +		res->name = dev->name;
    1.80  		pci_read_config_dword(dev, rom, &l);
    1.81  		pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
    1.82  		pci_read_config_dword(dev, rom, &sz);
    1.83 @@ -1110,13 +1123,14 @@ static void pci_read_bases(struct pci_de
    1.84  		if (l == 0xffffffff)
    1.85  			l = 0;
    1.86  		if (sz && sz != 0xffffffff) {
    1.87 +			sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
    1.88 +			if (!sz)
    1.89 +				return;
    1.90  			res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
    1.91  			  IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
    1.92  			res->start = l & PCI_ROM_ADDRESS_MASK;
    1.93 -			sz = pci_size(sz, PCI_ROM_ADDRESS_MASK);
    1.94  			res->end = res->start + (unsigned long) sz;
    1.95  		}
    1.96 -		res->name = dev->name;
    1.97  	}
    1.98  }
    1.99  
   1.100 @@ -1731,6 +1745,7 @@ pci_pm_callback(struct pm_dev *pm_device
   1.101  
   1.102  #endif
   1.103  
   1.104 +
   1.105  #if 0 /* XXX KAF: Only USB uses this stuff -- I think we'll just bin it. */
   1.106  
   1.107  /*
   1.108 @@ -2158,6 +2173,8 @@ EXPORT_SYMBOL(pci_add_new_bus);
   1.109  EXPORT_SYMBOL(pci_do_scan_bus);
   1.110  EXPORT_SYMBOL(pci_scan_slot);
   1.111  EXPORT_SYMBOL(pci_scan_bus);
   1.112 +EXPORT_SYMBOL(pci_scan_device);
   1.113 +EXPORT_SYMBOL(pci_read_bridge_bases);
   1.114  #ifdef CONFIG_PROC_FS
   1.115  EXPORT_SYMBOL(pci_proc_attach_device);
   1.116  EXPORT_SYMBOL(pci_proc_detach_device);
     2.1 --- a/xen-2.4.16/drivers/pci/pci.ids	Sun Feb 16 18:08:23 2003 +0000
     2.2 +++ b/xen-2.4.16/drivers/pci/pci.ids	Sun Feb 16 18:55:21 2003 +0000
     2.3 @@ -582,6 +582,7 @@ 1013  Cirrus Logic
     2.4  	6003  CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]
     2.5  		1013 4280  Crystal SoundFusion PCI Audio Accelerator
     2.6  		1681 0050  Hercules Game Theater XP
     2.7 +		1681 a011  Hercules Fortissimo III 7.1
     2.8  	6004  CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator]
     2.9  	6005  Crystal CS4281 PCI Audio
    2.10  		1013 4281  Crystal CS4281 PCI Audio
    2.11 @@ -2617,6 +2618,7 @@ 10fb  Thesys Gesellschaft für Mikroelektronik mbH
    2.12  10fc  I-O Data Device, Inc.
    2.13  # What's in the cardbus end of a Sony ACR-A01 card, comes with newer Vaio CD-RW drives
    2.14  	0003  Cardbus IDE Controller
    2.15 +	0005  Cardbus SCSI CBSC II
    2.16  10fd  Soyo Computer, Inc
    2.17  10fe  Fast Multimedia AG
    2.18  10ff  NCube
    2.19 @@ -2678,6 +2680,7 @@ 1106  VIA Technologies, Inc.
    2.20  	0505  VT82C505
    2.21  	0561  VT82C561
    2.22  	0571  VT82C586B PIPC Bus Master IDE
    2.23 +		1458 5002 GA-7VAX Mainboard
    2.24  	0576  VT82C576 3V [Apollo Master]
    2.25  	0585  VT82C585VP [Apollo VP1/VPX]
    2.26  	0586  VT82C586/A/B PCI-to-ISA [Apollo VP]
    2.27 @@ -2726,6 +2729,7 @@ 1106  VIA Technologies, Inc.
    2.28  		1462 3091  MS-6309 Onboard Audio
    2.29  		15dd 7609  Onboard Audio
    2.30  	3059  VT8233 AC97 Audio Controller
    2.31 +		1458 a002  GA-7VAX Onboard Audio (Realtek ALC650) 
    2.32  	3065  VT6102 [Rhine-II]
    2.33  		1186 1400  DFE-530TX rev A
    2.34  		1186 1401  DFE-530TX rev B
    2.35 @@ -2739,6 +2743,7 @@ 1106  VIA Technologies, Inc.
    2.36  	3102  VT8662 Host Bridge
    2.37  	3103  VT8615 Host Bridge
    2.38  	3104  USB 2.0
    2.39 +		1458 5004  GA-7VAX Mainboard
    2.40  	3109  VT8233C PCI to ISA Bridge
    2.41  	3112  VT8361 [KLE133] Host Bridge
    2.42  	3128  VT8753 [P4X266 AGP]
    2.43 @@ -2747,6 +2752,9 @@ 1106  VIA Technologies, Inc.
    2.44  	3148  P4M266 Host Bridge
    2.45  	3156  P/KN266 Host Bridge
    2.46  	3177  VT8233A ISA Bridge
    2.47 +		1458 5001 GA-7VAX Mainboard
    2.48 +	3189  VT8377 [KT400 AGP] Host Bridge
    2.49 +		1458 5000 GA-7VAX Mainboard
    2.50  	5030  VT82C596 ACPI [Apollo PRO]
    2.51  	6100  VT85C100A [Rhine II]
    2.52  	8231  VT8231 [PCI-to-ISA Bridge]
    2.53 @@ -2767,6 +2775,7 @@ 1106  VIA Technologies, Inc.
    2.54  	b102  VT8362 AGP Bridge
    2.55  	b103  VT8615 AGP Bridge
    2.56  	b112  VT8361 [KLE133] AGP Bridge
    2.57 +	b168  VT8235 PCI Bridge
    2.58  1107  Stratus Computers
    2.59  	0576  VIA VT82C570MV [Apollo] (Wrong vendor ID!)
    2.60  1108  Proteon, Inc.
    2.61 @@ -3027,6 +3036,12 @@ 1143  NetPower, Inc
    2.62  1144  Cincinnati Milacron
    2.63  	0001  Noservo controller
    2.64  1145  Workbit Corporation
    2.65 +	f007  NinjaSCSI-32 KME
    2.66 +	8007  NinjaSCSI-32 Workbit
    2.67 +	f010  NinjaSCSI-32 Workbit
    2.68 +	f012  NinjaSCSI-32 Logitec
    2.69 +	f013  NinjaSCSI-32 Logitec
    2.70 +	f015  NinjaSCSI-32 Melco
    2.71  1146  Force Computers
    2.72  1147  Interface Corp
    2.73  1148  Syskonnect (Schneider & Koch)
     3.1 --- a/xen-2.4.16/drivers/pci/quirks.c	Sun Feb 16 18:08:23 2003 +0000
     3.2 +++ b/xen-2.4.16/drivers/pci/quirks.c	Sun Feb 16 18:55:21 2003 +0000
     3.3 @@ -167,6 +167,21 @@ static void __init quirk_vsfx(struct pci
     3.4  	}
     3.5  }
     3.6  
     3.7 +/*
     3.8 + *	Ali Magik requires workarounds to be used by the drivers
     3.9 + *	that DMA to AGP space. Latency must be set to 0xA and triton
    3.10 + *	workaround applied too
    3.11 + *	[Info kindly provided by ALi]
    3.12 + */	
    3.13 + 
    3.14 +static void __init quirk_alimagik(struct pci_dev *dev)
    3.15 +{
    3.16 +	if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
    3.17 +	{
    3.18 +		printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
    3.19 +		pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
    3.20 +	}
    3.21 +}
    3.22  
    3.23  /*
    3.24   *	Natoma has some interesting boundary conditions with Zoran stuff
    3.25 @@ -212,6 +227,19 @@ static void __init quirk_io_region(struc
    3.26  }	
    3.27  
    3.28  /*
    3.29 + *	ATI Northbridge setups MCE the processor if you even
    3.30 + *	read somewhere between 0x3b0->0x3bb or read 0x3d3
    3.31 + */
    3.32 + 
    3.33 +static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
    3.34 +{
    3.35 +	printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
    3.36 +	/* Mae rhaid in i beidio a edrych ar y lleoliad I/O hyn */
    3.37 +	request_region(0x3b0, 0x0C, "RadeonIGP");
    3.38 +	request_region(0x3d3, 0x01, "RadeonIGP");
    3.39 +}
    3.40 +
    3.41 +/*
    3.42   * Let's make the southbridge information explicit instead
    3.43   * of having to worry about people probing the ACPI areas,
    3.44   * for example.. (Yes, it happens, and if you read the wrong
    3.45 @@ -495,6 +523,56 @@ static void __init quirk_mediagx_master(
    3.46  }
    3.47  
    3.48  /*
    3.49 + * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
    3.50 + * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
    3.51 + * secondary channels respectively). If the device reports Compatible mode
    3.52 + * but does use BAR0-3 for address decoding, we assume that firmware has
    3.53 + * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
    3.54 + * Exceptions (if they exist) must be handled in chip/architecture specific
    3.55 + * fixups.
    3.56 + *
    3.57 + * Note: for non x86 people. You may need an arch specific quirk to handle
    3.58 + * moving IDE devices to native mode as well. Some plug in card devices power
    3.59 + * up in compatible mode and assume the BIOS will adjust them.
    3.60 + *
    3.61 + * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
    3.62 + * we do now ? We don't want is pci_enable_device to come along
    3.63 + * and assign new resources. Both approaches work for that.
    3.64 + */ 
    3.65 +
    3.66 +static void __devinit quirk_ide_bases(struct pci_dev *dev)
    3.67 +{
    3.68 +       struct resource *res;
    3.69 +       int first_bar = 2, last_bar = 0;
    3.70 +
    3.71 +       if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
    3.72 +               return;
    3.73 +
    3.74 +       res = &dev->resource[0];
    3.75 +
    3.76 +       /* primary channel: ProgIf bit 0, BAR0, BAR1 */
    3.77 +       if (!(dev->class & 1) && (res[0].flags || res[1].flags)) { 
    3.78 +               res[0].start = res[0].end = res[0].flags = 0;
    3.79 +               res[1].start = res[1].end = res[1].flags = 0;
    3.80 +               first_bar = 0;
    3.81 +               last_bar = 1;
    3.82 +       }
    3.83 +
    3.84 +       /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
    3.85 +       if (!(dev->class & 4) && (res[2].flags || res[3].flags)) { 
    3.86 +               res[2].start = res[2].end = res[2].flags = 0;
    3.87 +               res[3].start = res[3].end = res[3].flags = 0;
    3.88 +               last_bar = 3;
    3.89 +       }
    3.90 +
    3.91 +       if (!last_bar)
    3.92 +               return;
    3.93 +
    3.94 +       printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
    3.95 +              first_bar, last_bar, dev->slot_name);
    3.96 +}
    3.97 +
    3.98 +/*
    3.99   *  The main table of quirks.
   3.100   */
   3.101  
   3.102 @@ -521,6 +599,8 @@ static struct pci_fixup pci_fixups[] __i
   3.103  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_0, 	quirk_natoma }, 
   3.104  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_1, 	quirk_natoma }, 
   3.105  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_INTEL, 	PCI_DEVICE_ID_INTEL_82443BX_2, 	quirk_natoma },
   3.106 +	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_AL, 	PCI_DEVICE_ID_AL_M1647, 	quirk_alimagik },
   3.107 +	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_AL, 	PCI_DEVICE_ID_AL_M1651, 	quirk_alimagik },
   3.108  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci },
   3.109  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci },
   3.110  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency },
   3.111 @@ -535,6 +615,7 @@ static struct pci_fixup pci_fixups[] __i
   3.112  	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi },
   3.113   	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371SB_2,	quirk_piix3_usb },
   3.114  	{ PCI_FIXUP_HEADER,	PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_2,	quirk_piix3_usb },
   3.115 +	{ PCI_FIXUP_HEADER,     PCI_ANY_ID,             PCI_ANY_ID,                     quirk_ide_bases },
   3.116  	{ PCI_FIXUP_FINAL,	PCI_ANY_ID,		PCI_ANY_ID,			quirk_cardbus_legacy },
   3.117  
   3.118  #ifdef CONFIG_X86_IO_APIC 
   3.119 @@ -548,6 +629,7 @@ static struct pci_fixup pci_fixups[] __i
   3.120  
   3.121  	{ PCI_FIXUP_FINAL, 	PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic },
   3.122  	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
   3.123 +	{ PCI_FIXUP_FINAL,	PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RADEON_IGP,   quirk_ati_exploding_mce },
   3.124  	/*
   3.125  	 * i82380FB mobile docking controller: its PCI-to-PCI bridge
   3.126  	 * is subtractive decoding (transparent), and does indicate this
     4.1 --- a/xen-2.4.16/include/xeno/pci.h	Sun Feb 16 18:08:23 2003 +0000
     4.2 +++ b/xen-2.4.16/include/xeno/pci.h	Sun Feb 16 18:55:21 2003 +0000
     4.3 @@ -65,9 +65,9 @@
     4.4  #define  PCI_HEADER_TYPE_CARDBUS 2
     4.5  
     4.6  #define PCI_BIST		0x0f	/* 8 bits */
     4.7 -#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
     4.8 -#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
     4.9 -#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
    4.10 +#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
    4.11 +#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
    4.12 +#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
    4.13  
    4.14  /*
    4.15   * Base addresses specify locations in memory or I/O space.
    4.16 @@ -195,6 +195,7 @@
    4.17  #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
    4.18  #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
    4.19  #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
    4.20 +#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
    4.21  #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
    4.22  #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
    4.23  #define PCI_CAP_SIZEOF		4
    4.24 @@ -271,6 +272,37 @@
    4.25  #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
    4.26  #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
    4.27  
    4.28 +/* CompactPCI Hotswap Register */
    4.29 +
    4.30 +#define PCI_CHSWP_CSR		2	/* Control and Status Register */
    4.31 +#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
    4.32 +#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
    4.33 +#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
    4.34 +#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
    4.35 +#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
    4.36 +#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
    4.37 +#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
    4.38 +
    4.39 +/* PCI-X registers */
    4.40 +
    4.41 +#define PCI_X_CMD		2	/* Modes & Features */
    4.42 +#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
    4.43 +#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
    4.44 +#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
    4.45 +#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
    4.46 +#define PCI_X_DEVFN		4	/* A copy of devfn. */
    4.47 +#define PCI_X_BUSNR		5	/* Bus segment number */
    4.48 +#define PCI_X_STATUS		6	/* PCI-X capabilities */
    4.49 +#define  PCI_X_STATUS_64BIT	0x0001	/* 64-bit device */
    4.50 +#define  PCI_X_STATUS_133MHZ	0x0002	/* 133 MHz capable */
    4.51 +#define  PCI_X_STATUS_SPL_DISC	0x0004	/* Split Completion Discarded */
    4.52 +#define  PCI_X_STATUS_UNX_SPL	0x0008	/* Unexpected Split Completion */
    4.53 +#define  PCI_X_STATUS_COMPLEX	0x0010	/* Device Complexity */
    4.54 +#define  PCI_X_STATUS_MAX_READ	0x0060	/* Designed Maximum Memory Read Count */
    4.55 +#define  PCI_X_STATUS_MAX_SPLIT	0x0380	/* Design Max Outstanding Split Trans */
    4.56 +#define  PCI_X_STATUS_MAX_CUM	0x1c00	/* Designed Max Cumulative Read Size */
    4.57 +#define  PCI_X_STATUS_SPL_ERR	0x2000	/* Rcvd Split Completion Error Msg */
    4.58 +
    4.59  /* Include the ID list */
    4.60  
    4.61  #include <linux/pci_ids.h>
    4.62 @@ -769,6 +801,7 @@ extern int pci_pci_problems;
    4.63  #define PCIPCI_NATOMA		4
    4.64  #define PCIPCI_VIAETBF		8
    4.65  #define PCIPCI_VSFX		16
    4.66 +#define PCIPCI_ALIMAGIK		32
    4.67  
    4.68  #endif /* __KERNEL__ */
    4.69  #endif /* LINUX_PCI_H */
     5.1 --- a/xen-2.4.16/include/xeno/pci_ids.h	Sun Feb 16 18:08:23 2003 +0000
     5.2 +++ b/xen-2.4.16/include/xeno/pci_ids.h	Sun Feb 16 18:55:21 2003 +0000
     5.3 @@ -136,6 +136,7 @@
     5.4  #define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
     5.5  #define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
     5.6  #define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
     5.7 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
     5.8  #define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
     5.9  #define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
    5.10  #define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
    5.11 @@ -143,6 +144,7 @@
    5.12  #define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
    5.13  #define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
    5.14  #define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
    5.15 +#define PCI_DEVICE_ID_COMPAQ_CISSC 	0x0046
    5.16  #define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
    5.17  #define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
    5.18  
    5.19 @@ -172,6 +174,8 @@
    5.20  #define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
    5.21  #define PCI_DEVICE_ID_LSI_FC919		0x0624
    5.22  #define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
    5.23 +#define PCI_DEVICE_ID_LSI_FC929X	0x0626
    5.24 +#define PCI_DEVICE_ID_LSI_FC919X	0x0628
    5.25  #define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
    5.26  #define PCI_DEVICE_ID_LSI_61C102	0x0901
    5.27  #define PCI_DEVICE_ID_LSI_63C815	0x1000
    5.28 @@ -265,6 +269,8 @@
    5.29  #define PCI_DEVICE_ID_ATI_RADEON_RB	0x5145
    5.30  #define PCI_DEVICE_ID_ATI_RADEON_RC	0x5146
    5.31  #define PCI_DEVICE_ID_ATI_RADEON_RD	0x5147
    5.32 +/* RadeonIGP */
    5.33 +#define PCI_DEVICE_ID_ATI_RADEON_IGP	0xCAB0
    5.34  
    5.35  #define PCI_VENDOR_ID_VLSI		0x1004
    5.36  #define PCI_DEVICE_ID_VLSI_82C592	0x0005
    5.37 @@ -288,6 +294,12 @@
    5.38  #define PCI_DEVICE_ID_NS_87560_USB	0x0012
    5.39  #define PCI_DEVICE_ID_NS_83815		0x0020
    5.40  #define PCI_DEVICE_ID_NS_83820		0x0022
    5.41 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
    5.42 +#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
    5.43 +#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
    5.44 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
    5.45 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
    5.46 +#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
    5.47  #define PCI_DEVICE_ID_NS_87410		0xd001
    5.48  
    5.49  #define PCI_VENDOR_ID_TSENG		0x100c
    5.50 @@ -372,7 +384,7 @@
    5.51  #define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
    5.52  #define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
    5.53  #define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
    5.54 -#define PCI_DEVIDE_ID_AMD_FE_GATE_700D	0x700D
    5.55 +#define PCI_DEVICE_ID_AMD_FE_GATE_700D	0x700D
    5.56  #define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
    5.57  #define PCI_DEVICE_ID_AMD_FE_GATE_700F	0x700F
    5.58  #define PCI_DEVICE_ID_AMD_COBRA_7400	0x7400
    5.59 @@ -387,11 +399,19 @@
    5.60  #define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
    5.61  #define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
    5.62  #define PCI_DEVICE_ID_AMD_VIPER_7414	0x7414
    5.63 -#define PCI_DEVICE_ID_AMD_VIPER_7440	0x7440
    5.64 -#define PCI_DEVICE_ID_AMD_VIPER_7441	0x7441
    5.65 -#define PCI_DEVICE_ID_AMD_VIPER_7443	0x7443
    5.66 -#define PCI_DEVICE_ID_AMD_VIPER_7448	0x7448
    5.67 -#define PCI_DEVICE_ID_AMD_VIPER_7449	0x7449
    5.68 +#define PCI_DEVICE_ID_AMD_OPUS_7440	0x7440
    5.69 +#	define PCI_DEVICE_ID_AMD_VIPER_7440	PCI_DEVICE_ID_AMD_OPUS_7440
    5.70 +#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
    5.71 +#	define PCI_DEVICE_ID_AMD_VIPER_7441	PCI_DEVICE_ID_AMD_OPUS_7441
    5.72 +#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
    5.73 +#	define PCI_DEVICE_ID_AMD_VIPER_7443	PCI_DEVICE_ID_AMD_OPUS_7443
    5.74 +#define PCI_DEVICE_ID_AMD_OPUS_7448	0x7448
    5.75 +# define	PCI_DEVICE_ID_AMD_VIPER_7448	PCI_DEVICE_ID_AMD_OPUS_7448
    5.76 +#define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
    5.77 +#	define PCI_DEVICE_ID_AMD_VIPER_7449	PCI_DEVICE_ID_AMD_OPUS_7449
    5.78 +#define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
    5.79 +#define PCI_DEVICE_ID_AMD_8111_IDE     0x7469
    5.80 +#define PCI_DEVICE_ID_AMD_8111_AC97    0x746d
    5.81  
    5.82  #define PCI_VENDOR_ID_TRIDENT		0x1023
    5.83  #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
    5.84 @@ -518,6 +538,8 @@
    5.85  #define PCI_DEVICE_ID_HP_DIVA1		0x1049
    5.86  #define PCI_DEVICE_ID_HP_DIVA2		0x104A
    5.87  #define PCI_DEVICE_ID_HP_SP2_0		0x104B
    5.88 +#define PCI_DEVICE_ID_HP_REO_SBA	0x10f0
    5.89 +#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
    5.90  #define PCI_DEVICE_ID_HP_ZX1_SBA	0x1229
    5.91  #define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
    5.92  #define PCI_DEVICE_ID_HP_ZX1_LBA	0x122e
    5.93 @@ -605,6 +627,7 @@
    5.94  #define PCI_VENDOR_ID_MOTOROLA_OOPS	0x1507
    5.95  #define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
    5.96  #define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
    5.97 +#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
    5.98  #define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
    5.99  #define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
   5.100  #define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
   5.101 @@ -617,8 +640,7 @@
   5.102  #define PCI_DEVICE_ID_PROMISE_20262	0x4d38
   5.103  #define PCI_DEVICE_ID_PROMISE_20263	0x0D38
   5.104  #define PCI_DEVICE_ID_PROMISE_20268	0x4d68
   5.105 -#define PCI_DEVICE_ID_PROMISE_20268R	0x6268
   5.106 -#define PCI_DEVICE_ID_PROMISE_20270     0x6268  /* XXX IAP */
   5.107 +#define PCI_DEVICE_ID_PROMISE_20270	0x6268
   5.108  #define PCI_DEVICE_ID_PROMISE_20269	0x4d69
   5.109  #define PCI_DEVICE_ID_PROMISE_20271	0x6269
   5.110  #define PCI_DEVICE_ID_PROMISE_20275	0x1275
   5.111 @@ -746,6 +768,9 @@
   5.112  #define PCI_DEVICE_ID_CMD_670		0x0670
   5.113  #define PCI_DEVICE_ID_CMD_680		0x0680
   5.114  
   5.115 +#define PCI_DEVICE_ID_SII_680		0x0680
   5.116 +#define PCI_DEVICE_ID_SII_3112		0x3112
   5.117 +
   5.118  #define PCI_VENDOR_ID_VISION		0x1098
   5.119  #define PCI_DEVICE_ID_VISION_QD8500	0x0001
   5.120  #define PCI_DEVICE_ID_VISION_QD8580	0x0002
   5.121 @@ -821,6 +846,7 @@
   5.122  #define PCI_DEVICE_ID_AL_M1523		0x1523
   5.123  #define PCI_DEVICE_ID_AL_M1531		0x1531
   5.124  #define PCI_DEVICE_ID_AL_M1533		0x1533
   5.125 +#define PCI_DEVICE_ID_AL_M1535 		0x1535
   5.126  #define PCI_DEVICE_ID_AL_M1541		0x1541
   5.127  #define PCI_DEVICE_ID_AL_M1621          0x1621
   5.128  #define PCI_DEVICE_ID_AL_M1631          0x1631
   5.129 @@ -875,6 +901,7 @@
   5.130  #define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
   5.131  #define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
   5.132  #define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
   5.133 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
   5.134  #define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
   5.135  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
   5.136  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
   5.137 @@ -888,6 +915,7 @@
   5.138  #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
   5.139  #define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
   5.140  #define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
   5.141 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
   5.142  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
   5.143  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
   5.144  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
   5.145 @@ -922,6 +950,7 @@
   5.146  #define PCI_DEVICE_ID_REALTEK_8029	0x8029
   5.147  #define PCI_DEVICE_ID_REALTEK_8129	0x8129
   5.148  #define PCI_DEVICE_ID_REALTEK_8139	0x8139
   5.149 +#define PCI_DEVICE_ID_REALTEK_8169	0x8169
   5.150  
   5.151  #define PCI_VENDOR_ID_XILINX		0x10ee
   5.152  #define PCI_DEVICE_ID_TURBOPAM		0x4020
   5.153 @@ -988,7 +1017,10 @@
   5.154  #define PCI_DEVICE_ID_VIA_8233C_0	0x3109
   5.155  #define PCI_DEVICE_ID_VIA_8361		0x3112
   5.156  #define PCI_DEVICE_ID_VIA_8233A		0x3147
   5.157 -#define PCI_DEVICE_ID_VIA_8235		0x3177
   5.158 +#define PCI_DEVICE_ID_VIA_P4X333   0x3168
   5.159 +#define PCI_DEVICE_ID_VIA_8235        0x3177
   5.160 +#define PCI_DEVICE_ID_VIA_8377_0  0x3189
   5.161 +#define PCI_DEVICE_ID_VIA_8377_0	0x3189
   5.162  #define PCI_DEVICE_ID_VIA_86C100A	0x6100
   5.163  #define PCI_DEVICE_ID_VIA_8231		0x8231
   5.164  #define PCI_DEVICE_ID_VIA_8231_4	0x8235
   5.165 @@ -1067,6 +1099,7 @@
   5.166  #define PCI_DEVICE_ID_EICON_DIVA20PRO_U	0xe003
   5.167  #define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
   5.168  #define PCI_DEVICE_ID_EICON_DIVA201	0xe005
   5.169 +#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
   5.170  #define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
   5.171  #define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
   5.172  #define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
   5.173 @@ -1571,6 +1604,9 @@
   5.174  #define PCI_VENDOR_ID_TEKRAM		0x1de1
   5.175  #define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
   5.176  
   5.177 +#define PCI_VENDOR_ID_HINT		0x3388
   5.178 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE	0x8013
   5.179 +
   5.180  #define PCI_VENDOR_ID_3DLABS		0x3d3d
   5.181  #define PCI_DEVICE_ID_3DLABS_300SX	0x0001
   5.182  #define PCI_DEVICE_ID_3DLABS_500TX	0x0002
   5.183 @@ -1634,6 +1670,9 @@
   5.184  #define PCI_DEVICE_ID_INTEL_I960	0x0960
   5.185  #define PCI_DEVICE_ID_INTEL_I960RM	0x0962
   5.186  #define PCI_DEVICE_ID_INTEL_82562ET	0x1031
   5.187 +
   5.188 +#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
   5.189 +
   5.190  #define PCI_DEVICE_ID_INTEL_82559ER	0x1209
   5.191  #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
   5.192  #define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222