ia64/xen-unstable

changeset 11460:da942e577e5e

[IA64] Instruction emulation patch

This patch fixes the instruction emulation issue, e.g. when executing
such instruction "ld.1 r31=[r32]", the loaded value should be zero
extended and placed in r31, but more than lowest 8 bits of r31 are set.

Signed-off-by: Xinmei Huang <Xinmei.huang@intel.com>
author awilliam@xenbuild.aw
date Thu Sep 21 15:35:45 2006 -0600 (2006-09-21)
parents 997bd5fcf307
children 432f978d1cd1
files xen/arch/ia64/vmx/mmio.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/mmio.c	Thu Sep 21 15:34:24 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/mmio.c	Thu Sep 21 15:35:45 2006 -0600
     1.3 @@ -428,7 +428,7 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
     1.4      IA64_BUNDLE bundle;
     1.5      int slot, dir=0, inst_type;
     1.6      size_t size;
     1.7 -    u64 data, value,post_update, slot1a, slot1b, temp;
     1.8 +    u64 data, post_update, slot1a, slot1b, temp;
     1.9      INST64 inst;
    1.10      regs=vcpu_regs(vcpu);
    1.11      if (IA64_RETRY == __vmx_get_domain_bundle(regs->cr_iip, &bundle)) {
    1.12 @@ -454,7 +454,6 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.13              vcpu_get_gr_nat(vcpu,inst.M4.r2,&data);
    1.14          }else if((inst.M1.x6>>2)<0xb){   //  read
    1.15              dir=IOREQ_READ;
    1.16 -            vcpu_get_gr_nat(vcpu,inst.M1.r1,&value);
    1.17          }
    1.18      }
    1.19      // Integer Load + Reg update
    1.20 @@ -462,7 +461,6 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.21          inst_type = SL_INTEGER;
    1.22          dir = IOREQ_READ;     //write
    1.23          size = (inst.M2.x6&0x3);
    1.24 -        vcpu_get_gr_nat(vcpu,inst.M2.r1,&value);
    1.25          vcpu_get_gr_nat(vcpu,inst.M2.r3,&temp);
    1.26          vcpu_get_gr_nat(vcpu,inst.M2.r2,&post_update);
    1.27          temp += post_update;
    1.28 @@ -485,7 +483,6 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.29  
    1.30          }else if((inst.M3.x6>>2)<0xb){   //  read
    1.31              dir=IOREQ_READ;
    1.32 -            vcpu_get_gr_nat(vcpu,inst.M3.r1,&value);
    1.33              vcpu_get_gr_nat(vcpu,inst.M3.r3,&temp);
    1.34              post_update = (inst.M3.i<<7)+inst.M3.imm7;
    1.35              if(inst.M3.s)
    1.36 @@ -597,13 +594,6 @@ void emulate_io_inst(VCPU *vcpu, u64 pad
    1.37          mmio_access(vcpu, padr, &data, size, ma, dir);
    1.38      }else{
    1.39          mmio_access(vcpu, padr, &data, size, ma, dir);
    1.40 -        if(size==1)
    1.41 -            data = (value & 0xffffffffffffff00U) | (data & 0xffU);
    1.42 -        else if(size==2)
    1.43 -            data = (value & 0xffffffffffff0000U) | (data & 0xffffU);
    1.44 -        else if(size==4)
    1.45 -            data = (value & 0xffffffff00000000U) | (data & 0xffffffffU);
    1.46 -
    1.47          if(inst_type==SL_INTEGER){       //gp
    1.48              vcpu_set_gr(vcpu,inst.M1.r1,data,0);
    1.49          }else{