ia64/xen-unstable

changeset 16176:da8e527d20bd

[IA64] phy_d mode in thash_vhpt_insert

Handle PHY_D mode in thash_vhpt_insert
Indentation.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Sun Oct 21 15:56:36 2007 -0600 (2007-10-21)
parents 85613b8c4176
children 98ac6d05aed2
files xen/arch/ia64/vmx/vtlb.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vtlb.c	Sun Oct 21 15:55:10 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Sun Oct 21 15:56:36 2007 -0600
     1.3 @@ -1,4 +1,3 @@
     1.4 -
     1.5  /* -*-  Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
     1.6  /*
     1.7   * vtlb.c: guest virtual tlb handling module.
     1.8 @@ -22,6 +21,7 @@
     1.9   */
    1.10  
    1.11  #include <asm/vmx_vcpu.h>
    1.12 +#include <asm/vmx_phy_mode.h>
    1.13  
    1.14  static thash_data_t *__alloc_chain(thash_cb_t *);
    1.15  
    1.16 @@ -81,9 +81,10 @@ static int
    1.17  static thash_data_t *__vtr_lookup(VCPU *vcpu, u64 va, int is_data)
    1.18  {
    1.19  
    1.20 -    thash_data_t  *trp;
    1.21 -    int  i;
    1.22 +    thash_data_t *trp;
    1.23 +    int i;
    1.24      u64 rid;
    1.25 +
    1.26      vcpu_get_rr(vcpu, va, &rid);
    1.27      rid &= RR_RID_MASK;
    1.28      if (is_data) {
    1.29 @@ -181,13 +182,15 @@ void thash_vhpt_insert(VCPU *v, u64 pte,
    1.30      u64 phy_pte, psr;
    1.31      ia64_rr mrr;
    1.32  
    1.33 -    mrr.rrval = ia64_get_rr(va);
    1.34      phy_pte = translate_phy_pte(v, &pte, itir, va);
    1.35 +    mrr.rrval = ia64_get_rr(va);
    1.36  
    1.37 -    if (itir_ps(itir) >= mrr.ps) {
    1.38 +    if (itir_ps(itir) >= mrr.ps && VMX_MMU_MODE(v) != VMX_MMU_PHY_D) {
    1.39          vmx_vhpt_insert(vcpu_get_vhpt(v), phy_pte, itir, va);
    1.40      } else {
    1.41 -        phy_pte &= ~PAGE_FLAGS_RV_MASK;
    1.42 +        if (VMX_MMU_MODE(v) == VMX_MMU_PHY_D)
    1.43 +            itir = (itir & ~RR_PS_MASK) | (mrr.rrval & RR_PS_MASK);
    1.44 +        phy_pte &= ~PAGE_FLAGS_RV_MASK; /* Clear reserved fields.  */
    1.45          psr = ia64_clear_ic();
    1.46          ia64_itc(type + 1, va, phy_pte, itir);
    1.47          ia64_set_psr(psr);
    1.48 @@ -195,6 +198,8 @@ void thash_vhpt_insert(VCPU *v, u64 pte,
    1.49      }
    1.50  }
    1.51  
    1.52 +/* On itr.d, old entries are not purged (optimization for Linux - see
    1.53 +   vmx_vcpu_itr_d).  Fixup possible mismatch.  */
    1.54  int vhpt_access_rights_fixup(VCPU *v, u64 ifa, int is_data)
    1.55  {
    1.56      thash_data_t *trp, *data;
    1.57 @@ -656,7 +661,7 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
    1.58  
    1.59      cch = __vtr_lookup(v, va, is_data);
    1.60      if (cch)
    1.61 -	return cch;
    1.62 +        return cch;
    1.63  
    1.64      if (vcpu_quick_region_check(v->arch.tc_regions, va) == 0)
    1.65          return NULL;