ia64/xen-unstable

changeset 5756:d99ebf2de9f3

Some more new files for Linux PAE.
Signed-off-by: Gerd Knorr <kraxel@suse.de>
author kaf24@firebug.cl.cam.ac.uk
date Tue Jul 12 16:20:36 2005 +0000 (2005-07-12)
parents be1153585cb0
children b513fd51f850
files linux-2.6-xen-sparse/include/asm-xen/asm-i386/bug.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-3level-defs.h linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-3level.h
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/linux-2.6-xen-sparse/include/asm-xen/asm-i386/bug.h	Tue Jul 12 16:20:36 2005 +0000
     1.3 @@ -0,0 +1,16 @@
     1.4 +#ifndef _I386_BUG_H
     1.5 +#define _I386_BUG_H
     1.6 +
     1.7 +#include <linux/config.h>
     1.8 +
     1.9 +#define BUG() do { \
    1.10 +	printk("kernel BUG at %s:%d (%s)!\n", \
    1.11 +	       __FILE__, __LINE__, __FUNCTION__); \
    1.12 +	dump_stack(); \
    1.13 +	panic("BUG!"); \
    1.14 +} while (0)
    1.15 +#define HAVE_ARCH_BUG
    1.16 +
    1.17 +#include <asm-generic/bug.h>
    1.18 +
    1.19 +#endif
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-3level-defs.h	Tue Jul 12 16:20:36 2005 +0000
     2.3 @@ -0,0 +1,25 @@
     2.4 +#ifndef _I386_PGTABLE_3LEVEL_DEFS_H
     2.5 +#define _I386_PGTABLE_3LEVEL_DEFS_H
     2.6 +
     2.7 +#define HAVE_SHARED_KERNEL_PMD 0
     2.8 +
     2.9 +/*
    2.10 + * PGDIR_SHIFT determines what a top-level page table entry can map
    2.11 + */
    2.12 +#define PGDIR_SHIFT	30
    2.13 +#define PTRS_PER_PGD	4
    2.14 +#define PTRS_PER_PGD_NO_HV 4
    2.15 +
    2.16 +/*
    2.17 + * PMD_SHIFT determines the size of the area a middle-level
    2.18 + * page table can map
    2.19 + */
    2.20 +#define PMD_SHIFT	21
    2.21 +#define PTRS_PER_PMD	512
    2.22 +
    2.23 +/*
    2.24 + * entries per page directory level
    2.25 + */
    2.26 +#define PTRS_PER_PTE	512
    2.27 +
    2.28 +#endif /* _I386_PGTABLE_3LEVEL_DEFS_H */
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/linux-2.6-xen-sparse/include/asm-xen/asm-i386/pgtable-3level.h	Tue Jul 12 16:20:36 2005 +0000
     3.3 @@ -0,0 +1,187 @@
     3.4 +#ifndef _I386_PGTABLE_3LEVEL_H
     3.5 +#define _I386_PGTABLE_3LEVEL_H
     3.6 +
     3.7 +#include <asm-generic/pgtable-nopud.h>
     3.8 +
     3.9 +/*
    3.10 + * Intel Physical Address Extension (PAE) Mode - three-level page
    3.11 + * tables on PPro+ CPUs.
    3.12 + *
    3.13 + * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
    3.14 + */
    3.15 +
    3.16 +#define pte_ERROR(e) \
    3.17 +	printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
    3.18 +#define pmd_ERROR(e) \
    3.19 +	printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
    3.20 +#define pgd_ERROR(e) \
    3.21 +	printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
    3.22 +
    3.23 +#define pud_none(pud)				0
    3.24 +#define pud_bad(pud)				0
    3.25 +#define pud_present(pud)			1
    3.26 +
    3.27 +/*
    3.28 + * Is the pte executable?
    3.29 + */
    3.30 +static inline int pte_x(pte_t pte)
    3.31 +{
    3.32 +	return !(pte_val(pte) & _PAGE_NX);
    3.33 +}
    3.34 +
    3.35 +/*
    3.36 + * All present user-pages with !NX bit are user-executable:
    3.37 + */
    3.38 +static inline int pte_exec(pte_t pte)
    3.39 +{
    3.40 +	return pte_user(pte) && pte_x(pte);
    3.41 +}
    3.42 +/*
    3.43 + * All present pages with !NX bit are kernel-executable:
    3.44 + */
    3.45 +static inline int pte_exec_kernel(pte_t pte)
    3.46 +{
    3.47 +	return pte_x(pte);
    3.48 +}
    3.49 +
    3.50 +/* Rules for using set_pte: the pte being assigned *must* be
    3.51 + * either not present or in a state where the hardware will
    3.52 + * not attempt to update the pte.  In places where this is
    3.53 + * not possible, use pte_get_and_clear to obtain the old pte
    3.54 + * value and then use set_pte to update it.  -ben
    3.55 + */
    3.56 +#define __HAVE_ARCH_SET_PTE_ATOMIC
    3.57 +
    3.58 +#if 1
    3.59 +/* use writable pagetables */
    3.60 +static inline void set_pte(pte_t *ptep, pte_t pte)
    3.61 +{
    3.62 +	ptep->pte_high = pte.pte_high;
    3.63 +	smp_wmb();
    3.64 +	ptep->pte_low = pte.pte_low;
    3.65 +}
    3.66 +# define set_pte_atomic(pteptr,pteval) \
    3.67 +		set_64bit((unsigned long long *)(pteptr),pte_val_ma(pteval))
    3.68 +#else
    3.69 +/* no writable pagetables */
    3.70 +# define set_pte(pteptr,pteval)				\
    3.71 +		xen_l1_entry_update((pteptr), (pteval))
    3.72 +# define set_pte_atomic(pteptr,pteval) set_pte(pteptr,pteval)
    3.73 +#endif
    3.74 +
    3.75 +#ifdef CONFIG_XEN_SHADOW_MODE
    3.76 +# define set_pmd(pmdptr,pmdval) \
    3.77 +		set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
    3.78 +# define set_pud(pudptr,pudval) \
    3.79 +		set_64bit((unsigned long long *)(pudptr),pud_val(pudval))
    3.80 +#else
    3.81 +# define set_pmd(pmdptr,pmdval)				\
    3.82 +		xen_l2_entry_update((pmdptr), (pmdval))
    3.83 +# define set_pud(pudptr,pudval) \
    3.84 +		xen_l3_entry_update((pudptr), (pudval))
    3.85 +#endif
    3.86 +
    3.87 +/*
    3.88 + * Pentium-II erratum A13: in PAE mode we explicitly have to flush
    3.89 + * the TLB via cr3 if the top-level pgd is changed...
    3.90 + * We do not let the generic code free and clear pgd entries due to
    3.91 + * this erratum.
    3.92 + */
    3.93 +static inline void pud_clear (pud_t * pud) { }
    3.94 +
    3.95 +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
    3.96 +
    3.97 +#define pmd_page_kernel(pmd) \
    3.98 +((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
    3.99 +
   3.100 +#define pud_page(pud) \
   3.101 +((struct page *) __va(pud_val(pud) & PAGE_MASK))
   3.102 +
   3.103 +#define pud_page_kernel(pud) \
   3.104 +((unsigned long) __va(pud_val(pud) & PAGE_MASK))
   3.105 +
   3.106 +
   3.107 +/* Find an entry in the second-level page table.. */
   3.108 +#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
   3.109 +			pmd_index(address))
   3.110 +
   3.111 +static inline pte_t ptep_get_and_clear(pte_t *ptep)
   3.112 +{
   3.113 +	pte_t res;
   3.114 +
   3.115 +	/* xchg acts as a barrier before the setting of the high bits */
   3.116 +	res.pte_low = xchg(&ptep->pte_low, 0);
   3.117 +	res.pte_high = ptep->pte_high;
   3.118 +	ptep->pte_high = 0;
   3.119 +
   3.120 +	return res;
   3.121 +}
   3.122 +
   3.123 +static inline int pte_same(pte_t a, pte_t b)
   3.124 +{
   3.125 +	return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
   3.126 +}
   3.127 +
   3.128 +#define pte_page(x)	pfn_to_page(pte_pfn(x))
   3.129 +
   3.130 +static inline int pte_none(pte_t pte)
   3.131 +{
   3.132 +	return !pte.pte_low && !pte.pte_high;
   3.133 +}
   3.134 +
   3.135 +#define INVALID_P2M_ENTRY (~0U)
   3.136 +#define FOREIGN_FRAME(_m) ((_m) | (1UL<<((sizeof(unsigned long)*8)-1)))
   3.137 +#define pte_mfn(_pte) ((_pte).pte_low >> PAGE_SHIFT) /* FIXME */
   3.138 +#define pte_pfn(_pte)                                                  \
   3.139 +({                                                                     \
   3.140 +       unsigned long mfn = pte_mfn(_pte);                              \
   3.141 +       unsigned long pfn = mfn_to_pfn(mfn);                            \
   3.142 +       if ((pfn >= max_mapnr) || (pfn_to_mfn(pfn) != mfn))             \
   3.143 +               pfn = max_mapnr; /* special: force !pfn_valid() */      \
   3.144 +       pfn;                                                            \
   3.145 +})
   3.146 +
   3.147 +extern unsigned long long __supported_pte_mask;
   3.148 +
   3.149 +static inline pte_t pfn_pte_ma(unsigned long page_nr, pgprot_t pgprot)
   3.150 +{
   3.151 +	pte_t pte;
   3.152 +
   3.153 +	pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
   3.154 +					(pgprot_val(pgprot) >> 32);
   3.155 +	pte.pte_high &= (__supported_pte_mask >> 32);
   3.156 +	pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
   3.157 +							__supported_pte_mask;
   3.158 +	return pte;
   3.159 +}
   3.160 +
   3.161 +static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
   3.162 +{
   3.163 +	return pfn_pte_ma(pfn_to_mfn(page_nr), pgprot);
   3.164 +}
   3.165 +
   3.166 +static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
   3.167 +{
   3.168 +	BUG(); panic("needs review");
   3.169 +	return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
   3.170 +			pgprot_val(pgprot)) & __supported_pte_mask);
   3.171 +}
   3.172 +
   3.173 +/*
   3.174 + * Bits 0, 6 and 7 are taken in the low part of the pte,
   3.175 + * put the 32 bits of offset into the high part.
   3.176 + */
   3.177 +#define pte_to_pgoff(pte) ((pte).pte_high)
   3.178 +#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
   3.179 +#define PTE_FILE_MAX_BITS       32
   3.180 +
   3.181 +/* Encode and de-code a swap entry */
   3.182 +#define __swp_type(x)			(((x).val) & 0x1f)
   3.183 +#define __swp_offset(x)			((x).val >> 5)
   3.184 +#define __swp_entry(type, offset)	((swp_entry_t){(type) | (offset) << 5})
   3.185 +#define __pte_to_swp_entry(pte)		((swp_entry_t){ (pte).pte_high })
   3.186 +#define __swp_entry_to_pte(x)		((pte_t){ 0, (x).val })
   3.187 +
   3.188 +#define __pmd_free_tlb(tlb, x)		do { } while (0)
   3.189 +
   3.190 +#endif /* _I386_PGTABLE_3LEVEL_H */