1.1 --- a/xen/drivers/ide/ide-pci.c	Wed Dec 24 16:46:32 2003 +0000
     1.2 +++ b/xen/drivers/ide/ide-pci.c	Wed Dec 31 17:44:09 2003 +0000
     1.3 @@ -61,7 +61,7 @@
     1.4  #define DEVID_CMD646	((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_646})
     1.5  #define DEVID_CMD648	((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_648})
     1.6  #define DEVID_CMD649	((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_649})
     1.7 -#define DEVID_CMD680	((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_680})
     1.8 +#define DEVID_CMD680	((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_SII_680})
     1.9  #define DEVID_SIS5513	((ide_pci_devid_t){PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_5513})
    1.10  #define DEVID_OPTI621	((ide_pci_devid_t){PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C621})
    1.11  #define DEVID_OPTI621V	((ide_pci_devid_t){PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C558})
    1.12 @@ -87,7 +87,7 @@
    1.13  #define DEVID_AMD7409	((ide_pci_devid_t){PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_VIPER_7409})
    1.14  #define DEVID_AMD7411	((ide_pci_devid_t){PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_VIPER_7411})
    1.15  #define DEVID_AMD7441	((ide_pci_devid_t){PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_VIPER_7441})
    1.16 -#define DEVID_PDCADMA	((ide_pci_devid_t){PCI_VENDOR_ID_PDC,     PCI_DEVICE_ID_PDC_1841})
    1.17 +#define DEVID_PDCADMA	((ide_pci_devid_t){PCI_VENDOR_ID_PDC,     PCI_DEVICE_ID_PDC_ADMA100})
    1.18  #define DEVID_SLC90E66	((ide_pci_devid_t){PCI_VENDOR_ID_EFAR,    PCI_DEVICE_ID_EFAR_SLC90E66_1})
    1.19  #define DEVID_OSB4	((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE})
    1.20  #define DEVID_CSB5	((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE})

     2.1 --- a/xen/drivers/net/tg3.c	Wed Dec 24 16:46:32 2003 +0000
     2.2 +++ b/xen/drivers/net/tg3.c	Wed Dec 31 17:44:09 2003 +0000
     2.3 @@ -1,17 +1,18 @@
     2.4  /*
     2.5   * tg3.c: Broadcom Tigon3 ethernet driver.
     2.6   *
     2.7 - * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
     2.8 - * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@pobox.com)
     2.9 + * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com)
    2.10 + * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
    2.11   */
    2.12  
    2.13  #include <linux/config.h>
    2.14  
    2.15  #include <linux/module.h>
    2.16  
    2.17 -#include <linux/lib.h>
    2.18 +#include <linux/kernel.h>
    2.19  #include <linux/types.h>
    2.20 -#include <linux/tqueue.h>
    2.21 +#include <linux/tqueue.h> // Xen
    2.22 +#include <linux/compiler.h>
    2.23  #include <linux/slab.h>
    2.24  #include <linux/delay.h>
    2.25  #include <linux/init.h>
    2.26 @@ -23,14 +24,20 @@
    2.27  #include <linux/ethtool.h>
    2.28  #include <linux/mii.h>
    2.29  #include <linux/if_vlan.h>
    2.30 +//#include <linux/ip.h>
    2.31 +//#include <linux/tcp.h>
    2.32 +
    2.33 +//#include <net/checksum.h>
    2.34  
    2.35  #include <asm/system.h>
    2.36  #include <asm/io.h>
    2.37  #include <asm/byteorder.h>
    2.38  #include <asm/uaccess.h>
    2.39  
    2.40 -#ifndef PCI_DMA_BUS_IS_PHYS
    2.41 -#define PCI_DMA_BUS_IS_PHYS 1
    2.42 +#ifdef CONFIG_SPARC64
    2.43 +#include <asm/idprom.h>
    2.44 +#include <asm/oplib.h>
    2.45 +#include <asm/pbm.h>
    2.46  #endif
    2.47  
    2.48  #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
    2.49 @@ -40,18 +47,17 @@
    2.50  #endif
    2.51  
    2.52  #ifdef NETIF_F_TSO
    2.53 -/* XXX some bug in tso firmware hangs tx cpu, disabled until fixed */
    2.54 -#define TG3_DO_TSO	0
    2.55 +#define TG3_TSO_SUPPORT	1
    2.56  #else
    2.57 -#define TG3_DO_TSO	0
    2.58 +#define TG3_TSO_SUPPORT	0
    2.59  #endif
    2.60  
    2.61  #include "tg3.h"
    2.62  
    2.63  #define DRV_MODULE_NAME		"tg3"
    2.64  #define PFX DRV_MODULE_NAME	": "
    2.65 -#define DRV_MODULE_VERSION	"1.4c"
    2.66 -#define DRV_MODULE_RELDATE	"Feb 18, 2003"
    2.67 +#define DRV_MODULE_VERSION	"2.3"
    2.68 +#define DRV_MODULE_RELDATE	"November 5, 2003"
    2.69  
    2.70  #define TG3_DEF_MAC_MODE	0
    2.71  #define TG3_DEF_RX_MODE		0
    2.72 @@ -73,7 +79,8 @@
    2.73  
    2.74  /* hardware minimum and maximum for a single frame's data payload */
    2.75  #define TG3_MIN_MTU			60
    2.76 -#define TG3_MAX_MTU			9000
    2.77 +#define TG3_MAX_MTU(tp)	\
    2.78 +	(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 ? 9000 : 1500)
    2.79  
    2.80  /* These numbers seem to be hard coded in the NIC firmware somehow.
    2.81   * You can't change the ring sizes, but you can change where you place
    2.82 @@ -83,7 +90,17 @@
    2.83  #define TG3_DEF_RX_RING_PENDING		200
    2.84  #define TG3_RX_JUMBO_RING_SIZE		256
    2.85  #define TG3_DEF_RX_JUMBO_RING_PENDING	100
    2.86 -#define TG3_RX_RCB_RING_SIZE		1024
    2.87 +
    2.88 +/* Do not place this n-ring entries value into the tp struct itself,
    2.89 + * we really want to expose these constants to GCC so that modulo et
    2.90 + * al.  operations are done with shifts and masks instead of with
    2.91 + * hw multiply/modulo instructions.  Another solution would be to
    2.92 + * replace things like '% foo' with '& (foo - 1)'.
    2.93 + */
    2.94 +#define TG3_RX_RCB_RING_SIZE(tp)	\
    2.95 +	(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
    2.96 +	 512 : 1024)
    2.97 +
    2.98  #define TG3_TX_RING_SIZE		512
    2.99  #define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
   2.100  
   2.101 @@ -91,8 +108,8 @@
   2.102  				 TG3_RX_RING_SIZE)
   2.103  #define TG3_RX_JUMBO_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
   2.104  			         TG3_RX_JUMBO_RING_SIZE)
   2.105 -#define TG3_RX_RCB_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
   2.106 -			         TG3_RX_RCB_RING_SIZE)
   2.107 +#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
   2.108 +			           TG3_RX_RCB_RING_SIZE(tp))
   2.109  #define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
   2.110  				 TG3_TX_RING_SIZE)
   2.111  #define TX_RING_GAP(TP)	\
   2.112 @@ -120,7 +137,7 @@ MODULE_PARM_DESC(tg3_debug, "Tigon3 bitm
   2.113  
   2.114  static int tg3_debug = -1;	/* -1 == use TG3_DEF_MSG_ENABLE as value */
   2.115  
   2.116 -static struct pci_device_id tg3_pci_tbl[] __devinitdata = {
   2.117 +static struct pci_device_id tg3_pci_tbl[] = {
   2.118  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
   2.119  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.120  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
   2.121 @@ -133,6 +150,14 @@ static struct pci_device_id tg3_pci_tbl[
   2.122  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.123  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
   2.124  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.125 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
   2.126 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.127 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
   2.128 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.129 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
   2.130 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.131 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
   2.132 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.133  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
   2.134  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.135  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
   2.136 @@ -143,10 +168,24 @@ static struct pci_device_id tg3_pci_tbl[
   2.137  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.138  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
   2.139  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.140 -	{ PCI_VENDOR_ID_SYSKONNECT, 0x4400,
   2.141 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
   2.142 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.143 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
   2.144 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.145 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
   2.146 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.147 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
   2.148 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.149 +	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
   2.150 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.151 +	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
   2.152  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.153  	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
   2.154  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.155 +	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
   2.156 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.157 +	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
   2.158 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.159  	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
   2.160  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
   2.161  	{ 0, }
   2.162 @@ -228,39 +267,13 @@ static void tg3_enable_ints(struct tg3 *
   2.163  	tg3_cond_int(tp);
   2.164  }
   2.165  
   2.166 -#ifdef NAPI
   2.167 -/* these netif_xxx funcs should be moved into generic net layer */
   2.168 -static void netif_poll_disable(struct net_device *dev)
   2.169 -{
   2.170 -	while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
   2.171 -		current->state = TASK_INTERRUPTIBLE;
   2.172 -		schedule_timeout(1);
   2.173 -	}
   2.174 -}
   2.175 -
   2.176 -static inline void netif_poll_enable(struct net_device *dev)
   2.177 -{
   2.178 -	clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
   2.179 -}
   2.180 -
   2.181 -/* same as netif_rx_complete, except that local_irq_save(flags)
   2.182 - * has already been issued
   2.183 - */
   2.184 -static inline void __netif_rx_complete(struct net_device *dev)
   2.185 -{
   2.186 -	if (!test_bit(__LINK_STATE_RX_SCHED, &dev->state)) BUG();
   2.187 -	list_del(&dev->poll_list);
   2.188 -	clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
   2.189 -}
   2.190 -#endif
   2.191 -
   2.192  static inline void netif_tx_disable(struct net_device *dev)
   2.193  {
   2.194 -	spin_lock_bh(&dev->xmit_lock);
   2.195 -	netif_stop_queue(dev);
   2.196 -	spin_unlock_bh(&dev->xmit_lock);
   2.197 +        spin_lock_bh(&dev->xmit_lock);
   2.198 +        netif_stop_queue(dev);
   2.199 +        spin_unlock_bh(&dev->xmit_lock);
   2.200  }
   2.201 -
   2.202 +                                                                                
   2.203  static inline void tg3_netif_stop(struct tg3 *tp)
   2.204  {
   2.205  #ifdef NAPI
   2.206 @@ -284,17 +297,28 @@ static inline void tg3_netif_start(struc
   2.207  
   2.208  static void tg3_switch_clocks(struct tg3 *tp)
   2.209  {
   2.210 -	if (tr32(TG3PCI_CLOCK_CTRL) & CLOCK_CTRL_44MHZ_CORE) {
   2.211 +	u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
   2.212 +	u32 orig_clock_ctrl;
   2.213 +
   2.214 +	orig_clock_ctrl = clock_ctrl;
   2.215 +	clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
   2.216 +		       CLOCK_CTRL_CLKRUN_OENABLE |
   2.217 +		       0x1f);
   2.218 +	tp->pci_clock_ctrl = clock_ctrl;
   2.219 +
   2.220 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
   2.221 +	    (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
   2.222  		tw32(TG3PCI_CLOCK_CTRL,
   2.223 +		     clock_ctrl |
   2.224  		     (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
   2.225  		tr32(TG3PCI_CLOCK_CTRL);
   2.226  		udelay(40);
   2.227  		tw32(TG3PCI_CLOCK_CTRL,
   2.228 -		     (CLOCK_CTRL_ALTCLK));
   2.229 +		     clock_ctrl | (CLOCK_CTRL_ALTCLK));
   2.230  		tr32(TG3PCI_CLOCK_CTRL);
   2.231  		udelay(40);
   2.232  	}
   2.233 -	tw32(TG3PCI_CLOCK_CTRL, 0);
   2.234 +	tw32(TG3PCI_CLOCK_CTRL, clock_ctrl);
   2.235  	tr32(TG3PCI_CLOCK_CTRL);
   2.236  	udelay(40);
   2.237  }
   2.238 @@ -397,24 +421,22 @@ static int tg3_writephy(struct tg3 *tp, 
   2.239  	return ret;
   2.240  }
   2.241  
   2.242 -/* This will reset the tigon3 PHY if there is no valid
   2.243 - * link unless the FORCE argument is non-zero.
   2.244 - */
   2.245 -static int tg3_phy_reset(struct tg3 *tp, int force)
   2.246 +static void tg3_phy_set_wirespeed(struct tg3 *tp)
   2.247  {
   2.248 -	u32 phy_status, phy_control;
   2.249 -	int err, limit;
   2.250 -
   2.251 -	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
   2.252 -	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
   2.253 -	if (err != 0)
   2.254 -		return -EBUSY;
   2.255 -
   2.256 -	/* If we have link, and not forcing a reset, then nothing
   2.257 -	 * to do.
   2.258 -	 */
   2.259 -	if ((phy_status & BMSR_LSTATUS) != 0 && (force == 0))
   2.260 -		return 0;
   2.261 +	u32 val;
   2.262 +
   2.263 +	if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
   2.264 +		return;
   2.265 +
   2.266 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
   2.267 +	tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
   2.268 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
   2.269 +}
   2.270 +
   2.271 +static int tg3_bmcr_reset(struct tg3 *tp)
   2.272 +{
   2.273 +	u32 phy_control;
   2.274 +	int limit, err;
   2.275  
   2.276  	/* OK, reset it, and poll the BMCR_RESET bit until it
   2.277  	 * clears or we time out.
   2.278 @@ -432,12 +454,303 @@ static int tg3_phy_reset(struct tg3 *tp,
   2.279  
   2.280  		if ((phy_control & BMCR_RESET) == 0) {
   2.281  			udelay(40);
   2.282 -			return 0;
   2.283 +			break;
   2.284  		}
   2.285  		udelay(10);
   2.286  	}
   2.287 -
   2.288 -	return -EBUSY;
   2.289 +	if (limit <= 0)
   2.290 +		return -EBUSY;
   2.291 +
   2.292 +	return 0;
   2.293 +}
   2.294 +
   2.295 +static int tg3_wait_macro_done(struct tg3 *tp)
   2.296 +{
   2.297 +	int limit = 100;
   2.298 +
   2.299 +	while (limit--) {
   2.300 +		u32 tmp32;
   2.301 +
   2.302 +		tg3_readphy(tp, 0x16, &tmp32);
   2.303 +		if ((tmp32 & 0x1000) == 0)
   2.304 +			break;
   2.305 +	}
   2.306 +	if (limit <= 0)
   2.307 +		return -EBUSY;
   2.308 +
   2.309 +	return 0;
   2.310 +}
   2.311 +
   2.312 +static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
   2.313 +{
   2.314 +	static const u32 test_pat[4][6] = {
   2.315 +	{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
   2.316 +	{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
   2.317 +	{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
   2.318 +	{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
   2.319 +	};
   2.320 +	int chan;
   2.321 +
   2.322 +	for (chan = 0; chan < 4; chan++) {
   2.323 +		int i;
   2.324 +
   2.325 +		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
   2.326 +			     (chan * 0x2000) | 0x0200);
   2.327 +		tg3_writephy(tp, 0x16, 0x0002);
   2.328 +
   2.329 +		for (i = 0; i < 6; i++)
   2.330 +			tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
   2.331 +				     test_pat[chan][i]);
   2.332 +
   2.333 +		tg3_writephy(tp, 0x16, 0x0202);
   2.334 +		if (tg3_wait_macro_done(tp)) {
   2.335 +			*resetp = 1;
   2.336 +			return -EBUSY;
   2.337 +		}
   2.338 +
   2.339 +		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
   2.340 +			     (chan * 0x2000) | 0x0200);
   2.341 +		tg3_writephy(tp, 0x16, 0x0082);
   2.342 +		if (tg3_wait_macro_done(tp)) {
   2.343 +			*resetp = 1;
   2.344 +			return -EBUSY;
   2.345 +		}
   2.346 +
   2.347 +		tg3_writephy(tp, 0x16, 0x0802);
   2.348 +		if (tg3_wait_macro_done(tp)) {
   2.349 +			*resetp = 1;
   2.350 +			return -EBUSY;
   2.351 +		}
   2.352 +
   2.353 +		for (i = 0; i < 6; i += 2) {
   2.354 +			u32 low, high;
   2.355 +
   2.356 +			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
   2.357 +			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
   2.358 +			if (tg3_wait_macro_done(tp)) {
   2.359 +				*resetp = 1;
   2.360 +				return -EBUSY;
   2.361 +			}
   2.362 +			low &= 0x7fff;
   2.363 +			high &= 0x000f;
   2.364 +			if (low != test_pat[chan][i] ||
   2.365 +			    high != test_pat[chan][i+1]) {
   2.366 +				tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
   2.367 +				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
   2.368 +				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
   2.369 +
   2.370 +				return -EBUSY;
   2.371 +			}
   2.372 +		}
   2.373 +	}
   2.374 +
   2.375 +	return 0;
   2.376 +}
   2.377 +
   2.378 +static int tg3_phy_reset_chanpat(struct tg3 *tp)
   2.379 +{
   2.380 +	int chan;
   2.381 +
   2.382 +	for (chan = 0; chan < 4; chan++) {
   2.383 +		int i;
   2.384 +
   2.385 +		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
   2.386 +			     (chan * 0x2000) | 0x0200);
   2.387 +		tg3_writephy(tp, 0x16, 0x0002);
   2.388 +		for (i = 0; i < 6; i++)
   2.389 +			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
   2.390 +		tg3_writephy(tp, 0x16, 0x0202);
   2.391 +		if (tg3_wait_macro_done(tp))
   2.392 +			return -EBUSY;
   2.393 +	}
   2.394 +
   2.395 +	return 0;
   2.396 +}
   2.397 +
   2.398 +static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
   2.399 +{
   2.400 +	u32 reg32, phy9_orig;
   2.401 +	int retries, do_phy_reset, err;
   2.402 +
   2.403 +	retries = 10;
   2.404 +	do_phy_reset = 1;
   2.405 +	do {
   2.406 +		if (do_phy_reset) {
   2.407 +			err = tg3_bmcr_reset(tp);
   2.408 +			if (err)
   2.409 +				return err;
   2.410 +			do_phy_reset = 0;
   2.411 +		}
   2.412 +
   2.413 +		/* Disable transmitter and interrupt.  */
   2.414 +		tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
   2.415 +		reg32 |= 0x3000;
   2.416 +		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
   2.417 +
   2.418 +		/* Set full-duplex, 1000 mbps.  */
   2.419 +		tg3_writephy(tp, MII_BMCR,
   2.420 +			     BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
   2.421 +
   2.422 +		/* Set to master mode.  */
   2.423 +		tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
   2.424 +		tg3_writephy(tp, MII_TG3_CTRL,
   2.425 +			     (MII_TG3_CTRL_AS_MASTER |
   2.426 +			      MII_TG3_CTRL_ENABLE_AS_MASTER));
   2.427 +
   2.428 +		/* Enable SM_DSP_CLOCK and 6dB.  */
   2.429 +		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
   2.430 +
   2.431 +		/* Block the PHY control access.  */
   2.432 +		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
   2.433 +		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
   2.434 +
   2.435 +		err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
   2.436 +		if (!err)
   2.437 +			break;
   2.438 +	} while (--retries);
   2.439 +
   2.440 +	err = tg3_phy_reset_chanpat(tp);
   2.441 +	if (err)
   2.442 +		return err;
   2.443 +
   2.444 +	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
   2.445 +	tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
   2.446 +
   2.447 +	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
   2.448 +	tg3_writephy(tp, 0x16, 0x0000);
   2.449 +
   2.450 +	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
   2.451 +
   2.452 +	tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
   2.453 +
   2.454 +	tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
   2.455 +	reg32 &= ~0x3000;
   2.456 +	tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
   2.457 +
   2.458 +	return err;
   2.459 +}
   2.460 +
   2.461 +/* This will reset the tigon3 PHY if there is no valid
   2.462 + * link unless the FORCE argument is non-zero.
   2.463 + */
   2.464 +static int tg3_phy_reset(struct tg3 *tp, int force)
   2.465 +{
   2.466 +	u32 phy_status;
   2.467 +	int err;
   2.468 +
   2.469 +	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
   2.470 +	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
   2.471 +	if (err != 0)
   2.472 +		return -EBUSY;
   2.473 +
   2.474 +	/* If we have link, and not forcing a reset, then nothing
   2.475 +	 * to do.
   2.476 +	 */
   2.477 +	if ((phy_status & BMSR_LSTATUS) != 0 && (force == 0))
   2.478 +		return 0;
   2.479 +
   2.480 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
   2.481 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
   2.482 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
   2.483 +		err = tg3_phy_reset_5703_4_5(tp);
   2.484 +		if (err)
   2.485 +			return err;
   2.486 +		goto out;
   2.487 +	}
   2.488 +
   2.489 +	err = tg3_bmcr_reset(tp);
   2.490 +	if (err)
   2.491 +		return err;
   2.492 +
   2.493 +out:
   2.494 +	tg3_phy_set_wirespeed(tp);
   2.495 +	return 0;
   2.496 +}
   2.497 +
   2.498 +static void tg3_frob_aux_power(struct tg3 *tp)
   2.499 +{
   2.500 +	struct tg3 *tp_peer = tp;
   2.501 +
   2.502 +	if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
   2.503 +		return;
   2.504 +
   2.505 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
   2.506 +		tp_peer = pci_get_drvdata(tp->pdev_peer);
   2.507 +		if (!tp_peer)
   2.508 +			BUG();
   2.509 +	}
   2.510 +
   2.511 +
   2.512 +	if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
   2.513 +	    (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
   2.514 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.515 +		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
   2.516 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.517 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.518 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.519 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.520 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.521 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.522 +			tr32(GRC_LOCAL_CTRL);
   2.523 +			udelay(100);
   2.524 +		} else {
   2.525 +			if (tp_peer != tp &&
   2.526 +			    (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
   2.527 +				return;
   2.528 +
   2.529 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.530 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.531 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.532 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.533 +			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.534 +			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.535 +			tr32(GRC_LOCAL_CTRL);
   2.536 +			udelay(100);
   2.537 +
   2.538 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.539 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.540 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.541 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.542 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.543 +			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.544 +			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.545 +			tr32(GRC_LOCAL_CTRL);
   2.546 +			udelay(100);
   2.547 +
   2.548 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.549 +			     (GRC_LCLCTRL_GPIO_OE0 |
   2.550 +			      GRC_LCLCTRL_GPIO_OE1 |
   2.551 +			      GRC_LCLCTRL_GPIO_OE2 |
   2.552 +			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.553 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.554 +			tr32(GRC_LOCAL_CTRL);
   2.555 +			udelay(100);
   2.556 +		}
   2.557 +	} else {
   2.558 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
   2.559 +		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
   2.560 +			if (tp_peer != tp &&
   2.561 +			    (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
   2.562 +				return;
   2.563 +
   2.564 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.565 +			     (GRC_LCLCTRL_GPIO_OE1 |
   2.566 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.567 +			tr32(GRC_LOCAL_CTRL);
   2.568 +			udelay(100);
   2.569 +
   2.570 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.571 +			     (GRC_LCLCTRL_GPIO_OE1));
   2.572 +			tr32(GRC_LOCAL_CTRL);
   2.573 +			udelay(100);
   2.574 +
   2.575 +			tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
   2.576 +			     (GRC_LCLCTRL_GPIO_OE1 |
   2.577 +			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.578 +			tr32(GRC_LOCAL_CTRL);
   2.579 +			udelay(100);
   2.580 +		}
   2.581 +	}
   2.582  }
   2.583  
   2.584  static int tg3_setup_phy(struct tg3 *);
   2.585 @@ -543,88 +856,64 @@ static int tg3_set_power_state(struct tg
   2.586  		udelay(10);
   2.587  	}
   2.588  
   2.589 -	if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) {
   2.590 +	if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
   2.591 +	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.592 +	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
   2.593  		u32 base_val;
   2.594  
   2.595 -		base_val = 0;
   2.596 -		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.597 -		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
   2.598 -			base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
   2.599 -				     CLOCK_CTRL_TXCLK_DISABLE);
   2.600 -
   2.601 -		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.602 -		     CLOCK_CTRL_ALTCLK);
   2.603 -		tr32(TG3PCI_CLOCK_CTRL);
   2.604 -		udelay(40);
   2.605 -
   2.606 -		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.607 -		     CLOCK_CTRL_ALTCLK |
   2.608 -		     CLOCK_CTRL_44MHZ_CORE);
   2.609 -		tr32(TG3PCI_CLOCK_CTRL);
   2.610 -		udelay(40);
   2.611 -
   2.612 -		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.613 -		     CLOCK_CTRL_44MHZ_CORE);
   2.614 -		tr32(TG3PCI_CLOCK_CTRL);
   2.615 -		udelay(40);
   2.616 -	} else {
   2.617 -		u32 base_val;
   2.618 -
   2.619 -		base_val = 0;
   2.620 -		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.621 -		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
   2.622 -			base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
   2.623 -				     CLOCK_CTRL_TXCLK_DISABLE);
   2.624 +		base_val = tp->pci_clock_ctrl;
   2.625 +		base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
   2.626 +			     CLOCK_CTRL_TXCLK_DISABLE);
   2.627  
   2.628  		tw32(TG3PCI_CLOCK_CTRL, base_val |
   2.629  		     CLOCK_CTRL_ALTCLK |
   2.630  		     CLOCK_CTRL_PWRDOWN_PLL133);
   2.631  		tr32(TG3PCI_CLOCK_CTRL);
   2.632  		udelay(40);
   2.633 -	}
   2.634 -
   2.635 -	if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) &&
   2.636 -	    (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
   2.637 +	} else {
   2.638 +		u32 newbits1, newbits2;
   2.639 +
   2.640  		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.641  		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
   2.642 -			tw32(GRC_LOCAL_CTRL,
   2.643 -			     (GRC_LCLCTRL_GPIO_OE0 |
   2.644 -			      GRC_LCLCTRL_GPIO_OE1 |
   2.645 -			      GRC_LCLCTRL_GPIO_OE2 |
   2.646 -			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.647 -			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.648 -			tr32(GRC_LOCAL_CTRL);
   2.649 -			udelay(100);
   2.650 +			newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
   2.651 +				    CLOCK_CTRL_TXCLK_DISABLE |
   2.652 +				    CLOCK_CTRL_ALTCLK);
   2.653 +			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
   2.654 +		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
   2.655 +			newbits1 = CLOCK_CTRL_625_CORE;
   2.656 +			newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
   2.657  		} else {
   2.658 -			tw32(GRC_LOCAL_CTRL,
   2.659 -			     (GRC_LCLCTRL_GPIO_OE0 |
   2.660 -			      GRC_LCLCTRL_GPIO_OE1 |
   2.661 -			      GRC_LCLCTRL_GPIO_OE2 |
   2.662 -			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.663 -			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.664 -			tr32(GRC_LOCAL_CTRL);
   2.665 -			udelay(100);
   2.666 -
   2.667 -			tw32(GRC_LOCAL_CTRL,
   2.668 -			     (GRC_LCLCTRL_GPIO_OE0 |
   2.669 -			      GRC_LCLCTRL_GPIO_OE1 |
   2.670 -			      GRC_LCLCTRL_GPIO_OE2 |
   2.671 -			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.672 -			      GRC_LCLCTRL_GPIO_OUTPUT1 |
   2.673 -			      GRC_LCLCTRL_GPIO_OUTPUT2));
   2.674 -			tr32(GRC_LOCAL_CTRL);
   2.675 -			udelay(100);
   2.676 -
   2.677 -			tw32(GRC_LOCAL_CTRL,
   2.678 -			     (GRC_LCLCTRL_GPIO_OE0 |
   2.679 -			      GRC_LCLCTRL_GPIO_OE1 |
   2.680 -			      GRC_LCLCTRL_GPIO_OE2 |
   2.681 -			      GRC_LCLCTRL_GPIO_OUTPUT0 |
   2.682 -			      GRC_LCLCTRL_GPIO_OUTPUT1));
   2.683 -			tr32(GRC_LOCAL_CTRL);
   2.684 -			udelay(100);
   2.685 +			newbits1 = CLOCK_CTRL_ALTCLK;
   2.686 +			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
   2.687  		}
   2.688 -	}
   2.689 +
   2.690 +		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
   2.691 +		tr32(TG3PCI_CLOCK_CTRL);
   2.692 +		udelay(40);
   2.693 +
   2.694 +		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
   2.695 +		tr32(TG3PCI_CLOCK_CTRL);
   2.696 +		udelay(40);
   2.697 +
   2.698 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
   2.699 +			u32 newbits3;
   2.700 +
   2.701 +			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   2.702 +			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
   2.703 +				newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
   2.704 +					    CLOCK_CTRL_TXCLK_DISABLE |
   2.705 +					    CLOCK_CTRL_44MHZ_CORE);
   2.706 +			} else {
   2.707 +				newbits3 = CLOCK_CTRL_44MHZ_CORE;
   2.708 +			}
   2.709 +
   2.710 +			tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits3);
   2.711 +			tr32(TG3PCI_CLOCK_CTRL);
   2.712 +			udelay(40);
   2.713 +		}
   2.714 +	}
   2.715 +
   2.716 +	tg3_frob_aux_power(tp);
   2.717  
   2.718  	/* Finally, set the new power state. */
   2.719  	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
   2.720 @@ -944,11 +1233,10 @@ static int tg3_setup_copper_phy(struct t
   2.721  
   2.722  	/* Some third-party PHYs need to be reset on link going
   2.723  	 * down.
   2.724 -	 *
   2.725 -	 * XXX 5705 note: This workaround also applies to 5705_a0
   2.726  	 */
   2.727  	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
   2.728 -	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
   2.729 +	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
   2.730 +	     tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) &&
   2.731  	    netif_carrier_ok(tp->dev)) {
   2.732  		tg3_readphy(tp, MII_BMSR, &bmsr);
   2.733  		tg3_readphy(tp, MII_BMSR, &bmsr);
   2.734 @@ -1752,7 +2040,7 @@ static void tg3_tx(struct tg3 *tp)
   2.735  
   2.736  		pci_unmap_single(tp->pdev,
   2.737  				 pci_unmap_addr(ri, mapping),
   2.738 -				 (skb->len - skb->data_len),
   2.739 +				 skb_headlen(skb),
   2.740  				 PCI_DMA_TODEVICE);
   2.741  
   2.742  		ri->skb = NULL;
   2.743 @@ -1923,7 +2211,7 @@ static int tg3_vlan_rx(struct tg3 *tp, s
   2.744   * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
   2.745   * which is within the range of the new packet's length is chosen.
   2.746   *
   2.747 - * The "seperate ring for rx status" scheme may sound queer, but it makes
   2.748 + * The "separate ring for rx status" scheme may sound queer, but it makes
   2.749   * sense from a cache coherency perspective.  If only the host writes
   2.750   * to the buffer post rings, and only the chip writes to the rx status
   2.751   * rings, then cache lines never move beyond shared-modified state.
   2.752 @@ -1938,7 +2226,7 @@ static int tg3_rx(struct tg3 *tp, int bu
   2.753  	int received;
   2.754  
   2.755  	hw_idx = tp->hw_status->idx[0].rx_producer;
   2.756 -	sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE;
   2.757 +	sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
   2.758  	work_mask = 0;
   2.759  	received = 0;
   2.760  	while (sw_idx != hw_idx && budget > 0) {
   2.761 @@ -2042,13 +2330,13 @@ next_pkt:
   2.762  		(*post_ptr)++;
   2.763  next_pkt_nopost:
   2.764  		rx_rcb_ptr++;
   2.765 -		sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE;
   2.766 +		sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
   2.767  	}
   2.768  
   2.769  	/* ACK the status ring. */
   2.770  	tp->rx_rcb_ptr = rx_rcb_ptr;
   2.771  	tw32_mailbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
   2.772 -		     (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE));
   2.773 +		     (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
   2.774  	if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
   2.775  		tr32(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW);
   2.776  
   2.777 @@ -2076,11 +2364,12 @@ static int tg3_poll(struct net_device *n
   2.778  	struct tg3 *tp = netdev->priv;
   2.779  	struct tg3_hw_status *sblk = tp->hw_status;
   2.780  	int done;
   2.781 +
   2.782  #ifdef NAPI
   2.783  	unsigned long flags;
   2.784 +
   2.785  	spin_lock_irqsave(&tp->lock, flags);
   2.786  #endif
   2.787 -
   2.788  	/* handle link change and other phy events */
   2.789  	if (!(tp->tg3_flags &
   2.790  	      (TG3_FLAG_USE_LINKCHG_REG |
   2.791 @@ -2098,11 +2387,9 @@ static int tg3_poll(struct net_device *n
   2.792  		tg3_tx(tp);
   2.793  		spin_unlock(&tp->tx_lock);
   2.794  	}
   2.795 -
   2.796  #ifdef NAPI
   2.797  	spin_unlock_irqrestore(&tp->lock, flags);
   2.798  #endif
   2.799 -
   2.800  	/* run RX thread, within the bounds set by NAPI.
   2.801  	 * All RX "locking" is done by ensuring outside
   2.802  	 * code synchronizes with dev->poll()
   2.803 @@ -2159,14 +2446,13 @@ static inline unsigned int tg3_has_work(
   2.804  	return work_exists;
   2.805  }
   2.806  
   2.807 -static void tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
   2.808 +static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
   2.809  {
   2.810  	struct net_device *dev = dev_id;
   2.811  	struct tg3 *tp = dev->priv;
   2.812 -#ifdef NAPI
   2.813  	struct tg3_hw_status *sblk = tp->hw_status;
   2.814 -#endif
   2.815  	unsigned long flags;
   2.816 +	unsigned int handled = 1;
   2.817  
   2.818  	spin_lock_irqsave(&tp->lock, flags);
   2.819  #ifdef NAPI
   2.820 @@ -2198,20 +2484,28 @@ static void tg3_interrupt(int irq, void 
   2.821  			tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   2.822  		}
   2.823  	}
   2.824 +	else {        /* shared interrupt */
   2.825 +                handled = 0;
   2.826 +        } 
   2.827  #else
   2.828 -	{
   2.829 -		int budget = 1000;
   2.830 -		tg3_poll( dev, &budget );
   2.831 -
   2.832 -		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   2.833 -		       0x00000000);
   2.834 -		tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   2.835 +	if (sblk->status & SD_STATUS_UPDATED) {
   2.836 +                int budget = 1000;
   2.837 +                tg3_poll( dev, &budget );
   2.838 +                                                                                
   2.839 +                tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   2.840 +                       0x00000000);
   2.841 +                tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   2.842 +        }
   2.843 +	else {	      /* shared interrupt */
   2.844 +		handled = 0;
   2.845  	}
   2.846  #endif
   2.847 +
   2.848  	spin_unlock_irqrestore(&tp->lock, flags);
   2.849 +
   2.850 +	return IRQ_RETVAL(handled);
   2.851  }
   2.852  
   2.853 -static void tg3_init_rings(struct tg3 *);
   2.854  static int tg3_init_hw(struct tg3 *);
   2.855  static int tg3_halt(struct tg3 *);
   2.856  
   2.857 @@ -2229,7 +2523,6 @@ static void tg3_reset_task(void *_data)
   2.858  	tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
   2.859  
   2.860  	tg3_halt(tp);
   2.861 -	tg3_init_rings(tp);
   2.862  	tg3_init_hw(tp);
   2.863  
   2.864  	spin_unlock(&tp->tx_lock);
   2.865 @@ -2243,97 +2536,32 @@ static void tg3_reset_task(void *_data)
   2.866  
   2.867  static void tg3_tx_timeout(struct net_device *dev)
   2.868  {
   2.869 -        struct tg3 *tp = dev->priv;
   2.870 -
   2.871 -        printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
   2.872 -               dev->name);
   2.873 -
   2.874 -        spin_lock_irq(&tp->lock);
   2.875 -        spin_lock(&tp->tx_lock);
   2.876 -
   2.877 -        tg3_halt(tp);
   2.878 -        tg3_init_rings(tp);
   2.879 -        tg3_init_hw(tp);
   2.880 -
   2.881 -        spin_unlock(&tp->tx_lock);
   2.882 -        spin_unlock_irq(&tp->lock);
   2.883 -
   2.884 -        netif_wake_queue(dev);
   2.885 +	struct tg3 *tp = dev->priv;
   2.886 +
   2.887 +	printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
   2.888 +	       dev->name);
   2.889 +
   2.890 +	//schedule_task(&tp->reset_task);
   2.891 +	tg3_reset_task(tp);
   2.892  }
   2.893  
   2.894 -#if !PCI_DMA_BUS_IS_PHYS
   2.895 -static void tg3_set_txd_addr(struct tg3 *tp, int entry, dma_addr_t mapping)
   2.896 -{
   2.897 -	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
   2.898 -		struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
   2.899 -
   2.900 -		txd->addr_hi = ((u64) mapping >> 32);
   2.901 -		txd->addr_lo = ((u64) mapping & 0xffffffff);
   2.902 -	} else {
   2.903 -		unsigned long txd;
   2.904 -
   2.905 -		txd = (tp->regs +
   2.906 -		       NIC_SRAM_WIN_BASE +
   2.907 -		       NIC_SRAM_TX_BUFFER_DESC);
   2.908 -		txd += (entry * TXD_SIZE);
   2.909 -
   2.910 -		if (sizeof(dma_addr_t) != sizeof(u32))
   2.911 -			writel(((u64) mapping >> 32),
   2.912 -			       txd + TXD_ADDR + TG3_64BIT_REG_HIGH);
   2.913 -
   2.914 -		writel(((u64) mapping & 0xffffffff),
   2.915 -		       txd + TXD_ADDR + TG3_64BIT_REG_LOW);
   2.916 -	}
   2.917 -}
   2.918 -#endif
   2.919 -
   2.920  static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
   2.921  
   2.922  static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
   2.923  				       u32 guilty_entry, int guilty_len,
   2.924  				       u32 last_plus_one, u32 *start, u32 mss)
   2.925  {
   2.926 +	struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
   2.927  	dma_addr_t new_addr;
   2.928  	u32 entry = *start;
   2.929  	int i;
   2.930  
   2.931 -#if !PCI_DMA_BUS_IS_PHYS
   2.932 -	/* IOMMU, just map the guilty area again which is guarenteed to
   2.933 -	 * use different addresses.
   2.934 -	 */
   2.935 -
   2.936 -	i = 0;
   2.937 -	while (entry != guilty_entry) {
   2.938 -		entry = NEXT_TX(entry);
   2.939 -		i++;
   2.940 -	}
   2.941 -	if (i == 0) {
   2.942 -		new_addr = pci_map_single(tp->pdev, skb->data, guilty_len,
   2.943 -					  PCI_DMA_TODEVICE);
   2.944 -	} else {
   2.945 -		skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
   2.946 -
   2.947 -		new_addr = pci_map_page(tp->pdev,
   2.948 -					frag->page, frag->page_offset,
   2.949 -					guilty_len, PCI_DMA_TODEVICE);
   2.950 -	}
   2.951 -	pci_unmap_single(tp->pdev, pci_unmap_addr(&tp->tx_buffers[guilty_entry],
   2.952 -						  mapping),
   2.953 -			 guilty_len, PCI_DMA_TODEVICE);
   2.954 -	tg3_set_txd_addr(tp, guilty_entry, new_addr);
   2.955 -	pci_unmap_addr_set(&tp->tx_buffers[guilty_entry], mapping,
   2.956 -			   new_addr);
   2.957 -	*start = last_plus_one;
   2.958 -#else
   2.959 -	/* Oh well, no IOMMU, have to allocate a whole new SKB. */
   2.960 -	struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
   2.961 -
   2.962  	if (!new_skb) {
   2.963  		dev_kfree_skb(skb);
   2.964  		return -1;
   2.965  	}
   2.966  
   2.967 -	/* New SKB is guarenteed to be linear. */
   2.968 +	/* New SKB is guaranteed to be linear. */
   2.969  	entry = *start;
   2.970  	new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
   2.971  				  PCI_DMA_TODEVICE);
   2.972 @@ -2348,7 +2576,7 @@ static int tigon3_4gb_hwbug_workaround(s
   2.973  		int len;
   2.974  
   2.975  		if (i == 0)
   2.976 -			len = skb->len - skb->data_len;
   2.977 +			len = skb_headlen(skb);
   2.978  		else
   2.979  			len = skb_shinfo(skb)->frags[i-1].size;
   2.980  		pci_unmap_single(tp->pdev,
   2.981 @@ -2364,7 +2592,6 @@ static int tigon3_4gb_hwbug_workaround(s
   2.982  	}
   2.983  
   2.984  	dev_kfree_skb(skb);
   2.985 -#endif
   2.986  
   2.987  	return 0;
   2.988  }
   2.989 @@ -2433,7 +2660,7 @@ static int tg3_start_xmit_4gbug(struct s
   2.990  	int would_hit_hwbug;
   2.991  	unsigned long flags;
   2.992  
   2.993 -	len = (skb->len - skb->data_len);
   2.994 +	len = skb_headlen(skb);
   2.995  
   2.996  	/* No BH disabling for tx_lock here.  We are running in BH disabled
   2.997  	 * context and TX reclaim runs via tp->poll inside of a software
   2.998 @@ -2469,10 +2696,36 @@ static int tg3_start_xmit_4gbug(struct s
   2.999  	base_flags = 0;
  2.1000  	if (skb->ip_summed == CHECKSUM_HW)
  2.1001  		base_flags |= TXD_FLAG_TCPUDP_CSUM;
  2.1002 -#if TG3_DO_TSO != 0
  2.1003 -	if ((mss = skb_shinfo(skb)->tso_size) != 0)
  2.1004 +#if TG3_TSO_SUPPORT != 0
  2.1005 +	mss = 0;
  2.1006 +	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
  2.1007 +	    (mss = skb_shinfo(skb)->tso_size) != 0) {
  2.1008 +		int tcp_opt_len, ip_tcp_len;
  2.1009 +
  2.1010 +		tcp_opt_len = ((skb->h.th->doff - 5) * 4);
  2.1011 +		ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  2.1012 +
  2.1013  		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  2.1014  			       TXD_FLAG_CPU_POST_DMA);
  2.1015 +
  2.1016 +		skb->nh.iph->check = 0;
  2.1017 +		skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
  2.1018 +		skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
  2.1019 +						      skb->nh.iph->daddr,
  2.1020 +						      0, IPPROTO_TCP, 0);
  2.1021 +
  2.1022 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.1023 +			if (tcp_opt_len || skb->nh.iph->ihl > 5) {
  2.1024 +				int tsflags;
  2.1025 +
  2.1026 +				tsflags = ((skb->nh.iph->ihl - 5) +
  2.1027 +					   (tcp_opt_len >> 2));
  2.1028 +				mss |= (tsflags << 11);
  2.1029 +			}
  2.1030 +		} else {
  2.1031 +			mss += tcp_opt_len;
  2.1032 +		}
  2.1033 +	}
  2.1034  #else
  2.1035  	mss = 0;
  2.1036  #endif
  2.1037 @@ -2523,7 +2776,7 @@ static int tg3_start_xmit_4gbug(struct s
  2.1038  			}
  2.1039  
  2.1040  			tg3_set_txd(tp, entry, mapping, len,
  2.1041 -				    base_flags, (i == last) | (mss << 1));
  2.1042 +				    base_flags, (i == last));
  2.1043  
  2.1044  			entry = NEXT_TX(entry);
  2.1045  		}
  2.1046 @@ -2541,7 +2794,7 @@ static int tg3_start_xmit_4gbug(struct s
  2.1047  		i = 0;
  2.1048  		while (entry != last_plus_one) {
  2.1049  			if (i == 0)
  2.1050 -				len = skb->len - skb->data_len;
  2.1051 +				len = skb_headlen(skb);
  2.1052  			else
  2.1053  				len = skb_shinfo(skb)->frags[i-1].size;
  2.1054  
  2.1055 @@ -2614,7 +2867,7 @@ static int tg3_start_xmit(struct sk_buff
  2.1056  	u32 len, entry, base_flags, mss;
  2.1057  	unsigned long flags;
  2.1058  
  2.1059 -	len = (skb->len - skb->data_len);
  2.1060 +	len = skb_headlen(skb);
  2.1061  
  2.1062  	/* No BH disabling for tx_lock here.  We are running in BH disabled
  2.1063  	 * context and TX reclaim runs via tp->poll inside of a software
  2.1064 @@ -2650,10 +2903,36 @@ static int tg3_start_xmit(struct sk_buff
  2.1065  	base_flags = 0;
  2.1066  	if (skb->ip_summed == CHECKSUM_HW)
  2.1067  		base_flags |= TXD_FLAG_TCPUDP_CSUM;
  2.1068 -#if TG3_DO_TSO != 0
  2.1069 -	if ((mss = skb_shinfo(skb)->tso_size) != 0)
  2.1070 +#if TG3_TSO_SUPPORT != 0
  2.1071 +	mss = 0;
  2.1072 +	if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
  2.1073 +	    (mss = skb_shinfo(skb)->tso_size) != 0) {
  2.1074 +		int tcp_opt_len, ip_tcp_len;
  2.1075 +
  2.1076 +		tcp_opt_len = ((skb->h.th->doff - 5) * 4);
  2.1077 +		ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  2.1078 +
  2.1079  		base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  2.1080  			       TXD_FLAG_CPU_POST_DMA);
  2.1081 +
  2.1082 +		skb->nh.iph->check = 0;
  2.1083 +		skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
  2.1084 +		skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
  2.1085 +						      skb->nh.iph->daddr,
  2.1086 +						      0, IPPROTO_TCP, 0);
  2.1087 +
  2.1088 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.1089 +			if (tcp_opt_len || skb->nh.iph->ihl > 5) {
  2.1090 +				int tsflags;
  2.1091 +
  2.1092 +				tsflags = ((skb->nh.iph->ihl - 5) +
  2.1093 +					   (tcp_opt_len >> 2));
  2.1094 +				mss |= (tsflags << 11);
  2.1095 +			}
  2.1096 +		} else {
  2.1097 +			mss += tcp_opt_len;
  2.1098 +		}
  2.1099 +	}
  2.1100  #else
  2.1101  	mss = 0;
  2.1102  #endif
  2.1103 @@ -2693,7 +2972,7 @@ static int tg3_start_xmit(struct sk_buff
  2.1104  			pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  2.1105  
  2.1106  			tg3_set_txd(tp, entry, mapping, len,
  2.1107 -				    base_flags, (i == last) | (mss << 1));
  2.1108 +				    base_flags, (i == last));
  2.1109  
  2.1110  			entry = NEXT_TX(entry);
  2.1111  		}
  2.1112 @@ -2753,7 +3032,7 @@ static int tg3_change_mtu(struct net_dev
  2.1113  {
  2.1114  	struct tg3 *tp = dev->priv;
  2.1115  
  2.1116 -	if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU)
  2.1117 +	if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  2.1118  		return -EINVAL;
  2.1119  
  2.1120  	if (!netif_running(dev)) {
  2.1121 @@ -2772,7 +3051,6 @@ static int tg3_change_mtu(struct net_dev
  2.1122  
  2.1123  	tg3_set_mtu(dev, tp, new_mtu);
  2.1124  
  2.1125 -	tg3_init_rings(tp);
  2.1126  	tg3_init_hw(tp);
  2.1127  
  2.1128  	spin_unlock(&tp->tx_lock);
  2.1129 @@ -2835,7 +3113,7 @@ static void tg3_free_rings(struct tg3 *t
  2.1130  
  2.1131  		pci_unmap_single(tp->pdev,
  2.1132  				 pci_unmap_addr(txp, mapping),
  2.1133 -				 (skb->len - skb->data_len),
  2.1134 +				 skb_headlen(skb),
  2.1135  				 PCI_DMA_TODEVICE);
  2.1136  		txp->skb = NULL;
  2.1137  
  2.1138 @@ -2858,8 +3136,8 @@ static void tg3_free_rings(struct tg3 *t
  2.1139   *
  2.1140   * The chip has been shut down and the driver detached from
  2.1141   * the networking, so no interrupts or new tx packets will
  2.1142 - * end up in the driver.  tp->{tx,}lock is not held and we are not
  2.1143 - * in an interrupt context and thus may sleep.
  2.1144 + * end up in the driver.  tp->{tx,}lock are held and thus
  2.1145 + * we may not sleep.
  2.1146   */
  2.1147  static void tg3_init_rings(struct tg3 *tp)
  2.1148  {
  2.1149 @@ -2872,7 +3150,7 @@ static void tg3_init_rings(struct tg3 *t
  2.1150  	/* Zero out all descriptors. */
  2.1151  	memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  2.1152  	memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  2.1153 -	memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES);
  2.1154 +	memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  2.1155  
  2.1156  	if (tp->tg3_flags & TG3_FLAG_HOST_TXDS) {
  2.1157  		memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  2.1158 @@ -2955,7 +3233,7 @@ static void tg3_free_consistent(struct t
  2.1159  		tp->rx_jumbo = NULL;
  2.1160  	}
  2.1161  	if (tp->rx_rcb) {
  2.1162 -		pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES,
  2.1163 +		pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  2.1164  				    tp->rx_rcb, tp->rx_rcb_mapping);
  2.1165  		tp->rx_rcb = NULL;
  2.1166  	}
  2.1167 @@ -3013,7 +3291,7 @@ static int tg3_alloc_consistent(struct t
  2.1168  	if (!tp->rx_jumbo)
  2.1169  		goto err_out;
  2.1170  
  2.1171 -	tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES,
  2.1172 +	tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  2.1173  					  &tp->rx_rcb_mapping);
  2.1174  	if (!tp->rx_rcb)
  2.1175  		goto err_out;
  2.1176 @@ -3060,6 +3338,23 @@ static int tg3_stop_block(struct tg3 *tp
  2.1177  	unsigned int i;
  2.1178  	u32 val;
  2.1179  
  2.1180 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.1181 +		switch (ofs) {
  2.1182 +		case RCVLSC_MODE:
  2.1183 +		case DMAC_MODE:
  2.1184 +		case MBFREE_MODE:
  2.1185 +		case BUFMGR_MODE:
  2.1186 +		case MEMARB_MODE:
  2.1187 +			/* We can't enable/disable these bits of the
  2.1188 +			 * 5705, just say success.
  2.1189 +			 */
  2.1190 +			return 0;
  2.1191 +
  2.1192 +		default:
  2.1193 +			break;
  2.1194 +		};
  2.1195 +	}
  2.1196 +
  2.1197  	val = tr32(ofs);
  2.1198  	val &= ~enable_bit;
  2.1199  	tw32(ofs, val);
  2.1200 @@ -3106,6 +3401,7 @@ static int tg3_abort_hw(struct tg3 *tp)
  2.1201  	err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  2.1202  	err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
  2.1203  	err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  2.1204 +	err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
  2.1205  	err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
  2.1206  	if (err)
  2.1207  		goto out;
  2.1208 @@ -3155,18 +3451,20 @@ static void tg3_chip_reset(struct tg3 *t
  2.1209  	u32 val;
  2.1210  	u32 flags_save;
  2.1211  
  2.1212 -	/* Force NVRAM to settle.
  2.1213 -	 * This deals with a chip bug which can result in EEPROM
  2.1214 -	 * corruption.
  2.1215 -	 */
  2.1216 -	if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  2.1217 -		int i;
  2.1218 -
  2.1219 -		tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2.1220 -		for (i = 0; i < 100000; i++) {
  2.1221 -			if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2.1222 -				break;
  2.1223 -			udelay(10);
  2.1224 +	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
  2.1225 +		/* Force NVRAM to settle.
  2.1226 +		 * This deals with a chip bug which can result in EEPROM
  2.1227 +		 * corruption.
  2.1228 +		 */
  2.1229 +		if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  2.1230 +			int i;
  2.1231 +
  2.1232 +			tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2.1233 +			for (i = 0; i < 100000; i++) {
  2.1234 +				if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2.1235 +					break;
  2.1236 +				udelay(10);
  2.1237 +			}
  2.1238  		}
  2.1239  	}
  2.1240  
  2.1241 @@ -3180,7 +3478,10 @@ static void tg3_chip_reset(struct tg3 *t
  2.1242  	tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
  2.1243  
  2.1244  	/* do the reset */
  2.1245 -	tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET);
  2.1246 +	val = GRC_MISC_CFG_CORECLK_RESET;
  2.1247 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.1248 +		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  2.1249 +	tw32(GRC_MISC_CFG, val);
  2.1250  
  2.1251  	/* restore 5701 hardware bug workaround flag */
  2.1252  	tp->tg3_flags = flags_save;
  2.1253 @@ -3216,6 +3517,13 @@ static void tg3_chip_reset(struct tg3 *t
  2.1254  
  2.1255  	tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  2.1256  
  2.1257 +	if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  2.1258 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.1259 +		tp->pci_clock_ctrl |=
  2.1260 +			(CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
  2.1261 +		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  2.1262 +	}
  2.1263 +
  2.1264  	tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  2.1265  }
  2.1266  
  2.1267 @@ -3259,7 +3567,8 @@ static int tg3_halt(struct tg3 *tp)
  2.1268  		udelay(10);
  2.1269  	}
  2.1270  
  2.1271 -	if (i >= 100000) {
  2.1272 +	if (i >= 100000 &&
  2.1273 +	    !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
  2.1274  		printk(KERN_ERR PFX "tg3_halt timed out for %s, "
  2.1275  		       "firmware will not restart magic=%08x\n",
  2.1276  		       tp->dev->name, val);
  2.1277 @@ -3397,7 +3706,7 @@ static u32 tg3FwRodata[(TG3_FW_RODATA_LE
  2.1278  	0x00000000
  2.1279  };
  2.1280  
  2.1281 -#if 0 /* All zeros, dont eat up space with it. */
  2.1282 +#if 0 /* All zeros, don't eat up space with it. */
  2.1283  u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  2.1284  	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  2.1285  	0x00000000, 0x00000000, 0x00000000, 0x00000000
  2.1286 @@ -3410,28 +3719,32 @@ u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(
  2.1287  #define TX_CPU_SCRATCH_SIZE	0x04000
  2.1288  
  2.1289  /* tp->lock is held. */
  2.1290 -static int tg3_reset_cpu(struct tg3 *tp, u32 offset)
  2.1291 +static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  2.1292  {
  2.1293  	int i;
  2.1294  
  2.1295 -	tw32(offset + CPU_STATE, 0xffffffff);
  2.1296 -	tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.1297 +	if (offset == TX_CPU_BASE &&
  2.1298 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.1299 +		BUG();
  2.1300 +
  2.1301  	if (offset == RX_CPU_BASE) {
  2.1302 -		for (i = 0; i < 10000; i++)
  2.1303 -			if (!(tr32(offset + CPU_MODE) & CPU_MODE_RESET))
  2.1304 +		for (i = 0; i < 10000; i++) {
  2.1305 +			tw32(offset + CPU_STATE, 0xffffffff);
  2.1306 +			tw32(offset + CPU_MODE,  CPU_MODE_HALT);
  2.1307 +			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2.1308  				break;
  2.1309 +		}
  2.1310 +
  2.1311  		tw32(offset + CPU_STATE, 0xffffffff);
  2.1312 -		tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.1313 +		tw32(offset + CPU_MODE,  CPU_MODE_HALT);
  2.1314  		tr32(offset + CPU_MODE);
  2.1315  		udelay(10);
  2.1316  	} else {
  2.1317  		for (i = 0; i < 10000; i++) {
  2.1318 -			if (!(tr32(offset + CPU_MODE) & CPU_MODE_RESET))
  2.1319 +			tw32(offset + CPU_STATE, 0xffffffff);
  2.1320 +			tw32(offset + CPU_MODE,  CPU_MODE_HALT);
  2.1321 +			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2.1322  				break;
  2.1323 -			tw32(offset + CPU_STATE, 0xffffffff);
  2.1324 -			tw32(offset + CPU_MODE,  CPU_MODE_RESET);
  2.1325 -			tr32(offset + CPU_MODE);
  2.1326 -			udelay(10);
  2.1327  		}
  2.1328  	}
  2.1329  
  2.1330 @@ -3463,38 +3776,52 @@ static int tg3_load_firmware_cpu(struct 
  2.1331  {
  2.1332  	int err, i;
  2.1333  	u32 orig_tg3_flags = tp->tg3_flags;
  2.1334 +	void (*write_op)(struct tg3 *, u32, u32);
  2.1335 +
  2.1336 +	if (cpu_base == TX_CPU_BASE &&
  2.1337 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.1338 +		printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  2.1339 +		       "TX cpu firmware on %s which is 5705.\n",
  2.1340 +		       tp->dev->name);
  2.1341 +		return -EINVAL;
  2.1342 +	}
  2.1343 +
  2.1344 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.1345 +		write_op = tg3_write_mem;
  2.1346 +	else
  2.1347 +		write_op = tg3_write_indirect_reg32;
  2.1348  
  2.1349  	/* Force use of PCI config space for indirect register
  2.1350  	 * write calls.
  2.1351  	 */
  2.1352  	tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  2.1353  
  2.1354 -	err = tg3_reset_cpu(tp, cpu_base);
  2.1355 +	err = tg3_halt_cpu(tp, cpu_base);
  2.1356  	if (err)
  2.1357  		goto out;
  2.1358  
  2.1359  	for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  2.1360 -		tg3_write_indirect_reg32(tp, cpu_scratch_base + i, 0);
  2.1361 +		write_op(tp, cpu_scratch_base + i, 0);
  2.1362  	tw32(cpu_base + CPU_STATE, 0xffffffff);
  2.1363  	tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  2.1364  	for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  2.1365 -		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.1366 -					      (info->text_base & 0xffff) +
  2.1367 -					      (i * sizeof(u32))),
  2.1368 -					 (info->text_data ?
  2.1369 -					  info->text_data[i] : 0));
  2.1370 +		write_op(tp, (cpu_scratch_base +
  2.1371 +			      (info->text_base & 0xffff) +
  2.1372 +			      (i * sizeof(u32))),
  2.1373 +			 (info->text_data ?
  2.1374 +			  info->text_data[i] : 0));
  2.1375  	for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  2.1376 -		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.1377 -					      (info->rodata_base & 0xffff) +
  2.1378 -					      (i * sizeof(u32))),
  2.1379 -					 (info->rodata_data ?
  2.1380 -					  info->rodata_data[i] : 0));
  2.1381 +		write_op(tp, (cpu_scratch_base +
  2.1382 +			      (info->rodata_base & 0xffff) +
  2.1383 +			      (i * sizeof(u32))),
  2.1384 +			 (info->rodata_data ?
  2.1385 +			  info->rodata_data[i] : 0));
  2.1386  	for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  2.1387 -		tg3_write_indirect_reg32(tp, (cpu_scratch_base +
  2.1388 -					      (info->data_base & 0xffff) +
  2.1389 -					      (i * sizeof(u32))),
  2.1390 -					 (info->data_data ?
  2.1391 -					  info->data_data[i] : 0));
  2.1392 +		write_op(tp, (cpu_scratch_base +
  2.1393 +			      (info->data_base & 0xffff) +
  2.1394 +			      (i * sizeof(u32))),
  2.1395 +			 (info->data_data ?
  2.1396 +			  info->data_data[i] : 0));
  2.1397  
  2.1398  	err = 0;
  2.1399  
  2.1400 @@ -3565,335 +3892,595 @@ static int tg3_load_5701_a0_firmware_fix
  2.1401  	return 0;
  2.1402  }
  2.1403  
  2.1404 -#if TG3_DO_TSO != 0
  2.1405 +#if TG3_TSO_SUPPORT != 0
  2.1406  
  2.1407  #define TG3_TSO_FW_RELEASE_MAJOR	0x1
  2.1408 -#define TG3_TSO_FW_RELASE_MINOR		0x8
  2.1409 +#define TG3_TSO_FW_RELASE_MINOR		0x3
  2.1410  #define TG3_TSO_FW_RELEASE_FIX		0x0
  2.1411  #define TG3_TSO_FW_START_ADDR		0x08000000
  2.1412  #define TG3_TSO_FW_TEXT_ADDR		0x08000000
  2.1413 -#define TG3_TSO_FW_TEXT_LEN		0x1650
  2.1414 +#define TG3_TSO_FW_TEXT_LEN		0x1ac0
  2.1415  #define TG3_TSO_FW_RODATA_ADDR		0x08001650
  2.1416 -#define TG3_TSO_FW_RODATA_LEN		0x30
  2.1417 +#define TG3_TSO_FW_RODATA_LEN		0x60
  2.1418  #define TG3_TSO_FW_DATA_ADDR		0x080016a0
  2.1419  #define TG3_TSO_FW_DATA_LEN		0x20
  2.1420  #define TG3_TSO_FW_SBSS_ADDR		0x080016c0
  2.1421 -#define TG3_TSO_FW_SBSS_LEN		0x14
  2.1422 +#define TG3_TSO_FW_SBSS_LEN		0x2c
  2.1423  #define TG3_TSO_FW_BSS_ADDR		0x080016e0
  2.1424 -#define TG3_TSO_FW_BSS_LEN		0x8fc
  2.1425 +#define TG3_TSO_FW_BSS_LEN		0x890
  2.1426  
  2.1427  static u32 tg3TsoFwText[] = {
  2.1428  	0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  2.1429  	0x37bd4000, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000010, 0x00000000,
  2.1430 -	0x0000000d, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0x3c1bc000,
  2.1431 -	0xafbf0018, 0x0e000058, 0xaf60680c, 0x3c040800, 0x24841650, 0x03602821,
  2.1432 -	0x24060001, 0x24070004, 0xafa00010, 0x0e00006c, 0xafa00014, 0x8f625c50,
  2.1433 -	0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001, 0xaf625c90, 0x2402ffff,
  2.1434 -	0x0e000098, 0xaf625404, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  2.1435 -	0x00000000, 0x00000000, 0x24030b60, 0x24050fff, 0xac000b50, 0x00002021,
  2.1436 -	0xac640000, 0x24630004, 0x0065102b, 0x1440fffc, 0x24840001, 0x24030b60,
  2.1437 -	0x0065102b, 0x10400011, 0x00002021, 0x24090b54, 0x3c06dead, 0x34c6beef,
  2.1438 -	0x24080b58, 0x24070b5c, 0x8c620000, 0x50440006, 0x24630004, 0xad260000,
  2.1439 -	0x8c620000, 0xace40000, 0xad020000, 0x24630004, 0x0065102b, 0x1440fff6,
  2.1440 -	0x24840001, 0x03e00008, 0x00000000, 0x27bdfff8, 0x18800009, 0x00002821,
  2.1441 -	0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000, 0x24a50001, 0x00a4102a,
  2.1442 -	0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008, 0x3c020800, 0x34423000,
  2.1443 -	0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac2216c4,
  2.1444 -	0x24020040, 0x3c010800, 0xac2216c8, 0x3c010800, 0xac2016c0, 0xac600000,
  2.1445 -	0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  2.1446 -	0x00804821, 0x8faa0010, 0x3c020800, 0x8c4216c0, 0x3c040800, 0x8c8416c8,
  2.1447 -	0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac2316c0, 0x14400003,
  2.1448 -	0x00004021, 0x3c010800, 0xac2016c0, 0x3c020800, 0x8c4216c0, 0x3c030800,
  2.1449 -	0x8c6316c4, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  2.1450 -	0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c4216c0,
  2.1451 -	0x3c030800, 0x8c6316c4, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  2.1452 -	0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  2.1453 -	0x00000000, 0x00000000, 0x27bdffe0, 0xafbf0018, 0xafb10014, 0x0e0000b6,
  2.1454 -	0xafb00010, 0x24110001, 0x8f706820, 0x32020100, 0x10400003, 0x00000000,
  2.1455 -	0x0e000127, 0x00000000, 0x8f706820, 0x32022000, 0x10400004, 0x32020001,
  2.1456 -	0x0e00025a, 0x24040001, 0x32020001, 0x10400003, 0x00000000, 0x0e0000e6,
  2.1457 -	0x00000000, 0x0a00009e, 0xaf715028, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
  2.1458 -	0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841660, 0x00002821,
  2.1459 -	0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00006c, 0xafa00014,
  2.1460 -	0x3c010800, 0xa4201fb8, 0x3c010800, 0xa02016f8, 0x3c010800, 0xac2016fc,
  2.1461 -	0x3c010800, 0xac201700, 0x3c010800, 0xac201704, 0x3c010800, 0xac20170c,
  2.1462 -	0x3c010800, 0xac201718, 0x3c010800, 0xac20171c, 0x8f624434, 0x3c010800,
  2.1463 -	0xac2216e8, 0x8f624438, 0x3c010800, 0xac2216ec, 0x8f624410, 0x3c010800,
  2.1464 -	0xac2016e0, 0x3c010800, 0xac2016e4, 0x3c010800, 0xac201fc0, 0x3c010800,
  2.1465 -	0xac201f68, 0x3c010800, 0xac201f6c, 0x3c010800, 0xac2216f0, 0x8fbf0018,
  2.1466 -	0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x2484166c, 0x00002821,
  2.1467 -	0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00006c, 0xafa00014,
  2.1468 -	0x3c040800, 0x24841660, 0x00002821, 0x00003021, 0x00003821, 0xafa00010,
  2.1469 -	0x0e00006c, 0xafa00014, 0x3c010800, 0xa4201fb8, 0x3c010800, 0xa02016f8,
  2.1470 -	0x3c010800, 0xac2016fc, 0x3c010800, 0xac201700, 0x3c010800, 0xac201704,
  2.1471 -	0x3c010800, 0xac20170c, 0x3c010800, 0xac201718, 0x3c010800, 0xac20171c,
  2.1472 -	0x8f624434, 0x3c010800, 0xac2216e8, 0x8f624438, 0x3c010800, 0xac2216ec,
  2.1473 -	0x8f624410, 0x3c010800, 0xac2016e0, 0x3c010800, 0xac2016e4, 0x3c010800,
  2.1474 -	0xac201fc0, 0x3c010800, 0xac201f68, 0x3c010800, 0xac201f6c, 0x3c010800,
  2.1475 -	0xac2216f0, 0x0e000120, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  2.1476 -	0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  2.1477 -	0xaf636820, 0x27bdffd0, 0x3c0300ff, 0xafbf002c, 0xafb60028, 0xafb50024,
  2.1478 -	0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f665c5c,
  2.1479 -	0x3c040800, 0x2484171c, 0x8c820000, 0x3463fff8, 0x14460005, 0x00c38824,
  2.1480 -	0x3c020800, 0x904216f8, 0x14400115, 0x00000000, 0x00111902, 0x306300ff,
  2.1481 -	0x30c20003, 0x000211c0, 0x00623825, 0x00e02821, 0x00061602, 0xac860000,
  2.1482 -	0x3c030800, 0x906316f8, 0x3044000f, 0x1460002b, 0x00804021, 0x24020001,
  2.1483 -	0x3c010800, 0xa02216f8, 0x00071100, 0x00821025, 0x3c010800, 0xac2016fc,
  2.1484 -	0x3c010800, 0xac201700, 0x3c010800, 0xac201704, 0x3c010800, 0xac20170c,
  2.1485 -	0x3c010800, 0xac201718, 0x3c010800, 0xac201710, 0x3c010800, 0xac201714,
  2.1486 -	0x3c010800, 0xa4221fb8, 0x9623000c, 0x30628000, 0x10400008, 0x30627fff,
  2.1487 -	0x2442003e, 0x3c010800, 0xa42216f6, 0x24020001, 0x3c010800, 0x0a00016e,
  2.1488 -	0xac221fd4, 0x24620036, 0x3c010800, 0xa42216f6, 0x3c010800, 0xac201fd4,
  2.1489 -	0x3c010800, 0xac201fd0, 0x3c010800, 0x0a000176, 0xac201fd8, 0x9622000c,
  2.1490 -	0x3c010800, 0xa4221fcc, 0x3c040800, 0x248416fc, 0x8c820000, 0x00021100,
  2.1491 -	0x3c010800, 0x00220821, 0xac311728, 0x8c820000, 0x00021100, 0x3c010800,
  2.1492 -	0x00220821, 0xac26172c, 0x8c820000, 0x24a30001, 0x306701ff, 0x00021100,
  2.1493 -	0x3c010800, 0x00220821, 0xac271730, 0x8c820000, 0x00021100, 0x3c010800,
  2.1494 -	0x00220821, 0xac281734, 0x96230008, 0x3c020800, 0x8c42170c, 0x00432821,
  2.1495 -	0x3c010800, 0xac25170c, 0x9622000a, 0x30420004, 0x14400019, 0x00071100,
  2.1496 -	0x3c02c000, 0x00c21825, 0xaf635c5c, 0x8f625c50, 0x30420002, 0x1440fffc,
  2.1497 -	0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002, 0x1440001e, 0x00000000,
  2.1498 -	0x8f630c14, 0x3c020800, 0x8c4216b4, 0x3063000f, 0x24420001, 0x3c010800,
  2.1499 -	0xac2216b4, 0x2c620002, 0x1040fff7, 0x00000000, 0x0a0001c1, 0x00000000,
  2.1500 -	0x3c030800, 0x8c6316e0, 0x3c040800, 0x948416f4, 0x01021025, 0x3c010800,
  2.1501 -	0xa4221fba, 0x24020001, 0x3c010800, 0xac221718, 0x24630001, 0x0085202a,
  2.1502 -	0x3c010800, 0x10800003, 0xac2316e0, 0x3c010800, 0xa42516f4, 0x3c030800,
  2.1503 -	0x246316fc, 0x8c620000, 0x24420001, 0xac620000, 0x28420080, 0x14400005,
  2.1504 -	0x24020001, 0x0e0002df, 0x24040002, 0x0a000250, 0x00000000, 0x3c030800,
  2.1505 -	0x906316f8, 0x1462007c, 0x24020003, 0x3c160800, 0x96d616f6, 0x3c050800,
  2.1506 -	0x8ca5170c, 0x32c4ffff, 0x00a4102a, 0x14400078, 0x00000000, 0x3c020800,
  2.1507 -	0x8c421718, 0x10400005, 0x32c2ffff, 0x14a40003, 0x00000000, 0x3c010800,
  2.1508 -	0xac231fd0, 0x10400062, 0x00009021, 0x0040a021, 0x3c150800, 0x26b51700,
  2.1509 -	0x26b30010, 0x8ea20000, 0x00028100, 0x3c110800, 0x02308821, 0x0e0002e1,
  2.1510 -	0x8e311728, 0x00403021, 0x10c00059, 0x00000000, 0x9628000a, 0x31020040,
  2.1511 -	0x10400004, 0x2407180c, 0x8e22000c, 0x2407188c, 0xacc20018, 0x31021000,
  2.1512 -	0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825, 0x3c030800,
  2.1513 -	0x00701821, 0x8c631730, 0x3c020800, 0x00501021, 0x8c421734, 0x00031d00,
  2.1514 -	0x00021400, 0x00621825, 0xacc30014, 0x8ea30004, 0x96220008, 0x00432023,
  2.1515 -	0x3242ffff, 0x3083ffff, 0x00431021, 0x0282102a, 0x14400002, 0x02d22823,
  2.1516 -	0x00802821, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000, 0x8e220000,
  2.1517 -	0xacc20000, 0x8e220004, 0x8e63fff4, 0x00431021, 0xacc20004, 0xa4c5000e,
  2.1518 -	0x8e62fff4, 0x00441021, 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005,
  2.1519 -	0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0xae62fff0, 0xacc00008,
  2.1520 -	0x3242ffff, 0x14540008, 0x24020305, 0x31020080, 0x54400001, 0x34e70010,
  2.1521 -	0x24020905, 0xa4c2000c, 0x0a000233, 0x34e70020, 0xa4c2000c, 0x30e2ffff,
  2.1522 -	0xacc20010, 0x3c020800, 0x8c421fd0, 0x10400003, 0x3c024b65, 0x0a00023d,
  2.1523 -	0x34427654, 0x3c02b49a, 0x344289ab, 0xacc2001c, 0x0e000560, 0x00c02021,
  2.1524 -	0x3242ffff, 0x0054102b, 0x1440ffa4, 0x00000000, 0x24020002, 0x3c010800,
  2.1525 -	0x0a000250, 0xa02216f8, 0x8ea208bc, 0x24420001, 0x0a000250, 0xaea208bc,
  2.1526 -	0x14620003, 0x00000000, 0x0e000450, 0x00000000, 0x8fbf002c, 0x8fb60028,
  2.1527 -	0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
  2.1528 -	0x03e00008, 0x27bd0030, 0x27bdffd8, 0xafb3001c, 0x00809821, 0xafbf0020,
  2.1529 -	0xafb20018, 0xafb10014, 0xafb00010, 0x8f725c9c, 0x3c0200ff, 0x3442fff8,
  2.1530 -	0x3c040800, 0x24841714, 0x02428824, 0x9623000e, 0x8c820000, 0x00431021,
  2.1531 -	0xac820000, 0x8e220010, 0x30420020, 0x14400011, 0x00000000, 0x0e0002f7,
  2.1532 +	0x0000000d, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0x3c04fefe,
  2.1533 +	0xafbf0018, 0x0e0005e0, 0x34840002, 0x0e000670, 0x00000000, 0x3c030800,
  2.1534 +	0x90631b78, 0x24020002, 0x3c040800, 0x24841acc, 0x14620003, 0x24050001,
  2.1535 +	0x3c040800, 0x24841ac0, 0x24060002, 0x00003821, 0xafa00010, 0x0e000684,
  2.1536 +	0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  2.1537 +	0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  2.1538 +	0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf0018,
  2.1539 +	0xafb10014, 0x0e000052, 0xafb00010, 0x24110001, 0x8f706820, 0x32020100,
  2.1540 +	0x10400003, 0x00000000, 0x0e0000b2, 0x00000000, 0x8f706820, 0x32022000,
  2.1541 +	0x10400004, 0x32020001, 0x0e0001e3, 0x24040001, 0x32020001, 0x10400003,
  2.1542 +	0x00000000, 0x0e00009a, 0x00000000, 0x0a00003a, 0xaf715028, 0x8fbf0018,
  2.1543 +	0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800,
  2.1544 +	0x24841ae0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  2.1545 +	0x0e000684, 0xafa00014, 0x3c040800, 0x248423e8, 0xa4800000, 0x3c010800,
  2.1546 +	0xa0201ba8, 0x3c010800, 0xac201bac, 0x3c010800, 0xac201bb0, 0x3c010800,
  2.1547 +	0xac201bb4, 0x3c010800, 0xac201bbc, 0x3c010800, 0xac201bc8, 0x3c010800,
  2.1548 +	0xac201bcc, 0x8f624434, 0x3c010800, 0xac221b98, 0x8f624438, 0x3c010800,
  2.1549 +	0xac221b9c, 0x8f624410, 0xac80f7a8, 0x3c010800, 0xac201b94, 0x3c010800,
  2.1550 +	0xac2023f0, 0x3c010800, 0xac2023d8, 0x3c010800, 0xac2023dc, 0x3c010800,
  2.1551 +	0xac202410, 0x3c010800, 0xac221ba0, 0x8f620068, 0x24030007, 0x00021702,
  2.1552 +	0x10430005, 0x00000000, 0x8f620068, 0x00021702, 0x14400004, 0x24020001,
  2.1553 +	0x3c010800, 0x0a00008e, 0xac20241c, 0xac820034, 0x3c040800, 0x24841aec,
  2.1554 +	0x3c050800, 0x8ca5241c, 0x00003021, 0x00003821, 0xafa00010, 0x0e000684,
  2.1555 +	0xafa00014, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x27bdffe0, 0x3c040800,
  2.1556 +	0x24841af8, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  2.1557 +	0x0e000684, 0xafa00014, 0x0e000052, 0x00000000, 0x0e0000ab, 0x00002021,
  2.1558 +	0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001, 0x8f636820, 0x00821004,
  2.1559 +	0x00021027, 0x00621824, 0x03e00008, 0xaf636820, 0x27bdffd0, 0xafbf002c,
  2.1560 +	0xafb60028, 0xafb50024, 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014,
  2.1561 +	0xafb00010, 0x8f665c5c, 0x3c030800, 0x24631bcc, 0x8c620000, 0x14460005,
  2.1562 +	0x3c0200ff, 0x3c020800, 0x90421ba8, 0x14400115, 0x3c0200ff, 0x3442fff8,
  2.1563 +	0x00c28824, 0xac660000, 0x00111902, 0x306300ff, 0x30c20003, 0x000211c0,
  2.1564 +	0x00623825, 0x00e02821, 0x00061602, 0x3c030800, 0x90631ba8, 0x3044000f,
  2.1565 +	0x1460002b, 0x00804021, 0x24020001, 0x3c010800, 0xa0221ba8, 0x00071100,
  2.1566 +	0x00821025, 0x3c010800, 0xac201bac, 0x3c010800, 0xac201bb0, 0x3c010800,
  2.1567 +	0xac201bb4, 0x3c010800, 0xac201bbc, 0x3c010800, 0xac201bc8, 0x3c010800,
  2.1568 +	0xac201bc0, 0x3c010800, 0xac201bc4, 0x3c010800, 0xa42223e8, 0x9623000c,
  2.1569 +	0x30628000, 0x10400008, 0x30627fff, 0x2442003e, 0x3c010800, 0xa4221ba6,
  2.1570 +	0x24020001, 0x3c010800, 0x0a0000f9, 0xac222404, 0x24620036, 0x3c010800,
  2.1571 +	0xa4221ba6, 0x3c010800, 0xac202404, 0x3c010800, 0xac202400, 0x3c010800,
  2.1572 +	0x0a000101, 0xac202408, 0x9622000c, 0x3c010800, 0xa42223fc, 0x3c040800,
  2.1573 +	0x24841bac, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821, 0xac311bd8,
  2.1574 +	0x8c820000, 0x00021100, 0x3c010800, 0x00220821, 0xac261bdc, 0x8c820000,
  2.1575 +	0x24a30001, 0x306701ff, 0x00021100, 0x3c010800, 0x00220821, 0xac271be0,
  2.1576 +	0x8c820000, 0x00021100, 0x3c010800, 0x00220821, 0xac281be4, 0x96230008,
  2.1577 +	0x3c020800, 0x8c421bbc, 0x00432821, 0x3c010800, 0xac251bbc, 0x9622000a,
  2.1578 +	0x30420004, 0x14400018, 0x00071100, 0x8f630c14, 0x3063000f, 0x2c620002,
  2.1579 +	0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800, 0x8c421b50, 0x3063000f,
  2.1580 +	0x24420001, 0x3c010800, 0xac221b50, 0x2c620002, 0x1040fff7, 0x3c02c000,
  2.1581 +	0x00c21825, 0xaf635c5c, 0x8f625c50, 0x30420002, 0x10400014, 0x00000000,
  2.1582 +	0x0a000133, 0x00000000, 0x3c030800, 0x8c631b90, 0x3c040800, 0x94841ba4,
  2.1583 +	0x01021025, 0x3c010800, 0xa42223ea, 0x24020001, 0x3c010800, 0xac221bc8,
  2.1584 +	0x24630001, 0x0085202a, 0x3c010800, 0x10800003, 0xac231b90, 0x3c010800,
  2.1585 +	0xa4251ba4, 0x3c060800, 0x24c61bac, 0x8cc20000, 0x24420001, 0xacc20000,
  2.1586 +	0x28420080, 0x14400005, 0x00000000, 0x0e00065e, 0x24040002, 0x0a0001d9,
  2.1587 +	0x00000000, 0x3c020800, 0x8c421bc8, 0x1040007f, 0x24020001, 0x3c040800,
  2.1588 +	0x90841ba8, 0x14820077, 0x24020003, 0x3c150800, 0x96b51ba6, 0x3c050800,
  2.1589 +	0x8ca51bbc, 0x32a3ffff, 0x00a3102a, 0x14400073, 0x00000000, 0x14a30003,
  2.1590 +	0x00000000, 0x3c010800, 0xac242400, 0x10600061, 0x00009021, 0x24d60004,
  2.1591 +	0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100, 0x3c110800, 0x02308821,
  2.1592 +	0x0e00062d, 0x8e311bd8, 0x00403021, 0x10c00059, 0x00000000, 0x9628000a,
  2.1593 +	0x31020040, 0x10400004, 0x2407180c, 0x8e22000c, 0x2407188c, 0xacc20018,
  2.1594 +	0x31021000, 0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825,
  2.1595 +	0x3c030800, 0x00701821, 0x8c631be0, 0x3c020800, 0x00501021, 0x8c421be4,
  2.1596 +	0x00031d00, 0x00021400, 0x00621825, 0xacc30014, 0x8ec30004, 0x96220008,
  2.1597 +	0x00432023, 0x3242ffff, 0x3083ffff, 0x00431021, 0x0282102a, 0x14400002,
  2.1598 +	0x02b22823, 0x00802821, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  2.1599 +	0x8e220000, 0xacc20000, 0x8e220004, 0x8e63fff4, 0x00431021, 0xacc20004,
  2.1600 +	0xa4c5000e, 0x8e62fff4, 0x00441021, 0xae62fff4, 0x96230008, 0x0043102a,
  2.1601 +	0x14400005, 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0xae62fff0,
  2.1602 +	0xacc00008, 0x3242ffff, 0x14540008, 0x24020305, 0x31020080, 0x54400001,
  2.1603 +	0x34e70010, 0x24020905, 0xa4c2000c, 0x0a0001bc, 0x34e70020, 0xa4c2000c,
  2.1604 +	0x3c020800, 0x8c422400, 0x10400003, 0x3c024b65, 0x0a0001c4, 0x34427654,
  2.1605 +	0x3c02b49a, 0x344289ab, 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005aa,
  2.1606 +	0x00c02021, 0x3242ffff, 0x0054102b, 0x1440ffa4, 0x00000000, 0x24020002,
  2.1607 +	0x3c010800, 0x0a0001d9, 0xa0221ba8, 0x8ec2083c, 0x24420001, 0x0a0001d9,
  2.1608 +	0xaec2083c, 0x14820003, 0x00000000, 0x0e0004b9, 0x00000000, 0x8fbf002c,
  2.1609 +	0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014,
  2.1610 +	0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028, 0xafb30024,
  2.1611 +	0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff, 0x3442fff8,
  2.1612 +	0x3c060800, 0x24c61bc4, 0x02428824, 0x9623000e, 0x8cc20000, 0x00431021,
  2.1613 +	0xacc20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821, 0x0e000643,
  2.1614  	0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  2.1615 -	0x10400061, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x1040005c,
  2.1616 -	0x00000000, 0x0a000278, 0x00000000, 0x8e220008, 0x00021c02, 0x000321c0,
  2.1617 -	0x3042ffff, 0x3c030800, 0x906316f8, 0x000229c0, 0x24020002, 0x14620003,
  2.1618 -	0x3c034b65, 0x0a000290, 0x00008021, 0x8e22001c, 0x34637654, 0x10430002,
  2.1619 -	0x24100002, 0x24100001, 0x0e000300, 0x02003021, 0x24020003, 0x3c010800,
  2.1620 -	0xa02216f8, 0x24020002, 0x1202000a, 0x24020001, 0x3c030800, 0x8c631fd0,
  2.1621 -	0x10620006, 0x00000000, 0x3c020800, 0x94421fb8, 0x00021400, 0x0a0002cd,
  2.1622 -	0xae220014, 0x3c040800, 0x24841fba, 0x94820000, 0x00021400, 0xae220014,
  2.1623 -	0x3c020800, 0x8c42171c, 0x3c03c000, 0x3c010800, 0xa02016f8, 0x00431025,
  2.1624 -	0xaf625c5c, 0x8f625c50, 0x30420002, 0x10400009, 0x00000000, 0x2484f762,
  2.1625 +	0x10400121, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x1040011c,
  2.1626 +	0x00000000, 0x0a000200, 0x00000000, 0x8e240008, 0x8e230014, 0x00041402,
  2.1627 +	0x000241c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f, 0x00031942,
  2.1628 +	0x30637800, 0x00021100, 0x24424000, 0x00625021, 0x9542000a, 0x3084ffff,
  2.1629 +	0x30420008, 0x104000b3, 0x000429c0, 0x3c020800, 0x8c422410, 0x1440002d,
  2.1630 +	0x25050008, 0x95020014, 0x3c010800, 0xa42223e0, 0x8d070010, 0x00071402,
  2.1631 +	0x3c010800, 0xa42223e2, 0x3c010800, 0xa42723e4, 0x9502000e, 0x30e3ffff,
  2.1632 +	0x00431023, 0x3c010800, 0xac222418, 0x8f626800, 0x3c030010, 0x00431024,
  2.1633 +	0x10400005, 0x00000000, 0x9503001a, 0x9502001c, 0x0a000235, 0x00431021,
  2.1634 +	0x9502001a, 0x3c010800, 0xac22240c, 0x3c02c000, 0x02421825, 0x3c010800,
  2.1635 +	0xac282410, 0x3c010800, 0xac322414, 0xaf635c9c, 0x8f625c90, 0x30420002,
  2.1636 +	0x104000df, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000da,
  2.1637 +	0x00000000, 0x0a000242, 0x00000000, 0x9502000e, 0x3c030800, 0x946323e4,
  2.1638 +	0x00434823, 0x3123ffff, 0x2c620008, 0x1040001c, 0x00000000, 0x95020014,
  2.1639 +	0x24420028, 0x00a22821, 0x00031042, 0x1840000b, 0x00002021, 0x24c60848,
  2.1640 +	0x00403821, 0x94a30000, 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000,
  2.1641 +	0x0087102a, 0x1440fff9, 0x24a50002, 0x31220001, 0x1040001f, 0x3c024000,
  2.1642 +	0x3c040800, 0x2484240c, 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021,
  2.1643 +	0x0a000281, 0xac820000, 0x8f626800, 0x3c030010, 0x00431024, 0x10400009,
  2.1644 +	0x00000000, 0x9502001a, 0x3c030800, 0x8c63240c, 0x00431021, 0x3c010800,
  2.1645 +	0xac22240c, 0x0a000282, 0x3c024000, 0x9502001a, 0x9504001c, 0x3c030800,
  2.1646 +	0x8c63240c, 0x00441023, 0x00621821, 0x3c010800, 0xac23240c, 0x3c024000,
  2.1647 +	0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000,
  2.1648 +	0x9542000a, 0x30420010, 0x10400095, 0x00000000, 0x3c060800, 0x24c62410,
  2.1649 +	0x3c020800, 0x944223e4, 0x8cc50000, 0x3c040800, 0x8c842418, 0x24420030,
  2.1650 +	0x00a22821, 0x94a20004, 0x3c030800, 0x8c63240c, 0x00441023, 0x00621821,
  2.1651 +	0x00603821, 0x00032402, 0x30e2ffff, 0x00823821, 0x00071402, 0x00e23821,
  2.1652 +	0x00071027, 0x3c010800, 0xac23240c, 0xa4a20006, 0x3c030800, 0x8c632414,
  2.1653 +	0x3c0200ff, 0x3442fff8, 0x00628824, 0x96220008, 0x24040001, 0x24034000,
  2.1654 +	0x000241c0, 0x00e01021, 0xa502001a, 0xa500001c, 0xacc00000, 0x3c010800,
  2.1655 +	0xac241b70, 0xaf635cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  2.1656 +	0x3c010800, 0xac201b70, 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002,
  2.1657 +	0x10400003, 0x00000000, 0x3c010800, 0xac201b70, 0x3c020800, 0x8c421b70,
  2.1658 +	0x1040ffec, 0x00000000, 0x3c040800, 0x0e000643, 0x8c842414, 0x0a000320,
  2.1659 +	0x00000000, 0x3c030800, 0x90631ba8, 0x24020002, 0x14620003, 0x3c034b65,
  2.1660 +	0x0a0002d7, 0x00008021, 0x8e22001c, 0x34637654, 0x10430002, 0x24100002,
  2.1661 +	0x24100001, 0x01002021, 0x0e000346, 0x02003021, 0x24020003, 0x3c010800,
  2.1662 +	0xa0221ba8, 0x24020002, 0x1202000a, 0x24020001, 0x3c030800, 0x8c632400,
  2.1663 +	0x10620006, 0x00000000, 0x3c020800, 0x944223e8, 0x00021400, 0x0a000315,
  2.1664 +	0xae220014, 0x3c040800, 0x248423ea, 0x94820000, 0x00021400, 0xae220014,
  2.1665 +	0x3c020800, 0x8c421bcc, 0x3c03c000, 0x3c010800, 0xa0201ba8, 0x00431025,
  2.1666 +	0xaf625c5c, 0x8f625c50, 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2,
  2.1667  	0x8c820000, 0x00431025, 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa,
  2.1668 -	0x00000000, 0x3c020800, 0x244216e4, 0x8c430000, 0x24630001, 0xac430000,
  2.1669 -	0x8f630c14, 0x3063000f, 0x2c620002, 0x1440000b, 0x00009821, 0x8f630c14,
  2.1670 -	0x3c020800, 0x8c4216b4, 0x3063000f, 0x24420001, 0x3c010800, 0xac2216b4,
  2.1671 -	0x2c620002, 0x1040fff7, 0x00009821, 0x3c024000, 0x02421825, 0xaf635c9c,
  2.1672 +	0x00000000, 0x3c020800, 0x24421b94, 0x8c430000, 0x24630001, 0xac430000,
  2.1673 +	0x8f630c14, 0x3063000f, 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14,
  2.1674 +	0x3c020800, 0x8c421b50, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b50,
  2.1675 +	0x2c620002, 0x1040fff7, 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c,
  2.1676  	0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x12600003, 0x00000000,
  2.1677 -	0x0e000450, 0x00000000, 0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014,
  2.1678 -	0x8fb00010, 0x03e00008, 0x27bd0028, 0x0a0002df, 0x00000000, 0x8f634450,
  2.1679 -	0x3c040800, 0x248416e8, 0x8c820000, 0x00031c02, 0x0043102b, 0x14400007,
  2.1680 -	0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc,
  2.1681 -	0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd, 0x00000000,
  2.1682 -	0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000, 0x00822025, 0xaf645c38,
  2.1683 -	0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000, 0x03e00008, 0x00000000,
  2.1684 -	0x27bdffe0, 0x00805021, 0x14c00017, 0x254c0008, 0x3c020800, 0x8c421fd4,
  2.1685 -	0x1040000a, 0x2402003e, 0x3c010800, 0xa4221fb0, 0x24020016, 0x3c010800,
  2.1686 -	0xa4221fb2, 0x2402002a, 0x3c010800, 0x0a00031a, 0xa4221fb4, 0x95420014,
  2.1687 -	0x3c010800, 0xa4221fb0, 0x8d430010, 0x00031402, 0x3c010800, 0xa4221fb2,
  2.1688 -	0x3c010800, 0xa4231fb4, 0x3c040800, 0x94841fb4, 0x3c030800, 0x94631fb2,
  2.1689 -	0x958d0006, 0x3c020800, 0x94421fb0, 0x00832023, 0x01a27023, 0x3065ffff,
  2.1690 -	0x24a20028, 0x01824021, 0x3082ffff, 0x14c0001a, 0x01025821, 0x9562000c,
  2.1691 -	0x3042003f, 0x3c010800, 0xa4221fb6, 0x95620004, 0x95630006, 0x3c010800,
  2.1692 -	0xac201fc4, 0x3c010800, 0xac201fc8, 0x00021400, 0x00431025, 0x3c010800,
  2.1693 -	0xac221720, 0x95020004, 0x3c010800, 0xa4221724, 0x95030002, 0x01a51023,
  2.1694 -	0x0043102a, 0x10400010, 0x24020001, 0x3c010800, 0x0a00034e, 0xac221fd8,
  2.1695 -	0x3c030800, 0x8c631fc8, 0x3c020800, 0x94421724, 0x00431021, 0xa5020004,
  2.1696 -	0x3c020800, 0x94421720, 0xa5620004, 0x3c020800, 0x8c421720, 0xa5620006,
  2.1697 -	0x3c020800, 0x8c421fd0, 0x3c070800, 0x8ce71fc4, 0x3c050800, 0x144000c7,
  2.1698 -	0x8ca51fc8, 0x3c020800, 0x94421724, 0x00451821, 0x3063ffff, 0x0062182b,
  2.1699 -	0x24020002, 0x10c2000d, 0x00a32823, 0x3c020800, 0x94421fb6, 0x30420009,
  2.1700 -	0x10400008, 0x00000000, 0x9562000c, 0x3042fff6, 0xa562000c, 0x3c020800,
  2.1701 -	0x94421fb6, 0x30420009, 0x00e23823, 0x3c020800, 0x8c421fd8, 0x1040004b,
  2.1702 -	0x24020002, 0x01003021, 0x3c020800, 0x94421fb2, 0x00003821, 0xa500000a,
  2.1703 -	0x01a21023, 0xa5020002, 0x3082ffff, 0x00021042, 0x18400008, 0x00002821,
  2.1704 -	0x00401821, 0x94c20000, 0x24e70001, 0x00a22821, 0x00e3102a, 0x1440fffb,
  2.1705 -	0x24c60002, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.1706 -	0x00a04821, 0x00051027, 0xa502000a, 0x00002821, 0x2506000c, 0x00003821,
  2.1707 -	0x94c20000, 0x24e70001, 0x00a22821, 0x2ce20004, 0x1440fffb, 0x24c60002,
  2.1708 -	0x95020002, 0x00003821, 0x91030009, 0x00442023, 0x01603021, 0x3082ffff,
  2.1709 -	0xa4c00010, 0x00621821, 0x00021042, 0x18400010, 0x00a32821, 0x00404021,
  2.1710 -	0x94c20000, 0x24c60002, 0x00a22821, 0x30c2007f, 0x14400006, 0x24e70001,
  2.1711 -	0x8d430000, 0x3c02007f, 0x3442ff80, 0x00625024, 0x25460008, 0x00e8102a,
  2.1712 -	0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00051c02, 0xa0c00001,
  2.1713 -	0x94c20000, 0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.1714 -	0x00a22821, 0x0a000415, 0x30a5ffff, 0x14c20063, 0x00000000, 0x3c090800,
  2.1715 -	0x95291fb2, 0x95030002, 0x01a91023, 0x1062005d, 0x01003021, 0x00003821,
  2.1716 -	0x00002821, 0x01a91023, 0xa5020002, 0x3082ffff, 0x00021042, 0x18400008,
  2.1717 -	0xa500000a, 0x00401821, 0x94c20000, 0x24e70001, 0x00a22821, 0x00e3102a,
  2.1718 -	0x1440fffb, 0x24c60002, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.1719 -	0x00a22821, 0x00a04821, 0x00051027, 0xa502000a, 0x00002821, 0x2506000c,
  2.1720 -	0x00003821, 0x94c20000, 0x24e70001, 0x00a22821, 0x2ce20004, 0x1440fffb,
  2.1721 -	0x24c60002, 0x95020002, 0x00003821, 0x91030009, 0x00442023, 0x01603021,
  2.1722 -	0x3082ffff, 0xa4c00010, 0x3c040800, 0x94841fb4, 0x00621821, 0x00a32821,
  2.1723 -	0x00051c02, 0x30a2ffff, 0x00622821, 0x00051c02, 0x3c020800, 0x94421fb0,
  2.1724 -	0x00a34021, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043, 0x18400010,
  2.1725 -	0x00002821, 0x00402021, 0x94c20000, 0x24c60002, 0x00a22821, 0x30c2007f,
  2.1726 -	0x14400006, 0x24e70001, 0x8d430000, 0x3c02007f, 0x3442ff80, 0x00625024,
  2.1727 -	0x25460008, 0x00e4102a, 0x1440fff3, 0x00000000, 0x3c020800, 0x94421fcc,
  2.1728 -	0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.1729 -	0x3102ffff, 0x00a22821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402,
  2.1730 -	0x00a22821, 0x00a02021, 0x00051027, 0xa5620010, 0xad800014, 0x0a000435,
  2.1731 -	0xad800000, 0x8d830010, 0x00602021, 0x10a00007, 0x00034c02, 0x01252821,
  2.1732 -	0x00051402, 0x30a3ffff, 0x00432821, 0x00051402, 0x00a24821, 0x00091027,
  2.1733 -	0xa502000a, 0x3c030800, 0x94631fb4, 0x3082ffff, 0x01a21021, 0x00432823,
  2.1734 -	0x00a72821, 0x00051c02, 0x30a2ffff, 0x00622821, 0x00051402, 0x00a22821,
  2.1735 -	0x00a02021, 0x00051027, 0xa5620010, 0x3082ffff, 0x00091c00, 0x00431025,
  2.1736 -	0xad820010, 0x3c020800, 0x8c421fd4, 0x10400002, 0x25a2fff2, 0xa5820034,
  2.1737 -	0x3c020800, 0x8c421fc8, 0x3c030800, 0x8c631720, 0x24420001, 0x3c010800,
  2.1738 -	0xac221fc8, 0x3c020800, 0x8c421fc4, 0x31c4ffff, 0x00641821, 0x3c010800,
  2.1739 -	0xac231720, 0x00441021, 0x3c010800, 0xac221fc4, 0x03e00008, 0x27bd0020,
  2.1740 -	0x27bdffc8, 0x3c040800, 0x248416f8, 0xafbf0034, 0xafbe0030, 0xafb7002c,
  2.1741 -	0xafb60028, 0xafb50024, 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014,
  2.1742 -	0xafb00010, 0x90830000, 0x24020003, 0x146200f4, 0x00000000, 0x3c020800,
  2.1743 -	0x8c421710, 0x3c030800, 0x8c63170c, 0x3c1e0800, 0x97de16f6, 0x0043102a,
  2.1744 -	0x104000eb, 0x3c168000, 0x249708c4, 0x33d5ffff, 0x24920018, 0x3c020800,
  2.1745 -	0x8c421718, 0x104000e4, 0x00000000, 0x3c140800, 0x96941fb0, 0x3282ffff,
  2.1746 -	0x104000d6, 0x00008021, 0x00409821, 0x00008821, 0x8f634450, 0x3c020800,
  2.1747 -	0x8c4216e8, 0x00031c02, 0x0043102b, 0x14400008, 0x00000000, 0x3c040800,
  2.1748 -	0x8c8416ec, 0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc, 0x00000000,
  2.1749 -	0xaf764444, 0x8f624444, 0x00561024, 0x10400006, 0x00000000, 0x3c038000,
  2.1750 -	0x8f624444, 0x00431024, 0x1440fffd, 0x00000000, 0x8f624448, 0x3046ffff,
  2.1751 -	0x10c0005f, 0x00000000, 0x3c090800, 0x01314821, 0x8d291728, 0x9528000a,
  2.1752 -	0x31020040, 0x10400004, 0x2407180c, 0x8d22000c, 0x2407188c, 0xacc20018,
  2.1753 -	0x31021000, 0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825,
  2.1754 -	0x31020080, 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421730,
  2.1755 -	0x3c030800, 0x00711821, 0x8c631734, 0x00021500, 0x00031c00, 0x00431025,
  2.1756 -	0xacc20014, 0x95240008, 0x3202ffff, 0x00821021, 0x0262102a, 0x14400002,
  2.1757 -	0x02902823, 0x00802821, 0x8d220000, 0x02058021, 0xacc20000, 0x8d220004,
  2.1758 -	0x00c02021, 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e,
  2.1759 -	0xac820010, 0x24020305, 0x0e000560, 0xa482000c, 0x3202ffff, 0x0053102b,
  2.1760 -	0x1440ffaf, 0x3202ffff, 0x0a00054c, 0x00000000, 0x8e420000, 0x8e43fffc,
  2.1761 -	0x0043102a, 0x10400084, 0x00000000, 0x8e45fff0, 0x8f644450, 0x3c030800,
  2.1762 -	0x8c6316e8, 0x00051100, 0x3c090800, 0x01224821, 0x8d291728, 0x00041402,
  2.1763 -	0x0062182b, 0x14600008, 0x00000000, 0x3c030800, 0x8c6316ec, 0x8f624450,
  2.1764 -	0x00021402, 0x0062102b, 0x1040fffc, 0x00000000, 0xaf764444, 0x8f624444,
  2.1765 -	0x00561024, 0x10400006, 0x00000000, 0x3c038000, 0x8f624444, 0x00431024,
  2.1766 -	0x1440fffd, 0x00000000, 0x8f624448, 0x3046ffff, 0x14c00005, 0x00000000,
  2.1767 -	0x8ee20000, 0x24420001, 0x0a000554, 0xaee20000, 0x9528000a, 0x31020040,
  2.1768 -	0x10400004, 0x2407180c, 0x8d22000c, 0x2407188c, 0xacc20018, 0x31021000,
  2.1769 -	0x10400004, 0x34e32000, 0x00081040, 0x3042c000, 0x00623825, 0x00051900,
  2.1770 -	0x3c020800, 0x00431021, 0x8c421730, 0x3c010800, 0x00230821, 0x8c231734,
  2.1771 -	0x00021500, 0x00031c00, 0x00431025, 0xacc20014, 0x3c030800, 0x8c631704,
  2.1772 -	0x95220008, 0x00432023, 0x3202ffff, 0x3083ffff, 0x00431021, 0x02a2102a,
  2.1773 -	0x14400002, 0x03d02823, 0x00802821, 0x8e420000, 0x30a4ffff, 0x00441021,
  2.1774 -	0xae420000, 0xa4c5000e, 0x8d220000, 0xacc20000, 0x8d220004, 0x8e43fff4,
  2.1775 -	0x00431021, 0xacc20004, 0x8e43fff4, 0x95220008, 0x00641821, 0x0062102a,
  2.1776 -	0x14400006, 0x02058021, 0x8e42fff0, 0xae40fff4, 0x24420001, 0x0a000530,
  2.1777 -	0xae42fff0, 0xae43fff4, 0xacc00008, 0x3202ffff, 0x10550003, 0x31020004,
  2.1778 -	0x10400006, 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020,
  2.1779 -	0x24020905, 0xa4c2000c, 0x30e2ffff, 0xacc20010, 0x3c030800, 0x8c63170c,
  2.1780 -	0x3c020800, 0x8c421710, 0x54620004, 0x3c02b49a, 0x3c024b65, 0x0a000548,
  2.1781 -	0x34427654, 0x344289ab, 0xacc2001c, 0x0e000560, 0x00c02021, 0x3202ffff,
  2.1782 -	0x0055102b, 0x1440ff7e, 0x00000000, 0x8e420000, 0x8e43fffc, 0x0043102a,
  2.1783 -	0x1440ff1a, 0x00000000, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028,
  2.1784 -	0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
  2.1785 -	0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  2.1786 -	0x8f634410, 0x0a00056f, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  2.1787 -	0x00000000, 0x0e00025a, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  2.1788 -	0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  2.1789 -	0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c4216b4, 0x3063000f,
  2.1790 -	0x24420001, 0x3c010800, 0xac2216b4, 0x2c620002, 0x1040fff7, 0x00000000,
  2.1791 -	0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  2.1792 -	0x30422000, 0x1040fff8, 0x00000000, 0x0e00025a, 0x00002021, 0x0a000582,
  2.1793 -	0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  2.1794 -	0x00000000
  2.1795 +	0x0e0004b9, 0x00000000, 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c,
  2.1796 +	0x8fb00018, 0x03e00008, 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b98,
  2.1797 +	0x8c820000, 0x00031c02, 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004,
  2.1798 +	0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444,
  2.1799 +	0x8f624444, 0x00431024, 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008,
  2.1800 +	0x3042ffff, 0x3c024000, 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002,
  2.1801 +	0x1440fffc, 0x00000000, 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821,
  2.1802 +	0x14c00017, 0x256e0008, 0x3c020800, 0x8c422404, 0x1040000a, 0x2402003e,
  2.1803 +	0x3c010800, 0xa42223e0, 0x24020016, 0x3c010800, 0xa42223e2, 0x2402002a,
  2.1804 +	0x3c010800, 0x0a000360, 0xa42223e4, 0x95620014, 0x3c010800, 0xa42223e0,
  2.1805 +	0x8d670010, 0x00071402, 0x3c010800, 0xa42223e2, 0x3c010800, 0xa42723e4,
  2.1806 +	0x3c040800, 0x948423e4, 0x3c030800, 0x946323e2, 0x95cf0006, 0x3c020800,
  2.1807 +	0x944223e0, 0x00832023, 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821,
  2.1808 +	0x3082ffff, 0x14c0001a, 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800,
  2.1809 +	0xa42223e6, 0x95820004, 0x95830006, 0x3c010800, 0xac2023f4, 0x3c010800,
  2.1810 +	0xac2023f8, 0x00021400, 0x00431025, 0x3c010800, 0xac221bd0, 0x95220004,
  2.1811 +	0x3c010800, 0xa4221bd4, 0x95230002, 0x01e51023, 0x0043102a, 0x10400010,
  2.1812 +	0x24020001, 0x3c010800, 0x0a000394, 0xac222408, 0x3c030800, 0x8c6323f8,
  2.1813 +	0x3c020800, 0x94421bd4, 0x00431021, 0xa5220004, 0x3c020800, 0x94421bd0,
  2.1814 +	0xa5820004, 0x3c020800, 0x8c421bd0, 0xa5820006, 0x3c020800, 0x8c422400,
  2.1815 +	0x3c0d0800, 0x8dad23f4, 0x3c0a0800, 0x144000e5, 0x8d4a23f8, 0x3c020800,
  2.1816 +	0x94421bd4, 0x004a1821, 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d,
  2.1817 +	0x01435023, 0x3c020800, 0x944223e6, 0x30420009, 0x10400008, 0x00000000,
  2.1818 +	0x9582000c, 0x3042fff6, 0xa582000c, 0x3c020800, 0x944223e6, 0x30420009,
  2.1819 +	0x01a26823, 0x3c020800, 0x8c422408, 0x1040004a, 0x01203821, 0x3c020800,
  2.1820 +	0x944223e2, 0x00004021, 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff,
  2.1821 +	0x00021042, 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001,
  2.1822 +	0x00c23021, 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff,
  2.1823 +	0x00623021, 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a,
  2.1824 +	0x00003021, 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021,
  2.1825 +	0x2d020004, 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009,
  2.1826 +	0x00442023, 0x01803821, 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042,
  2.1827 +	0x18400010, 0x00c33021, 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021,
  2.1828 +	0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  2.1829 +	0x00625824, 0x25670008, 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001,
  2.1830 +	0x10400005, 0x00061c02, 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02,
  2.1831 +	0x30c2ffff, 0x00623021, 0x00061402, 0x00c23021, 0x0a000479, 0x30c6ffff,
  2.1832 +	0x24020002, 0x14c20081, 0x00000000, 0x3c020800, 0x8c42241c, 0x14400007,
  2.1833 +	0x00000000, 0x3c020800, 0x944223e2, 0x95230002, 0x01e21023, 0x10620077,
  2.1834 +	0x00000000, 0x3c020800, 0x944223e2, 0x01e21023, 0xa5220002, 0x3c020800,
  2.1835 +	0x8c42241c, 0x1040001a, 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421ba6,
  2.1836 +	0x00e04021, 0x00072c02, 0x00aa2021, 0x00431023, 0x00823823, 0x00072402,
  2.1837 +	0x30e2ffff, 0x00823821, 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800,
  2.1838 +	0x948423e4, 0x00453023, 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021,
  2.1839 +	0x00061c02, 0x30c2ffff, 0x0a000479, 0x00623021, 0x01203821, 0x00004021,
  2.1840 +	0x3082ffff, 0x00021042, 0x18400008, 0x00003021, 0x00401821, 0x94e20000,
  2.1841 +	0x25080001, 0x00c23021, 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02,
  2.1842 +	0x30c2ffff, 0x00623021, 0x00061402, 0x00c23021, 0x00c02821, 0x00061027,
  2.1843 +	0xa522000a, 0x00003021, 0x2527000c, 0x00004021, 0x94e20000, 0x25080001,
  2.1844 +	0x00c23021, 0x2d020004, 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021,
  2.1845 +	0x91230009, 0x00442023, 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800,
  2.1846 +	0x948423e4, 0x00621821, 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021,
  2.1847 +	0x00061c02, 0x3c020800, 0x944223e0, 0x00c34821, 0x00441023, 0x00021fc2,
  2.1848 +	0x00431021, 0x00021043, 0x18400010, 0x00003021, 0x00402021, 0x94e20000,
  2.1849 +	0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000,
  2.1850 +	0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3,
  2.1851 +	0x00000000, 0x3c020800, 0x944223fc, 0x00c23021, 0x3122ffff, 0x00c23021,
  2.1852 +	0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402, 0x00c23021, 0x00c04021,
  2.1853 +	0x00061027, 0xa5820010, 0xadc00014, 0x0a000499, 0xadc00000, 0x8dc70010,
  2.1854 +	0x00e04021, 0x11400007, 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff,
  2.1855 +	0x00433021, 0x00061402, 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800,
  2.1856 +	0x946323e4, 0x3102ffff, 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02,
  2.1857 +	0x30c2ffff, 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027,
  2.1858 +	0xa5820010, 0x3102ffff, 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800,
  2.1859 +	0x8c422404, 0x10400002, 0x25e2fff2, 0xa5c20034, 0x3c020800, 0x8c4223f8,
  2.1860 +	0x3c040800, 0x8c8423f4, 0x24420001, 0x3c010800, 0xac2223f8, 0x3c020800,
  2.1861 +	0x8c421bd0, 0x3303ffff, 0x00832021, 0x3c010800, 0xac2423f4, 0x00431821,
  2.1862 +	0x0062102b, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223f4, 0x3c010800,
  2.1863 +	0xac231bd0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800, 0x24a51ba8,
  2.1864 +	0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034, 0xafb40030,
  2.1865 +	0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x90a30000, 0x24020003,
  2.1866 +	0x146200d5, 0x00000000, 0x3c090800, 0x95291ba6, 0x3c020800, 0x944223e0,
  2.1867 +	0x3c030800, 0x8c631bc0, 0x3c040800, 0x8c841bbc, 0x01221023, 0x0064182a,
  2.1868 +	0xa7a9001e, 0x106000c8, 0xa7a20016, 0x24be0020, 0x97b6001e, 0x24b30018,
  2.1869 +	0x24b70014, 0x8fc20000, 0x14400008, 0x00000000, 0x8fc2fff8, 0x97a30016,
  2.1870 +	0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000ba, 0x00000000, 0x97d50818,
  2.1871 +	0x32a2ffff, 0x104000ad, 0x00009021, 0x0040a021, 0x00008821, 0x0e00062d,
  2.1872 +	0x00000000, 0x00403021, 0x14c00007, 0x00000000, 0x3c020800, 0x8c4223ec,
  2.1873 +	0x24420001, 0x3c010800, 0x0a00059e, 0xac2223ec, 0x3c100800, 0x02118021,
  2.1874 +	0x8e101bd8, 0x9608000a, 0x31020040, 0x10400004, 0x2407180c, 0x8e02000c,
  2.1875 +	0x2407188c, 0xacc20018, 0x31021000, 0x10400004, 0x34e32000, 0x00081040,
  2.1876 +	0x3042c000, 0x00623825, 0x31020080, 0x54400001, 0x34e70010, 0x3c020800,
  2.1877 +	0x00511021, 0x8c421be0, 0x3c030800, 0x00711821, 0x8c631be4, 0x00021500,
  2.1878 +	0x00031c00, 0x00431025, 0xacc20014, 0x96040008, 0x3242ffff, 0x00821021,
  2.1879 +	0x0282102a, 0x14400002, 0x02b22823, 0x00802821, 0x8e020000, 0x02459021,
  2.1880 +	0xacc20000, 0x8e020004, 0x00c02021, 0x26310010, 0xac820004, 0x30e2ffff,
  2.1881 +	0xac800008, 0xa485000e, 0xac820010, 0x24020305, 0x0e0005aa, 0xa482000c,
  2.1882 +	0x3242ffff, 0x0054102b, 0x1440ffc0, 0x3242ffff, 0x0a000596, 0x00000000,
  2.1883 +	0x8e620000, 0x8e63fffc, 0x0043102a, 0x1040006c, 0x00000000, 0x8e62fff0,
  2.1884 +	0x00028900, 0x3c100800, 0x02118021, 0x0e00062d, 0x8e101bd8, 0x00403021,
  2.1885 +	0x14c00005, 0x00000000, 0x8e62082c, 0x24420001, 0x0a00059e, 0xae62082c,
  2.1886 +	0x9608000a, 0x31020040, 0x10400004, 0x2407180c, 0x8e02000c, 0x2407188c,
  2.1887 +	0xacc20018, 0x31021000, 0x10400004, 0x34e32000, 0x00081040, 0x3042c000,
  2.1888 +	0x00623825, 0x3c020800, 0x00511021, 0x8c421be0, 0x3c030800, 0x00711821,
  2.1889 +	0x8c631be4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4,
  2.1890 +	0x96020008, 0x00432023, 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a,
  2.1891 +	0x10400003, 0x00802821, 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff,
  2.1892 +	0x00441021, 0xae620000, 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004,
  2.1893 +	0x8e63fff4, 0x00431021, 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821,
  2.1894 +	0x0062102a, 0x14400006, 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001,
  2.1895 +	0x0a000579, 0xae62fff0, 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003,
  2.1896 +	0x31020004, 0x10400006, 0x24020305, 0x31020080, 0x54400001, 0x34e70010,
  2.1897 +	0x34e70020, 0x24020905, 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007,
  2.1898 +	0x3c02b49a, 0x8ee20860, 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000590,
  2.1899 +	0x34427654, 0x344289ab, 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005aa,
  2.1900 +	0x00c02021, 0x3242ffff, 0x0056102b, 0x1440ff96, 0x00000000, 0x8e620000,
  2.1901 +	0x8e63fffc, 0x0043102a, 0x1440ff3e, 0x00000000, 0x8fbf0044, 0x8fbe0040,
  2.1902 +	0x8fb7003c, 0x8fb60038, 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028,
  2.1903 +	0x8fb10024, 0x8fb00020, 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014,
  2.1904 +	0xafb00010, 0x8f624450, 0x8f634410, 0x0a0005b9, 0x00808021, 0x8f626820,
  2.1905 +	0x30422000, 0x10400003, 0x00000000, 0x0e0001e3, 0x00002021, 0x8f624450,
  2.1906 +	0x8f634410, 0x3042ffff, 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14,
  2.1907 +	0x3063000f, 0x2c620002, 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800,
  2.1908 +	0x8c421b50, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b50, 0x2c620002,
  2.1909 +	0x1040fff7, 0x00000000, 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009,
  2.1910 +	0x00000000, 0x8f626820, 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001e3,
  2.1911 +	0x00002021, 0x0a0005cc, 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008,
  2.1912 +	0x27bd0018, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000,
  2.1913 +	0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804,
  2.1914 +	0x8f634000, 0x24020b50, 0x3c010800, 0xac221b64, 0x24020b78, 0x3c010800,
  2.1915 +	0xac221b74, 0x34630002, 0xaf634000, 0x0e00060d, 0x00808021, 0x3c010800,
  2.1916 +	0xa0221b78, 0x304200ff, 0x24030002, 0x14430005, 0x00000000, 0x3c020800,
  2.1917 +	0x8c421b64, 0x0a000600, 0xac5000c0, 0x3c020800, 0x8c421b64, 0xac5000bc,
  2.1918 +	0x8f624434, 0x8f634438, 0x8f644410, 0x3c010800, 0xac221b6c, 0x3c010800,
  2.1919 +	0xac231b7c, 0x3c010800, 0xac241b68, 0x8fbf0014, 0x8fb00010, 0x03e00008,
  2.1920 +	0x27bd0018, 0x3c040800, 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003,
  2.1921 +	0xac830000, 0x8cc20000, 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa,
  2.1922 +	0xac830000, 0x8cc20000, 0x50430001, 0x24050001, 0x3c020800, 0xac470000,
  2.1923 +	0x03e00008, 0x00a01021, 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c,
  2.1924 +	0x8f62680c, 0x1043fffe, 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9,
  2.1925 +	0x00000000, 0x03e00008, 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b6c,
  2.1926 +	0x00031c02, 0x0043102b, 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b7c,
  2.1927 +	0x8f624450, 0x00021c02, 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444,
  2.1928 +	0x8f624444, 0x00431024, 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008,
  2.1929 +	0x3042ffff, 0x3082ffff, 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000,
  2.1930 +	0x0a000650, 0x2402ffff, 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002,
  2.1931 +	0x1440fffc, 0x00001021, 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800,
  2.1932 +	0x8c631b68, 0x0a000659, 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b,
  2.1933 +	0x1440fffc, 0x00000000, 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821,
  2.1934 +	0x3c040800, 0x24841b10, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  2.1935 +	0x0e000684, 0xafa00014, 0x0a000668, 0x00000000, 0x8fbf0018, 0x03e00008,
  2.1936 +	0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  2.1937 +	0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b84,
  2.1938 +	0x24020040, 0x3c010800, 0xac221b88, 0x3c010800, 0xac201b80, 0xac600000,
  2.1939 +	0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  2.1940 +	0x00804821, 0x8faa0010, 0x3c020800, 0x8c421b80, 0x3c040800, 0x8c841b88,
  2.1941 +	0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac231b80, 0x14400003,
  2.1942 +	0x00004021, 0x3c010800, 0xac201b80, 0x3c020800, 0x8c421b80, 0x3c030800,
  2.1943 +	0x8c631b84, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  2.1944 +	0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b80,
  2.1945 +	0x3c030800, 0x8c631b84, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  2.1946 +	0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  2.1947 +	0x00000000, 0x00000000,
  2.1948  };
  2.1949  
  2.1950  u32 tg3TsoFwRodata[] = {
  2.1951 -	0x4d61696e, 0x43707542, 0x00000000, 0x00000000, 0x74637073, 0x6567496e,
  2.1952 -	0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000, 0x00000000,
  2.1953 -	0x00000000
  2.1954 +	0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541,
  2.1955 +	0x00000000, 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64,
  2.1956 +	0x496e0000, 0x73746b6f, 0x66662a2a, 0x00000000, 0x53774576,
  2.1957 +	0x656e7430, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  2.1958 +	0x66617461, 0x6c457272, 0x00000000, 0x00000000, 0x00000000
  2.1959  };
  2.1960  
  2.1961 -#if 0 /* All zeros, dont eat up space with it. */
  2.1962 +#if 0 /* All zeros, don't eat up space with it. */
  2.1963  u32 tg3TsoFwData[] = {
  2.1964  	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  2.1965  	0x00000000, 0x00000000, 0x00000000
  2.1966  };
  2.1967  #endif
  2.1968  
  2.1969 +/* 5705 needs a special version of the TSO firmware.  */
  2.1970 +#define TG3_TSO5_FW_RELEASE_MAJOR	0x1
  2.1971 +#define TG3_TSO5_FW_RELASE_MINOR	0x1
  2.1972 +#define TG3_TSO5_FW_RELEASE_FIX		0x0
  2.1973 +#define TG3_TSO5_FW_START_ADDR		0x00010000
  2.1974 +#define TG3_TSO5_FW_TEXT_ADDR		0x00010000
  2.1975 +#define TG3_TSO5_FW_TEXT_LEN		0xeb0
  2.1976 +#define TG3_TSO5_FW_RODATA_ADDR		0x00010eb0
  2.1977 +#define TG3_TSO5_FW_RODATA_LEN		0x50
  2.1978 +#define TG3_TSO5_FW_DATA_ADDR		0x00010f20
  2.1979 +#define TG3_TSO5_FW_DATA_LEN		0x20
  2.1980 +#define TG3_TSO5_FW_SBSS_ADDR		0x00010f40
  2.1981 +#define TG3_TSO5_FW_SBSS_LEN		0x28
  2.1982 +#define TG3_TSO5_FW_BSS_ADDR		0x00010f70
  2.1983 +#define TG3_TSO5_FW_BSS_LEN		0x88
  2.1984 +
  2.1985 +static u32 tg3Tso5FwText[] = {
  2.1986 +	0x0c004003, 0x00000000, 0x00010f30, 0x00000000, 0x10000003, 0x00000000,
  2.1987 +	0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  2.1988 +	0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  2.1989 +	0xafbf0018, 0x0c0042f0, 0x34840002, 0x0c00436c, 0x00000000, 0x3c030001,
  2.1990 +	0x90630f54, 0x24020002, 0x3c040001, 0x24840ebc, 0x14620003, 0x24050001,
  2.1991 +	0x3c040001, 0x24840eb0, 0x24060001, 0x00003821, 0xafa00010, 0x0c004380,
  2.1992 +	0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  2.1993 +	0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  2.1994 +	0x0c0042d3, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  2.1995 +	0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  2.1996 +	0x0c004064, 0x00000000, 0x3c020001, 0x90420f76, 0x10510003, 0x32020200,
  2.1997 +	0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  2.1998 +	0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  2.1999 +	0x27bdffe0, 0x3c040001, 0x24840ed0, 0x00002821, 0x00003021, 0x00003821,
  2.2000 +	0xafbf0018, 0xafa00010, 0x0c004380, 0xafa00014, 0x0000d021, 0x24020130,
  2.2001 +	0xaf625000, 0x3c010001, 0xa4200f70, 0x3c010001, 0xa0200f77, 0x8fbf0018,
  2.2002 +	0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f80,
  2.2003 +	0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  2.2004 +	0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  2.2005 +	0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  2.2006 +	0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f9a, 0x00041402,
  2.2007 +	0xa0a20000, 0x3c010001, 0xa0240f9b, 0x3c020001, 0x00431021, 0x94428014,
  2.2008 +	0x3c010001, 0xa0220f9c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  2.2009 +	0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f80, 0x0124102b,
  2.2010 +	0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  2.2011 +	0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  2.2012 +	0x24c60008, 0x00003821, 0x3c080001, 0x25080f9b, 0x91060000, 0x3c020001,
  2.2013 +	0x90420f9c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  2.2014 +	0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  2.2015 +	0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  2.2016 +	0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  2.2017 +	0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  2.2018 +	0x080040fa, 0xac220fa0, 0x3c050001, 0x24a50f9c, 0x90a20000, 0x3c0c0001,
  2.2019 +	0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  2.2020 +	0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  2.2021 +	0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f9c,
  2.2022 +	0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  2.2023 +	0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  2.2024 +	0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  2.2025 +	0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  2.2026 +	0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  2.2027 +	0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  2.2028 +	0x90420f9c, 0x3c030001, 0x90630f9a, 0x00e2c823, 0x3c020001, 0x90420f9b,
  2.2029 +	0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  2.2030 +	0x3c010001, 0xa4220f98, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f96,
  2.2031 +	0x3c010001, 0xa4200f92, 0x00021400, 0x00431025, 0x3c010001, 0xac220f8c,
  2.2032 +	0x95020004, 0x3c010001, 0x08004124, 0xa4220f90, 0x3c020001, 0x94420f90,
  2.2033 +	0x3c030001, 0x94630f92, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f8c,
  2.2034 +	0xa4c20004, 0x3c020001, 0x8c420f8c, 0xa4c20006, 0x3c040001, 0x94840f92,
  2.2035 +	0x3c020001, 0x94420f90, 0x3c0a0001, 0x954a0f96, 0x00441821, 0x3063ffff,
  2.2036 +	0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f98,
  2.2037 +	0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f98,
  2.2038 +	0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  2.2039 +	0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  2.2040 +	0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0fa0, 0x10800005,
  2.2041 +	0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  2.2042 +	0xa502000a, 0x3c030001, 0x90630f9b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  2.2043 +	0x00432023, 0x3c020001, 0x94420fa0, 0x00442021, 0x00041c02, 0x3082ffff,
  2.2044 +	0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  2.2045 +	0x24a50f9a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  2.2046 +	0x00e21023, 0xa5020002, 0x3c030001, 0x94630fa0, 0x3c020001, 0x94420f7a,
  2.2047 +	0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  2.2048 +	0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f9c, 0x24620001,
  2.2049 +	0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  2.2050 +	0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  2.2051 +	0x94420fa2, 0x3183ffff, 0x3c040001, 0x90840f9b, 0x00431021, 0x00e21021,
  2.2052 +	0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  2.2053 +	0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  2.2054 +	0x00431025, 0x3c040001, 0x24840f92, 0xade20010, 0x94820000, 0x3c050001,
  2.2055 +	0x94a50f96, 0x3c030001, 0x8c630f8c, 0x24420001, 0x00b92821, 0xa4820000,
  2.2056 +	0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f96, 0x10600003,
  2.2057 +	0x24a2ffff, 0x3c010001, 0xa4220f96, 0x3c024000, 0x03021025, 0x3c010001,
  2.2058 +	0xac240f8c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f76,
  2.2059 +	0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  2.2060 +	0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f84,
  2.2061 +	0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  2.2062 +	0x24020008, 0x3c010001, 0xa4220f88, 0x30620004, 0x10400005, 0x24020001,
  2.2063 +	0x3c010001, 0xa0220f77, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f77,
  2.2064 +	0x00031402, 0x3c010001, 0xa4220f74, 0x9483000c, 0x24020001, 0x3c010001,
  2.2065 +	0xa4200f70, 0x3c010001, 0xa0220f76, 0x3c010001, 0xa4230f82, 0x24020001,
  2.2066 +	0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  2.2067 +	0x080042cf, 0x00000000, 0x3c020001, 0x94420f82, 0x241a0001, 0x3c010001,
  2.2068 +	0xa4200f7e, 0x3c010001, 0xa4200f72, 0x304407ff, 0x00021bc2, 0x00031823,
  2.2069 +	0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  2.2070 +	0xa4240f78, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f7a, 0x3c010001,
  2.2071 +	0xa4230f7c, 0x3c060001, 0x24c60f72, 0x94c50000, 0x94c30002, 0x3c040001,
  2.2072 +	0x94840f7a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  2.2073 +	0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f76, 0x8f641008,
  2.2074 +	0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  2.2075 +	0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  2.2076 +	0x94630f70, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  2.2077 +	0xa4230f70, 0xaf620ce8, 0x3c020001, 0x94420f88, 0x34420024, 0xaf620cec,
  2.2078 +	0x94c30002, 0x3c020001, 0x94420f70, 0x14620012, 0x3c028000, 0x3c108000,
  2.2079 +	0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f76, 0x8f641008, 0x00901024,
  2.2080 +	0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  2.2081 +	0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  2.2082 +	0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  2.2083 +	0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  2.2084 +	0x3c070001, 0x24e70f70, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  2.2085 +	0x8c420f84, 0xaf620ce4, 0x3c050001, 0x94a50f74, 0x94e30000, 0x3c040001,
  2.2086 +	0x94840f78, 0x3c020001, 0x94420f7e, 0x00a32823, 0x00822023, 0x30a6ffff,
  2.2087 +	0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f7c,
  2.2088 +	0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f74,
  2.2089 +	0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  2.2090 +	0x90420f77, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f88, 0x34630624,
  2.2091 +	0x0800427c, 0x0000d021, 0x3c020001, 0x94420f88, 0x3c030008, 0x34630624,
  2.2092 +	0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  2.2093 +	0xa0200f76, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  2.2094 +	0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  2.2095 +	0x00000000, 0x3c030001, 0x94630f88, 0x34420624, 0x3c108000, 0x00621825,
  2.2096 +	0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  2.2097 +	0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  2.2098 +	0x00000000, 0x3c010001, 0x080042cf, 0xa4200f7e, 0x3c020001, 0x94420f7c,
  2.2099 +	0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f77, 0x10400009,
  2.2100 +	0x3c03000c, 0x3c020001, 0x94420f88, 0x34630624, 0x0000d021, 0x00431025,
  2.2101 +	0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f88, 0x3c030008,
  2.2102 +	0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f7e, 0x00451021,
  2.2103 +	0x3c010001, 0xa4220f7e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  2.2104 +	0xa0200f76, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  2.2105 +	0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  2.2106 +	0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffe0, 0x3c040001, 0x24840ee0,
  2.2107 +	0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004380,
  2.2108 +	0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001, 0xa4200f70,
  2.2109 +	0x3c010001, 0xa0200f77, 0x8f636804, 0x3c020001, 0x3442e000, 0x00621824,
  2.2110 +	0x3c020001, 0x14620003, 0x00000000, 0x080042eb, 0x00000000, 0x8fbf0018,
  2.2111 +	0x03e00008, 0x27bd0020, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  2.2112 +	0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  2.2113 +	0x3c010001, 0xac220f40, 0x24020b78, 0x3c010001, 0xac220f50, 0x34630002,
  2.2114 +	0xaf634000, 0x0c00431d, 0x00808021, 0x3c010001, 0xa0220f54, 0x304200ff,
  2.2115 +	0x24030002, 0x14430005, 0x00000000, 0x3c020001, 0x8c420f40, 0x08004310,
  2.2116 +	0xac5000c0, 0x3c020001, 0x8c420f40, 0xac5000bc, 0x8f624434, 0x8f634438,
  2.2117 +	0x8f644410, 0x3c010001, 0xac220f48, 0x3c010001, 0xac230f58, 0x3c010001,
  2.2118 +	0xac240f44, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008,
  2.2119 +	0x24020001, 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c,
  2.2120 +	0x1043fffe, 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000,
  2.2121 +	0x03e00008, 0x27bd0008, 0x8f634450, 0x3c020001, 0x8c420f48, 0x00031c02,
  2.2122 +	0x0043102b, 0x14400008, 0x3c038000, 0x3c040001, 0x8c840f58, 0x8f624450,
  2.2123 +	0x00021c02, 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444,
  2.2124 +	0x00431024, 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff,
  2.2125 +	0x3082ffff, 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0800434f,
  2.2126 +	0x2402ffff, 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc,
  2.2127 +	0x00001021, 0x03e00008, 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f44,
  2.2128 +	0x08004358, 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc,
  2.2129 +	0x00000000, 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001,
  2.2130 +	0x24840ef0, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004380,
  2.2131 +	0xafa00014, 0x08004367, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  2.2132 +	0x3c020001, 0x3442d600, 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff,
  2.2133 +	0x3c010001, 0xac220f60, 0x24020040, 0x3c010001, 0xac220f64, 0x3c010001,
  2.2134 +	0xac200f5c, 0xac600000, 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000,
  2.2135 +	0x03e00008, 0x00000000, 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f5c,
  2.2136 +	0x3c040001, 0x8c840f64, 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001,
  2.2137 +	0xac230f5c, 0x14400003, 0x00004021, 0x3c010001, 0xac200f5c, 0x3c020001,
  2.2138 +	0x8c420f5c, 0x3c030001, 0x8c630f60, 0x91240000, 0x00021140, 0x00431021,
  2.2139 +	0x00481021, 0x25080001, 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001,
  2.2140 +	0x3c020001, 0x8c420f5c, 0x3c030001, 0x8c630f60, 0x8f64680c, 0x00021140,
  2.2141 +	0x00431021, 0xac440008, 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018,
  2.2142 +	0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  2.2143 +};
  2.2144 +
  2.2145 +u32 tg3Tso5FwRodata[] = {
  2.2146 +	0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  2.2147 +	0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  2.2148 +	0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  2.2149 +	0x00000000, 0x00000000, 0x00000000
  2.2150 +};
  2.2151 +
  2.2152 +u32 tg3Tso5FwData[] = {
  2.2153 +	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x73746b6f, 
  2.2154 +	0x66666c64, 0x5f76312e, 0x312e3000, 0x00000000
  2.2155 +};
  2.2156 +
  2.2157  /* tp->lock is held. */
  2.2158  static int tg3_load_tso_firmware(struct tg3 *tp)
  2.2159  {
  2.2160  	struct fw_info info;
  2.2161 +	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  2.2162  	int err, i;
  2.2163  
  2.2164 -	info.text_base = TG3_TSO_FW_TEXT_ADDR;
  2.2165 -	info.text_len = TG3_TSO_FW_TEXT_LEN;
  2.2166 -	info.text_data = &tg3TsoFwText[0];
  2.2167 -	info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  2.2168 -	info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  2.2169 -	info.rodata_data = &tg3TsoFwRodata[0];
  2.2170 -	info.data_base = TG3_TSO_FW_DATA_ADDR;
  2.2171 -	info.data_len = TG3_TSO_FW_DATA_LEN;
  2.2172 -	info.data_data = NULL;
  2.2173 -
  2.2174 -	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  2.2175 -				    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  2.2176 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.2177 +		info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  2.2178 +		info.text_len = TG3_TSO5_FW_TEXT_LEN;
  2.2179 +		info.text_data = &tg3Tso5FwText[0];
  2.2180 +		info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  2.2181 +		info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  2.2182 +		info.rodata_data = &tg3Tso5FwRodata[0];
  2.2183 +		info.data_base = TG3_TSO5_FW_DATA_ADDR;
  2.2184 +		info.data_len = TG3_TSO5_FW_DATA_LEN;
  2.2185 +		info.data_data = &tg3Tso5FwData[0];
  2.2186 +		cpu_base = RX_CPU_BASE;
  2.2187 +		cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  2.2188 +		cpu_scratch_size = (info.text_len +
  2.2189 +				    info.rodata_len +
  2.2190 +				    info.data_len +
  2.2191 +				    TG3_TSO5_FW_SBSS_LEN +
  2.2192 +				    TG3_TSO5_FW_BSS_LEN);
  2.2193 +	} else {
  2.2194 +		info.text_base = TG3_TSO_FW_TEXT_ADDR;
  2.2195 +		info.text_len = TG3_TSO_FW_TEXT_LEN;
  2.2196 +		info.text_data = &tg3TsoFwText[0];
  2.2197 +		info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  2.2198 +		info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  2.2199 +		info.rodata_data = &tg3TsoFwRodata[0];
  2.2200 +		info.data_base = TG3_TSO_FW_DATA_ADDR;
  2.2201 +		info.data_len = TG3_TSO_FW_DATA_LEN;
  2.2202 +		info.data_data = NULL;
  2.2203 +		cpu_base = TX_CPU_BASE;
  2.2204 +		cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  2.2205 +		cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  2.2206 +	}
  2.2207 +
  2.2208 +	err = tg3_load_firmware_cpu(tp, cpu_base,
  2.2209 +				    cpu_scratch_base, cpu_scratch_size,
  2.2210  				    &info);
  2.2211  	if (err)
  2.2212  		return err;
  2.2213  
  2.2214 -	/* Now startup only the TX cpu. */
  2.2215 -	tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.2216 -	tw32(TX_CPU_BASE + CPU_PC,    TG3_TSO_FW_TEXT_ADDR);
  2.2217 +	/* Now startup the cpu. */
  2.2218 +	tw32(cpu_base + CPU_STATE, 0xffffffff);
  2.2219 +	tw32(cpu_base + CPU_PC,    info.text_base);
  2.2220  
  2.2221  	/* Flush posted writes. */
  2.2222 -	tr32(TX_CPU_BASE + CPU_PC);
  2.2223 +	tr32(cpu_base + CPU_PC);
  2.2224  	for (i = 0; i < 5; i++) {
  2.2225 -		if (tr32(TX_CPU_BASE + CPU_PC) == TG3_TSO_FW_TEXT_ADDR)
  2.2226 +		if (tr32(cpu_base + CPU_PC) == info.text_base)
  2.2227  			break;
  2.2228 -		tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.2229 -		tw32(TX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
  2.2230 -		tw32(TX_CPU_BASE + CPU_PC,    TG3_TSO_FW_TEXT_ADDR);
  2.2231 +		tw32(cpu_base + CPU_STATE, 0xffffffff);
  2.2232 +		tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
  2.2233 +		tw32(cpu_base + CPU_PC,    info.text_base);
  2.2234  
  2.2235  		/* Flush posted writes. */
  2.2236 -		tr32(TX_CPU_BASE + CPU_PC);
  2.2237 +		tr32(cpu_base + CPU_PC);
  2.2238  
  2.2239  		udelay(1000);
  2.2240  	}
  2.2241  	if (i >= 5) {
  2.2242  		printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  2.2243 -		       "to set TX CPU PC, is %08x should be %08x\n",
  2.2244 -		       tp->dev->name, tr32(TX_CPU_BASE + CPU_PC),
  2.2245 -		       TG3_TSO_FW_TEXT_ADDR);
  2.2246 +		       "to set CPU PC, is %08x should be %08x\n",
  2.2247 +		       tp->dev->name, tr32(cpu_base + CPU_PC),
  2.2248 +		       info.text_base);
  2.2249  		return -ENODEV;
  2.2250  	}
  2.2251 -	tw32(TX_CPU_BASE + CPU_STATE, 0xffffffff);
  2.2252 -	tw32(TX_CPU_BASE + CPU_MODE,  0x00000000);
  2.2253 +	tw32(cpu_base + CPU_STATE, 0xffffffff);
  2.2254 +	tw32(cpu_base + CPU_MODE,  0x00000000);
  2.2255  
  2.2256  	/* Flush posted writes. */
  2.2257 -	tr32(TX_CPU_BASE + CPU_MODE);
  2.2258 +	tr32(cpu_base + CPU_MODE);
  2.2259  
  2.2260  	return 0;
  2.2261  }
  2.2262  
  2.2263 -#endif /* TG3_DO_TSO != 0 */
  2.2264 +#endif /* TG3_TSO_SUPPORT != 0 */
  2.2265  
  2.2266  /* tp->lock is held. */
  2.2267  static void __tg3_set_mac_addr(struct tg3 *tp)
  2.2268 @@ -3912,6 +4499,15 @@ static void __tg3_set_mac_addr(struct tg
  2.2269  		tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  2.2270  	}
  2.2271  
  2.2272 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  2.2273 +	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  2.2274 +	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2275 +		for (i = 0; i < 12; i++) {
  2.2276 +			tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  2.2277 +			tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  2.2278 +		}
  2.2279 +	}
  2.2280 +
  2.2281  	addr_high = (tp->dev->dev_addr[0] +
  2.2282  		     tp->dev->dev_addr[1] +
  2.2283  		     tp->dev->dev_addr[2] +
  2.2284 @@ -3945,23 +4541,19 @@ static void tg3_set_bdinfo(struct tg3 *t
  2.2285  			   u32 nic_addr)
  2.2286  {
  2.2287  	tg3_write_mem(tp,
  2.2288 -		      (bdinfo_addr +
  2.2289 -		       TG3_BDINFO_HOST_ADDR +
  2.2290 -		       TG3_64BIT_REG_HIGH),
  2.2291 +		      (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  2.2292  		      ((u64) mapping >> 32));
  2.2293  	tg3_write_mem(tp,
  2.2294 -		      (bdinfo_addr +
  2.2295 -		       TG3_BDINFO_HOST_ADDR +
  2.2296 -		       TG3_64BIT_REG_LOW),
  2.2297 +		      (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  2.2298  		      ((u64) mapping & 0xffffffff));
  2.2299  	tg3_write_mem(tp,
  2.2300 -		      (bdinfo_addr +
  2.2301 -		       TG3_BDINFO_MAXLEN_FLAGS),
  2.2302 +		      (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  2.2303  		       maxlen_flags);
  2.2304 -	tg3_write_mem(tp,
  2.2305 -		      (bdinfo_addr +
  2.2306 -		       TG3_BDINFO_NIC_ADDR),
  2.2307 -		      nic_addr);
  2.2308 +
  2.2309 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
  2.2310 +		tg3_write_mem(tp,
  2.2311 +			      (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  2.2312 +			      nic_addr);
  2.2313  }
  2.2314  
  2.2315  static void __tg3_set_rx_mode(struct net_device *);
  2.2316 @@ -3969,8 +4561,8 @@ static void __tg3_set_rx_mode(struct net
  2.2317  /* tp->lock is held. */
  2.2318  static int tg3_reset_hw(struct tg3 *tp)
  2.2319  {
  2.2320 -	u32 val;
  2.2321 -	int i, err;
  2.2322 +	u32 val, rdmac_mode;
  2.2323 +	int i, err, limit;
  2.2324  
  2.2325  	tg3_disable_ints(tp);
  2.2326  
  2.2327 @@ -4003,7 +4595,8 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2328  			break;
  2.2329  		udelay(10);
  2.2330  	}
  2.2331 -	if (i >= 100000) {
  2.2332 +	if (i >= 100000 &&
  2.2333 +	    !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
  2.2334  		printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
  2.2335  		       "firmware will not restart magic=%08x\n",
  2.2336  		       tp->dev->name, val);
  2.2337 @@ -4021,9 +4614,8 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2338  	 * B3 tigon3 silicon.  This bit has no effect on any
  2.2339  	 * other revision.
  2.2340  	 */
  2.2341 -	val = tr32(TG3PCI_CLOCK_CTRL);
  2.2342 -	val |= CLOCK_CTRL_DELAY_PCI_GRANT;
  2.2343 -	tw32(TG3PCI_CLOCK_CTRL, val);
  2.2344 +	tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  2.2345 +	tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  2.2346  	tr32(TG3PCI_CLOCK_CTRL);
  2.2347  
  2.2348  	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  2.2349 @@ -4033,12 +4625,21 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2350  		tw32(TG3PCI_PCISTATE, val);
  2.2351  	}
  2.2352  
  2.2353 +	/* Descriptor ring init may make accesses to the
  2.2354 +	 * NIC SRAM area to setup the TX descriptors, so we
  2.2355 +	 * can only do this after the hardware has been
  2.2356 +	 * successfully reset.
  2.2357 +	 */
  2.2358 +	tg3_init_rings(tp);
  2.2359 +
  2.2360  	/* Clear statistics/status block in chip, and status block in ram. */
  2.2361 -	for (i = NIC_SRAM_STATS_BLK;
  2.2362 -	     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  2.2363 -	     i += sizeof(u32)) {
  2.2364 -		tg3_write_mem(tp, i, 0);
  2.2365 -		udelay(40);
  2.2366 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2367 +		for (i = NIC_SRAM_STATS_BLK;
  2.2368 +	     	     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  2.2369 +	     	     i += sizeof(u32)) {
  2.2370 +			tg3_write_mem(tp, i, 0);
  2.2371 +			udelay(40);
  2.2372 +		}
  2.2373  	}
  2.2374  	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  2.2375  
  2.2376 @@ -4069,13 +4670,31 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2377  	     (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
  2.2378  
  2.2379  	/* Initialize MBUF/DESC pool. */
  2.2380 -	tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  2.2381 -	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.2382 -		tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  2.2383 -	else
  2.2384 -		tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  2.2385 -	tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  2.2386 -	tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  2.2387 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2388 +		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  2.2389 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.2390 +			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  2.2391 +		else
  2.2392 +			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  2.2393 +		tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  2.2394 +		tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  2.2395 +	}
  2.2396 +#if TG3_TSO_SUPPORT != 0
  2.2397 +	else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  2.2398 +		int fw_len;
  2.2399 +
  2.2400 +		fw_len = (TG3_TSO5_FW_TEXT_LEN +
  2.2401 +			  TG3_TSO5_FW_RODATA_LEN +
  2.2402 +			  TG3_TSO5_FW_DATA_LEN +
  2.2403 +			  TG3_TSO5_FW_SBSS_LEN +
  2.2404 +			  TG3_TSO5_FW_BSS_LEN);
  2.2405 +		fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  2.2406 +		tw32(BUFMGR_MB_POOL_ADDR,
  2.2407 +		     NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  2.2408 +		tw32(BUFMGR_MB_POOL_SIZE,
  2.2409 +		     NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  2.2410 +	}
  2.2411 +#endif
  2.2412  
  2.2413  	if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
  2.2414  		tw32(BUFMGR_MB_RDMA_LOW_WATER,
  2.2415 @@ -4122,6 +4741,9 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2416  		return -ENODEV;
  2.2417  	}
  2.2418  
  2.2419 +	/* Setup replenish threshold. */
  2.2420 +	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
  2.2421 +
  2.2422  	/* Initialize TG3_BDINFO's at:
  2.2423  	 *  RCVDBDI_STD_BD:	standard eth size rx ring
  2.2424  	 *  RCVDBDI_JUMBO_BD:	jumbo frame rx ring
  2.2425 @@ -4143,35 +4765,50 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2426  	     ((u64) tp->rx_std_mapping >> 32));
  2.2427  	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2428  	     ((u64) tp->rx_std_mapping & 0xffffffff));
  2.2429 -	tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2430 -	     RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.2431  	tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  2.2432  	     NIC_SRAM_RX_BUFFER_DESC);
  2.2433  
  2.2434 -	tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2435 -	     BDINFO_FLAGS_DISABLED);
  2.2436 -
  2.2437 -	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
  2.2438 -		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.2439 -		     ((u64) tp->rx_jumbo_mapping >> 32));
  2.2440 -		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2441 -		     ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  2.2442 -		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2443 -		     RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.2444 -		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  2.2445 -		     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  2.2446 +	/* Don't even try to program the JUMBO/MINI buffer descriptor
  2.2447 +	 * configs on 5705.
  2.2448 +	 */
  2.2449 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.2450 +		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2451 +		     RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.2452  	} else {
  2.2453 -		tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2454 +		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2455 +		     RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.2456 +
  2.2457 +		tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2458  		     BDINFO_FLAGS_DISABLED);
  2.2459 -	}
  2.2460 -
  2.2461 -	/* Setup replenish thresholds. */
  2.2462 -	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
  2.2463 -	tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  2.2464 -
  2.2465 -	/* Clear out send RCB ring in SRAM. */
  2.2466 -	for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  2.2467 -		tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
  2.2468 +
  2.2469 +		/* Setup replenish threshold. */
  2.2470 +		tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  2.2471 +
  2.2472 +		if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
  2.2473 +			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.2474 +			     ((u64) tp->rx_jumbo_mapping >> 32));
  2.2475 +			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2476 +			     ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  2.2477 +			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2478 +			     RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  2.2479 +			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  2.2480 +			     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  2.2481 +		} else {
  2.2482 +			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  2.2483 +			     BDINFO_FLAGS_DISABLED);
  2.2484 +		}
  2.2485 +
  2.2486 +	}
  2.2487 +
  2.2488 +	/* There is only one send ring on 5705, no need to explicitly
  2.2489 +	 * disable the others.
  2.2490 +	 */
  2.2491 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2492 +		/* Clear out send RCB ring in SRAM. */
  2.2493 +		for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  2.2494 +			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  2.2495 +				      BDINFO_FLAGS_DISABLED);
  2.2496 +	}
  2.2497  
  2.2498  	tp->tx_prod = 0;
  2.2499  	tp->tx_cons = 0;
  2.2500 @@ -4193,9 +4830,15 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2501  			       NIC_SRAM_TX_BUFFER_DESC);
  2.2502  	}
  2.2503  
  2.2504 -	for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
  2.2505 -		tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  2.2506 -			      BDINFO_FLAGS_DISABLED);
  2.2507 +	/* There is only one receive return ring on 5705, no need to explicitly
  2.2508 +	 * disable the others.
  2.2509 +	 */
  2.2510 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2511 +		for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  2.2512 +		     i += TG3_BDINFO_SIZE) {
  2.2513 +			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  2.2514 +				      BDINFO_FLAGS_DISABLED);
  2.2515 +		}
  2.2516  	}
  2.2517  
  2.2518  	tp->rx_rcb_ptr = 0;
  2.2519 @@ -4205,7 +4848,7 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2520  
  2.2521  	tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  2.2522  		       tp->rx_rcb_mapping,
  2.2523 -		       (TG3_RX_RCB_RING_SIZE <<
  2.2524 +		       (TG3_RX_RCB_RING_SIZE(tp) <<
  2.2525  			BDINFO_FLAGS_MAXLEN_SHIFT),
  2.2526  		       0);
  2.2527  
  2.2528 @@ -4242,8 +4885,36 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2529  	tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  2.2530  	tw32(RCVLPC_CONFIG, 0x0181);
  2.2531  
  2.2532 +	/* Calculate RDMAC_MODE setting early, we need it to determine
  2.2533 +	 * the RCVLPC_STATE_ENABLE mask.
  2.2534 +	 */
  2.2535 +	rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  2.2536 +		      RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  2.2537 +		      RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  2.2538 +		      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  2.2539 +		      RDMAC_MODE_LNGREAD_ENAB);
  2.2540 +	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.2541 +		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
  2.2542 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.2543 +		if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  2.2544 +			if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  2.2545 +				rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  2.2546 +			} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  2.2547 +				   !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  2.2548 +				rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  2.2549 +			}
  2.2550 +		}
  2.2551 +	}
  2.2552 +
  2.2553  	/* Receive/send statistics. */
  2.2554 -	tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  2.2555 +	if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  2.2556 +	    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  2.2557 +		val = tr32(RCVLPC_STATS_ENABLE);
  2.2558 +		val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  2.2559 +		tw32(RCVLPC_STATS_ENABLE, val);
  2.2560 +	} else {
  2.2561 +		tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  2.2562 +	}
  2.2563  	tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  2.2564  	tw32(SNDDATAI_STATSENAB, 0xffffff);
  2.2565  	tw32(SNDDATAI_STATSCTRL,
  2.2566 @@ -4259,46 +4930,54 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2567  	}
  2.2568  
  2.2569  #ifdef NAPI
  2.2570 -	tw32(HOSTCC_RXCOL_TICKS, 0);
  2.2571 -	tw32(HOSTCC_RXMAX_FRAMES, 1);
  2.2572 -	tw32(HOSTCC_RXCOAL_TICK_INT, 0);
  2.2573 -	tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
  2.2574 -	tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
  2.2575 -	tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
  2.2576 -	tw32(HOSTCC_TXCOAL_TICK_INT, 0);
  2.2577 -	tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  2.2578 -	tw32(HOSTCC_STAT_COAL_TICKS,
  2.2579 -	     DEFAULT_STAT_COAL_TICKS);
  2.2580 +        tw32(HOSTCC_RXCOL_TICKS, 0);
  2.2581 +        tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
  2.2582 +        tw32(HOSTCC_RXMAX_FRAMES, 1);
  2.2583 +        tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
  2.2584 +        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
  2.2585 +                tw32(HOSTCC_RXCOAL_TICK_INT, 0);
  2.2586 +        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
  2.2587 +                tw32(HOSTCC_TXCOAL_TICK_INT, 0);
  2.2588 +        tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
  2.2589 +        tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  2.2590  #else
  2.2591 -	tw32(HOSTCC_RXCOL_TICKS, DEFAULT_RXCOL_TICKS);
  2.2592 +        tw32(HOSTCC_RXCOL_TICKS, DEFAULT_RXCOL_TICKS);
  2.2593 +        tw32(HOSTCC_TXCOL_TICKS, DEFAULT_TXCOL_TICKS);
  2.2594  	tw32(HOSTCC_RXMAX_FRAMES, DEFAULT_RXMAX_FRAMES);
  2.2595 +        tw32(HOSTCC_TXMAX_FRAMES, DEFAULT_TXMAX_FRAMES);
  2.2596  	tw32(HOSTCC_RXCOAL_TICK_INT, DEFAULT_RXCOAL_TICK_INT);
  2.2597 -	tw32(HOSTCC_RXCOAL_MAXF_INT, DEFAULT_RXCOAL_MAXF_INT);
  2.2598 -	tw32(HOSTCC_TXCOL_TICKS, DEFAULT_TXCOL_TICKS);
  2.2599 -	tw32(HOSTCC_TXMAX_FRAMES, DEFAULT_TXMAX_FRAMES);
  2.2600 -	tw32(HOSTCC_TXCOAL_TICK_INT, DEFAULT_TXCOAL_TICK_INT);
  2.2601 -	tw32(HOSTCC_TXCOAL_MAXF_INT, DEFAULT_TXCOAL_MAXF_INT);
  2.2602 -	tw32(HOSTCC_STAT_COAL_TICKS,
  2.2603 -	     DEFAULT_STAT_COAL_TICKS);
  2.2604 +        tw32(HOSTCC_TXCOAL_TICK_INT, DEFAULT_TXCOAL_TICK_INT);
  2.2605 +        tw32(HOSTCC_RXCOAL_MAXF_INT, DEFAULT_RXCOAL_MAXF_INT);
  2.2606 +        tw32(HOSTCC_TXCOAL_MAXF_INT, DEFAULT_TXCOAL_MAXF_INT);
  2.2607  #endif
  2.2608  
  2.2609 -	/* Status/statistics block address. */
  2.2610 -	tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.2611 -	     ((u64) tp->stats_mapping >> 32));
  2.2612 -	tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2613 -	     ((u64) tp->stats_mapping & 0xffffffff));
  2.2614 +	/* set status block DMA address */
  2.2615  	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.2616  	     ((u64) tp->status_mapping >> 32));
  2.2617  	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2618  	     ((u64) tp->status_mapping & 0xffffffff));
  2.2619 -	tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  2.2620 -	tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  2.2621 +
  2.2622 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2623 +		/* Status/statistics block address.  See tg3_timer,
  2.2624 +		 * the tg3_periodic_fetch_stats call there, and
  2.2625 +		 * tg3_get_stats to see how this works for 5705 chips.
  2.2626 +		 */
  2.2627 +		tw32(HOSTCC_STAT_COAL_TICKS,
  2.2628 +		     DEFAULT_STAT_COAL_TICKS);
  2.2629 +		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  2.2630 +		     ((u64) tp->stats_mapping >> 32));
  2.2631 +		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  2.2632 +		     ((u64) tp->stats_mapping & 0xffffffff));
  2.2633 +		tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  2.2634 +		tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  2.2635 +	}
  2.2636  
  2.2637  	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  2.2638  
  2.2639  	tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  2.2640  	tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  2.2641 -	tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  2.2642 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
  2.2643 +		tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  2.2644  
  2.2645  	tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  2.2646  		MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  2.2647 @@ -4317,42 +4996,47 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2648  	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  2.2649  	tr32(MAILBOX_INTERRUPT_0);
  2.2650  
  2.2651 -	tw32(DMAC_MODE, DMAC_MODE_ENABLE);
  2.2652 -	tr32(DMAC_MODE);
  2.2653 -	udelay(40);
  2.2654 -
  2.2655 -	tw32(WDMAC_MODE, (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  2.2656 -			  WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  2.2657 -			  WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  2.2658 -			  WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  2.2659 -			  WDMAC_MODE_LNGREAD_ENAB));
  2.2660 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  2.2661 +		tw32(DMAC_MODE, DMAC_MODE_ENABLE);
  2.2662 +		tr32(DMAC_MODE);
  2.2663 +		udelay(40);
  2.2664 +	}
  2.2665 +
  2.2666 +	val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  2.2667 +	       WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  2.2668 +	       WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  2.2669 +	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  2.2670 +	       WDMAC_MODE_LNGREAD_ENAB);
  2.2671 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  2.2672 +	    (tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0 &&
  2.2673 +	    !(tp->tg3_flags2 & TG3_FLG2_IS_5788))
  2.2674 +		val |= WDMAC_MODE_RX_ACCEL;
  2.2675 +	tw32(WDMAC_MODE, val);
  2.2676  	tr32(WDMAC_MODE);
  2.2677  	udelay(40);
  2.2678  
  2.2679 -	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  2.2680 -	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  2.2681 +	if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
  2.2682  		val = tr32(TG3PCI_X_CAPS);
  2.2683 -		val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
  2.2684 -		val |= (PCIX_CAPS_MAX_BURST_5704 << PCIX_CAPS_BURST_SHIFT);
  2.2685 -		if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.2686 -			val |= (tp->split_mode_max_reqs <<
  2.2687 -				PCIX_CAPS_SPLIT_SHIFT);
  2.2688 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  2.2689 +			val &= ~PCIX_CAPS_BURST_MASK;
  2.2690 +			val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  2.2691 +		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  2.2692 +			val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
  2.2693 +			val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  2.2694 +			if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.2695 +				val |= (tp->split_mode_max_reqs <<
  2.2696 +					PCIX_CAPS_SPLIT_SHIFT);
  2.2697 +		}
  2.2698  		tw32(TG3PCI_X_CAPS, val);
  2.2699  	}
  2.2700  
  2.2701 -	val = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  2.2702 -	       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  2.2703 -	       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  2.2704 -	       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  2.2705 -	       RDMAC_MODE_LNGREAD_ENAB);
  2.2706 -	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
  2.2707 -		val |= RDMAC_MODE_SPLIT_ENABLE;
  2.2708 -	tw32(RDMAC_MODE, val);
  2.2709 +	tw32(RDMAC_MODE, rdmac_mode);
  2.2710  	tr32(RDMAC_MODE);
  2.2711  	udelay(40);
  2.2712  
  2.2713  	tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  2.2714 -	tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  2.2715 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)
  2.2716 +		tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  2.2717  	tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  2.2718  	tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  2.2719  	tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  2.2720 @@ -4367,10 +5051,12 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2721  			return err;
  2.2722  	}
  2.2723  
  2.2724 -#if TG3_DO_TSO != 0
  2.2725 -	err = tg3_load_tso_firmware(tp);
  2.2726 -	if (err)
  2.2727 -		return err;
  2.2728 +#if TG3_TSO_SUPPORT != 0
  2.2729 +	if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  2.2730 +		err = tg3_load_tso_firmware(tp);
  2.2731 +		if (err)
  2.2732 +			return err;
  2.2733 +	}
  2.2734  #endif
  2.2735  
  2.2736  	tp->tx_mode = TX_MODE_ENABLE;
  2.2737 @@ -4397,9 +5083,11 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2738  
  2.2739  	tw32(MAC_LED_CTRL, 0);
  2.2740  	tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  2.2741 -	tw32(MAC_RX_MODE, RX_MODE_RESET);
  2.2742 -	tr32(MAC_RX_MODE);
  2.2743 -	udelay(10);
  2.2744 +	if (tp->phy_id == PHY_ID_SERDES) {
  2.2745 +		tw32(MAC_RX_MODE, RX_MODE_RESET);
  2.2746 +		tr32(MAC_RX_MODE);
  2.2747 +		udelay(10);
  2.2748 +	}
  2.2749  	tw32(MAC_RX_MODE, tp->rx_mode);
  2.2750  	tr32(MAC_RX_MODE);
  2.2751  	udelay(10);
  2.2752 @@ -4433,22 +5121,48 @@ static int tg3_reset_hw(struct tg3 *tp)
  2.2753  	tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  2.2754  	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
  2.2755  	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  2.2756 -#if 0
  2.2757 -	tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0);
  2.2758 -	tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0);
  2.2759 -#endif
  2.2760 -	tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
  2.2761 -	tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
  2.2762 -	tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
  2.2763 -	tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
  2.2764 -	tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
  2.2765 -	tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
  2.2766 -	tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
  2.2767 -	tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
  2.2768 -	tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
  2.2769 -	tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
  2.2770 -	tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
  2.2771 -	tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
  2.2772 +
  2.2773 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.2774 +		limit = 8;
  2.2775 +	else
  2.2776 +		limit = 16;
  2.2777 +	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  2.2778 +		limit -= 4;
  2.2779 +	switch (limit) {
  2.2780 +	case 16:
  2.2781 +		tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
  2.2782 +	case 15:
  2.2783 +		tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
  2.2784 +	case 14:
  2.2785 +		tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
  2.2786 +	case 13:
  2.2787 +		tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
  2.2788 +	case 12:
  2.2789 +		tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
  2.2790 +	case 11:
  2.2791 +		tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
  2.2792 +	case 10:
  2.2793 +		tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
  2.2794 +	case 9:
  2.2795 +		tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
  2.2796 +	case 8:
  2.2797 +		tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
  2.2798 +	case 7:
  2.2799 +		tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
  2.2800 +	case 6:
  2.2801 +		tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
  2.2802 +	case 5:
  2.2803 +		tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
  2.2804 +	case 4:
  2.2805 +		/* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
  2.2806 +	case 3:
  2.2807 +		/* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
  2.2808 +	case 2:
  2.2809 +	case 1:
  2.2810 +
  2.2811 +	default:
  2.2812 +		break;
  2.2813 +	};
  2.2814  
  2.2815  	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
  2.2816  		tg3_enable_ints(tp);
  2.2817 @@ -4478,6 +5192,50 @@ out:
  2.2818  	return err;
  2.2819  }
  2.2820  
  2.2821 +#define TG3_STAT_ADD32(PSTAT, REG) \
  2.2822 +do {	u32 __val = tr32(REG); \
  2.2823 +	(PSTAT)->low += __val; \
  2.2824 +	if ((PSTAT)->low < __val) \
  2.2825 +		(PSTAT)->high += 1; \
  2.2826 +} while (0)
  2.2827 +
  2.2828 +static void tg3_periodic_fetch_stats(struct tg3 *tp)
  2.2829 +{
  2.2830 +	struct tg3_hw_stats *sp = tp->hw_stats;
  2.2831 +
  2.2832 +	if (!netif_carrier_ok(tp->dev))
  2.2833 +		return;
  2.2834 +
  2.2835 +	TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  2.2836 +	TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  2.2837 +	TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  2.2838 +	TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  2.2839 +	TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  2.2840 +	TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  2.2841 +	TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  2.2842 +	TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  2.2843 +	TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  2.2844 +	TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  2.2845 +	TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  2.2846 +	TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  2.2847 +	TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  2.2848 +
  2.2849 +	TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  2.2850 +	TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  2.2851 +	TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  2.2852 +	TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  2.2853 +	TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  2.2854 +	TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  2.2855 +	TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  2.2856 +	TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  2.2857 +	TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  2.2858 +	TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  2.2859 +	TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  2.2860 +	TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  2.2861 +	TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  2.2862 +	TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  2.2863 +}
  2.2864 +
  2.2865  static void tg3_timer(unsigned long __opaque)
  2.2866  {
  2.2867  	struct tg3 *tp = (struct tg3 *) __opaque;
  2.2868 @@ -4502,16 +5260,14 @@ static void tg3_timer(unsigned long __op
  2.2869  		tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  2.2870  		spin_unlock(&tp->tx_lock);
  2.2871  		spin_unlock_irqrestore(&tp->lock, flags);
  2.2872 -#if 0
  2.2873 -		schedule_task(&tp->reset_task);
  2.2874 -#else
  2.2875 -                tg3_halt(tp);
  2.2876 -                tg3_init_rings(tp);
  2.2877 -                tg3_init_hw(tp);
  2.2878 -#endif
  2.2879 +		//schedule_task(&tp->reset_task);
  2.2880 +		tg3_reset_task(tp);
  2.2881  		return;
  2.2882  	}
  2.2883  
  2.2884 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.2885 +		tg3_periodic_fetch_stats(tp);
  2.2886 +
  2.2887  	/* This part only runs once per second. */
  2.2888  	if (!--tp->timer_counter) {
  2.2889  		if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  2.2890 @@ -4611,8 +5367,6 @@ static int tg3_open(struct net_device *d
  2.2891  	spin_lock_irq(&tp->lock);
  2.2892  	spin_lock(&tp->tx_lock);
  2.2893  
  2.2894 -	tg3_init_rings(tp);
  2.2895 -
  2.2896  	err = tg3_init_hw(tp);
  2.2897  	if (err) {
  2.2898  		tg3_halt(tp);
  2.2899 @@ -4971,7 +5725,9 @@ static struct net_device_stats *tg3_get_
  2.2900  		get_stat64(&hw_stats->rx_bcast_packets);
  2.2901  		
  2.2902  	stats->tx_packets = old_stats->tx_packets +
  2.2903 -		get_stat64(&hw_stats->COS_out_packets[0]);
  2.2904 +		get_stat64(&hw_stats->tx_ucast_packets) +
  2.2905 +		get_stat64(&hw_stats->tx_mcast_packets) +
  2.2906 +		get_stat64(&hw_stats->tx_bcast_packets);
  2.2907  
  2.2908  	stats->rx_bytes = old_stats->rx_bytes +
  2.2909  		get_stat64(&hw_stats->rx_octets);
  2.2910 @@ -5114,16 +5870,20 @@ static void tg3_set_rx_mode(struct net_d
  2.2911  
  2.2912  #define TG3_REGDUMP_LEN		(32 * 1024)
  2.2913  
  2.2914 -static u8 *tg3_get_regs(struct tg3 *tp)
  2.2915 +static int tg3_get_regs_len(struct net_device *dev)
  2.2916  {
  2.2917 -	u8 *orig_p = kmalloc(TG3_REGDUMP_LEN, GFP_KERNEL);
  2.2918 -	u8 *p;
  2.2919 +	return TG3_REGDUMP_LEN;
  2.2920 +}
  2.2921 +
  2.2922 +static void tg3_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
  2.2923 +{
  2.2924 +	struct tg3 *tp = dev->priv;
  2.2925 +	u8 *orig_p = p;
  2.2926  	int i;
  2.2927  
  2.2928 -	if (orig_p == NULL)
  2.2929 -		return NULL;
  2.2930 -
  2.2931 -	memset(orig_p, 0, TG3_REGDUMP_LEN);
  2.2932 +	regs->version = 0;
  2.2933 +
  2.2934 +	memset(p, 0, TG3_REGDUMP_LEN);
  2.2935  
  2.2936  	spin_lock_irq(&tp->lock);
  2.2937  	spin_lock(&tp->tx_lock);
  2.2938 @@ -5177,390 +5937,283 @@ do {	p = orig_p + (reg);	\
  2.2939  
  2.2940  	spin_unlock(&tp->tx_lock);
  2.2941  	spin_unlock_irq(&tp->lock);
  2.2942 -
  2.2943 -	return orig_p;
  2.2944 +}
  2.2945 +
  2.2946 +static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2.2947 +{
  2.2948 +  	struct tg3 *tp = dev->priv;
  2.2949 +  
  2.2950 +	if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.2951 +					tp->link_config.phy_is_low_power)
  2.2952 +		return -EAGAIN;
  2.2953 +
  2.2954 +	cmd->supported = (SUPPORTED_Autoneg);
  2.2955 +
  2.2956 +	if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  2.2957 +		cmd->supported |= (SUPPORTED_1000baseT_Half |
  2.2958 +				   SUPPORTED_1000baseT_Full);
  2.2959 +
  2.2960 +	if (tp->phy_id != PHY_ID_SERDES)
  2.2961 +		cmd->supported |= (SUPPORTED_100baseT_Half |
  2.2962 +				  SUPPORTED_100baseT_Full |
  2.2963 +				  SUPPORTED_10baseT_Half |
  2.2964 +				  SUPPORTED_10baseT_Full |
  2.2965 +				  SUPPORTED_MII);
  2.2966 +	else
  2.2967 +		cmd->supported |= SUPPORTED_FIBRE;
  2.2968 +  
  2.2969 +	cmd->advertising = tp->link_config.advertising;
  2.2970 +	cmd->speed = tp->link_config.active_speed;
  2.2971 +	cmd->duplex = tp->link_config.active_duplex;
  2.2972 +	cmd->port = 0;
  2.2973 +	cmd->phy_address = PHY_ADDR;
  2.2974 +	cmd->transceiver = 0;
  2.2975 +	cmd->autoneg = tp->link_config.autoneg;
  2.2976 +	cmd->maxtxpkt = 0;
  2.2977 +	cmd->maxrxpkt = 0;
  2.2978 +	return 0;
  2.2979 +}
  2.2980 +  
  2.2981 +static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2.2982 +{
  2.2983 +	struct tg3 *tp = dev->priv;
  2.2984 +  
  2.2985 +	if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.2986 +					tp->link_config.phy_is_low_power)
  2.2987 +		return -EAGAIN;
  2.2988 +
  2.2989 +	spin_lock_irq(&tp->lock);
  2.2990 +	spin_lock(&tp->tx_lock);
  2.2991 +
  2.2992 +	tp->link_config.autoneg = cmd->autoneg;
  2.2993 +	if (cmd->autoneg == AUTONEG_ENABLE) {
  2.2994 +		tp->link_config.advertising = cmd->advertising;
  2.2995 +		tp->link_config.speed = SPEED_INVALID;
  2.2996 +		tp->link_config.duplex = DUPLEX_INVALID;
  2.2997 +	} else {
  2.2998 +		tp->link_config.speed = cmd->speed;
  2.2999 +		tp->link_config.duplex = cmd->duplex;
  2.3000 +  	}
  2.3001 +  
  2.3002 +	tg3_setup_phy(tp);
  2.3003 +	spin_unlock(&tp->tx_lock);
  2.3004 +	spin_unlock_irq(&tp->lock);
  2.3005 +  
  2.3006 +	return 0;
  2.3007  }
  2.3008 -
  2.3009 -static int tg3_ethtool_ioctl (struct net_device *dev, void *useraddr)
  2.3010 +  
  2.3011 +static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  2.3012 +{
  2.3013 +	struct tg3 *tp = dev->priv;
  2.3014 +  
  2.3015 +	strcpy(info->driver, DRV_MODULE_NAME);
  2.3016 +	strcpy(info->version, DRV_MODULE_VERSION);
  2.3017 +	strcpy(info->bus_info, pci_name(tp->pdev));
  2.3018 +}
  2.3019 +  
  2.3020 +static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2.3021 +{
  2.3022 +	struct tg3 *tp = dev->priv;
  2.3023 +  
  2.3024 +	wol->supported = WAKE_MAGIC;
  2.3025 +	wol->wolopts = 0;
  2.3026 +	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  2.3027 +		wol->wolopts = WAKE_MAGIC;
  2.3028 +	memset(&wol->sopass, 0, sizeof(wol->sopass));
  2.3029 +}
  2.3030 +  
  2.3031 +static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2.3032 +{
  2.3033 +	struct tg3 *tp = dev->priv;
  2.3034 +  
  2.3035 +	if (wol->wolopts & ~WAKE_MAGIC)
  2.3036 +		return -EINVAL;
  2.3037 +	if ((wol->wolopts & WAKE_MAGIC) &&
  2.3038 +	    tp->phy_id == PHY_ID_SERDES &&
  2.3039 +	    !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
  2.3040 +		return -EINVAL;
  2.3041 +  
  2.3042 +	spin_lock_irq(&tp->lock);
  2.3043 +	if (wol->wolopts & WAKE_MAGIC)
  2.3044 +		tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  2.3045 +	else
  2.3046 +		tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  2.3047 +	spin_unlock_irq(&tp->lock);
  2.3048 +  
  2.3049 +	return 0;
  2.3050 +}
  2.3051 +  
  2.3052 +static u32 tg3_get_msglevel(struct net_device *dev)
  2.3053 +{
  2.3054 +	struct tg3 *tp = dev->priv;
  2.3055 +	return tp->msg_enable;
  2.3056 +}
  2.3057 +  
  2.3058 +static void tg3_set_msglevel(struct net_device *dev, u32 value)
  2.3059 +{
  2.3060 +	struct tg3 *tp = dev->priv;
  2.3061 +	tp->msg_enable = value;
  2.3062 +}
  2.3063 +  
  2.3064 +#if TG3_TSO_SUPPORT != 0
  2.3065 +static int tg3_set_tso(struct net_device *dev, u32 value)
  2.3066 +{
  2.3067 +	struct tg3 *tp = dev->priv;
  2.3068 +
  2.3069 +	if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  2.3070 +		if (value)
  2.3071 +			return -EINVAL;
  2.3072 +		return 0;
  2.3073 +	}
  2.3074 +	return ethtool_op_set_tso(dev, value);
  2.3075 +}
  2.3076 +#endif
  2.3077 +  
  2.3078 +static int tg3_nway_reset(struct net_device *dev)
  2.3079  {
  2.3080  	struct tg3 *tp = dev->priv;
  2.3081 -	struct pci_dev *pci_dev = tp->pdev;
  2.3082 -	u32 ethcmd;
  2.3083 -
  2.3084 -	if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
  2.3085 -		return -EFAULT;
  2.3086 -
  2.3087 -	switch (ethcmd) {
  2.3088 -	case ETHTOOL_GDRVINFO:{
  2.3089 -		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
  2.3090 -		strcpy (info.driver, DRV_MODULE_NAME);
  2.3091 -		strcpy (info.version, DRV_MODULE_VERSION);
  2.3092 -		memset(&info.fw_version, 0, sizeof(info.fw_version));
  2.3093 -		strcpy (info.bus_info, pci_dev->slot_name);
  2.3094 -		info.eedump_len = 0;
  2.3095 -		info.regdump_len = TG3_REGDUMP_LEN;
  2.3096 -		if (copy_to_user (useraddr, &info, sizeof (info)))
  2.3097 -			return -EFAULT;
  2.3098 -		return 0;
  2.3099 -	}
  2.3100 -
  2.3101 -	case ETHTOOL_GSET: {
  2.3102 -		struct ethtool_cmd cmd = { ETHTOOL_GSET };
  2.3103 -
  2.3104 -		if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.3105 -		    tp->link_config.phy_is_low_power)
  2.3106 -			return -EAGAIN;
  2.3107 -		cmd.supported = (SUPPORTED_Autoneg);
  2.3108 -
  2.3109 -		if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  2.3110 -			cmd.supported |= (SUPPORTED_1000baseT_Half |
  2.3111 -					  SUPPORTED_1000baseT_Full);
  2.3112 -
  2.3113 -		if (tp->phy_id != PHY_ID_SERDES)
  2.3114 -			cmd.supported |= (SUPPORTED_100baseT_Half |
  2.3115 -					  SUPPORTED_100baseT_Full |
  2.3116 -					  SUPPORTED_10baseT_Half |
  2.3117 -					  SUPPORTED_10baseT_Full |
  2.3118 -					  SUPPORTED_MII);
  2.3119 -		else
  2.3120 -			cmd.supported |= SUPPORTED_FIBRE;
  2.3121 -
  2.3122 -		cmd.advertising = tp->link_config.advertising;
  2.3123 -		cmd.speed = tp->link_config.active_speed;
  2.3124 -		cmd.duplex = tp->link_config.active_duplex;
  2.3125 -		cmd.port = 0;
  2.3126 -		cmd.phy_address = PHY_ADDR;
  2.3127 -		cmd.transceiver = 0;
  2.3128 -		cmd.autoneg = tp->link_config.autoneg;
  2.3129 -		cmd.maxtxpkt = 0;
  2.3130 -		cmd.maxrxpkt = 0;
  2.3131 -		if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
  2.3132 -			return -EFAULT;
  2.3133 -		return 0;
  2.3134 -	}
  2.3135 -	case ETHTOOL_SSET: {
  2.3136 -		struct ethtool_cmd cmd;
  2.3137 -
  2.3138 -		if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
  2.3139 -		    tp->link_config.phy_is_low_power)
  2.3140 -			return -EAGAIN;
  2.3141 -
  2.3142 -		if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
  2.3143 -			return -EFAULT;
  2.3144 -
  2.3145 -		/* Fiber PHY only supports 1000 full/half */
  2.3146 -		if (cmd.autoneg == AUTONEG_ENABLE) {
  2.3147 -			if (tp->phy_id == PHY_ID_SERDES &&
  2.3148 -			    (cmd.advertising &
  2.3149 -			     (ADVERTISED_10baseT_Half |
  2.3150 -			      ADVERTISED_10baseT_Full |
  2.3151 -			      ADVERTISED_100baseT_Half |
  2.3152 -			      ADVERTISED_100baseT_Full)))
  2.3153 -				return -EINVAL;
  2.3154 -			if ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  2.3155 -			    (cmd.advertising &
  2.3156 -			     (ADVERTISED_1000baseT_Half |
  2.3157 -			      ADVERTISED_1000baseT_Full)))
  2.3158 -				return -EINVAL;
  2.3159 -		} else {
  2.3160 -			if (tp->phy_id == PHY_ID_SERDES &&
  2.3161 -			    (cmd.speed == SPEED_10 ||
  2.3162 -			     cmd.speed == SPEED_100))
  2.3163 -				return -EINVAL;
  2.3164 -			if ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  2.3165 -			    (cmd.speed == SPEED_10 ||
  2.3166 -			     cmd.speed == SPEED_100))
  2.3167 -				return -EINVAL;
  2.3168 -		}
  2.3169 -
  2.3170 -		spin_lock_irq(&tp->lock);
  2.3171 -		spin_lock(&tp->tx_lock);
  2.3172 -
  2.3173 -		tp->link_config.autoneg = cmd.autoneg;
  2.3174 -		if (cmd.autoneg == AUTONEG_ENABLE) {
  2.3175 -			tp->link_config.advertising = cmd.advertising;
  2.3176 -			tp->link_config.speed = SPEED_INVALID;
  2.3177 -			tp->link_config.duplex = DUPLEX_INVALID;
  2.3178 -		} else {
  2.3179 -			tp->link_config.speed = cmd.speed;
  2.3180 -			tp->link_config.duplex = cmd.duplex;
  2.3181 -		}
  2.3182 -
  2.3183 -		tg3_setup_phy(tp);
  2.3184 -		spin_unlock(&tp->tx_lock);
  2.3185 -		spin_unlock_irq(&tp->lock);
  2.3186 -
  2.3187 -		return 0;
  2.3188 -	}
  2.3189 -
  2.3190 -	case ETHTOOL_GREGS: {
  2.3191 -		struct ethtool_regs regs;
  2.3192 -		u8 *regbuf;
  2.3193 -		int ret;
  2.3194 -
  2.3195 -		if (copy_from_user(&regs, useraddr, sizeof(regs)))
  2.3196 -			return -EFAULT;
  2.3197 -		if (regs.len > TG3_REGDUMP_LEN)
  2.3198 -			regs.len = TG3_REGDUMP_LEN;
  2.3199 -		regs.version = 0;
  2.3200 -		if (copy_to_user(useraddr, &regs, sizeof(regs)))
  2.3201 -			return -EFAULT;
  2.3202 -
  2.3203 -		regbuf = tg3_get_regs(tp);
  2.3204 -		if (!regbuf)
  2.3205 -			return -ENOMEM;
  2.3206 -
  2.3207 -		useraddr += offsetof(struct ethtool_regs, data);
  2.3208 -		ret = 0;
  2.3209 -		if (copy_to_user(useraddr, regbuf, regs.len))
  2.3210 -			ret = -EFAULT;
  2.3211 -		kfree(regbuf);
  2.3212 -		return ret;
  2.3213 -	}
  2.3214 -	case ETHTOOL_GWOL: {
  2.3215 -		struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
  2.3216 -
  2.3217 -		wol.supported = WAKE_MAGIC;
  2.3218 -		wol.wolopts = 0;
  2.3219 -		if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  2.3220 -			wol.wolopts = WAKE_MAGIC;
  2.3221 -		memset(&wol.sopass, 0, sizeof(wol.sopass));
  2.3222 -		if (copy_to_user(useraddr, &wol, sizeof(wol)))
  2.3223 -			return -EFAULT;
  2.3224 -		return 0;
  2.3225 -	}
  2.3226 -	case ETHTOOL_SWOL: {
  2.3227 -		struct ethtool_wolinfo wol;
  2.3228 -
  2.3229 -		if (copy_from_user(&wol, useraddr, sizeof(wol)))
  2.3230 -			return -EFAULT;
  2.3231 -		if (wol.wolopts & ~WAKE_MAGIC)
  2.3232 -			return -EINVAL;
  2.3233 -		if ((wol.wolopts & WAKE_MAGIC) &&
  2.3234 -		    tp->phy_id == PHY_ID_SERDES &&
  2.3235 -		    !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
  2.3236 +	u32 bmcr;
  2.3237 +	int r;
  2.3238 +  
  2.3239 +	spin_lock_irq(&tp->lock);
  2.3240 +	tg3_readphy(tp, MII_BMCR, &bmcr);
  2.3241 +	tg3_readphy(tp, MII_BMCR, &bmcr);
  2.3242 +	r = -EINVAL;
  2.3243 +	if (bmcr & BMCR_ANENABLE) {
  2.3244 +		tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
  2.3245 +		r = 0;
  2.3246 +	}
  2.3247 +	spin_unlock_irq(&tp->lock);
  2.3248 +  
  2.3249 +	return r;
  2.3250 +}
  2.3251 +  
  2.3252 +static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  2.3253 +{
  2.3254 +	struct tg3 *tp = dev->priv;
  2.3255 +  
  2.3256 +	ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  2.3257 +	ering->rx_mini_max_pending = 0;
  2.3258 +	ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  2.3259 +
  2.3260 +	ering->rx_pending = tp->rx_pending;
  2.3261 +	ering->rx_mini_pending = 0;
  2.3262 +	ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  2.3263 +	ering->tx_pending = tp->tx_pending;
  2.3264 +}
  2.3265 +  
  2.3266 +static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  2.3267 +{
  2.3268 +	struct tg3 *tp = dev->priv;
  2.3269 +  
  2.3270 +	if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  2.3271 +	    (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  2.3272 +	    (ering->tx_pending > TG3_TX_RING_SIZE - 1))
  2.3273 +		return -EINVAL;
  2.3274 +  
  2.3275 +	tg3_netif_stop(tp);
  2.3276 +	spin_lock_irq(&tp->lock);
  2.3277 +	spin_lock(&tp->tx_lock);
  2.3278 +  
  2.3279 +	tp->rx_pending = ering->rx_pending;
  2.3280 +
  2.3281 +	if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  2.3282 +	    tp->rx_pending > 63)
  2.3283 +		tp->rx_pending = 63;
  2.3284 +	tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  2.3285 +	tp->tx_pending = ering->tx_pending;
  2.3286 +
  2.3287 +	tg3_halt(tp);
  2.3288 +	tg3_init_hw(tp);
  2.3289 +	netif_wake_queue(tp->dev);
  2.3290 +	spin_unlock(&tp->tx_lock);
  2.3291 +	spin_unlock_irq(&tp->lock);
  2.3292 +	tg3_netif_start(tp);
  2.3293 +  
  2.3294 +	return 0;
  2.3295 +}
  2.3296 +  
  2.3297 +static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  2.3298 +{
  2.3299 +	struct tg3 *tp = dev->priv;
  2.3300 +  
  2.3301 +	epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  2.3302 +	epause->rx_pause = (tp->tg3_flags & TG3_FLAG_PAUSE_RX) != 0;
  2.3303 +	epause->tx_pause = (tp->tg3_flags & TG3_FLAG_PAUSE_TX) != 0;
  2.3304 +}
  2.3305 +  
  2.3306 +static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  2.3307 +{
  2.3308 +	struct tg3 *tp = dev->priv;
  2.3309 +  
  2.3310 +	tg3_netif_stop(tp);
  2.3311 +	spin_lock_irq(&tp->lock);
  2.3312 +	spin_lock(&tp->tx_lock);
  2.3313 +	if (epause->autoneg)
  2.3314 +		tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  2.3315 +	else
  2.3316 +		tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  2.3317 +	if (epause->rx_pause)
  2.3318 +		tp->tg3_flags |= TG3_FLAG_PAUSE_RX;
  2.3319 +	else
  2.3320 +		tp->tg3_flags &= ~TG3_FLAG_PAUSE_RX;
  2.3321 +	if (epause->tx_pause)
  2.3322 +		tp->tg3_flags |= TG3_FLAG_PAUSE_TX;
  2.3323 +	else
  2.3324 +		tp->tg3_flags &= ~TG3_FLAG_PAUSE_TX;
  2.3325 +	tg3_halt(tp);
  2.3326 +	tg3_init_hw(tp);
  2.3327 +	spin_unlock(&tp->tx_lock);
  2.3328 +	spin_unlock_irq(&tp->lock);
  2.3329 +	tg3_netif_start(tp);
  2.3330 +  
  2.3331 +	return 0;
  2.3332 +}
  2.3333 +  
  2.3334 +static u32 tg3_get_rx_csum(struct net_device *dev)
  2.3335 +{
  2.3336 +	struct tg3 *tp = dev->priv;
  2.3337 +	return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  2.3338 +}
  2.3339 +  
  2.3340 +static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  2.3341 +{
  2.3342 +	struct tg3 *tp = dev->priv;
  2.3343 +  
  2.3344 +	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.3345 +		if (data != 0)
  2.3346  			return -EINVAL;
  2.3347 -
  2.3348 -		spin_lock_irq(&tp->lock);
  2.3349 -		if (wol.wolopts & WAKE_MAGIC)
  2.3350 -			tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  2.3351 -		else
  2.3352 -			tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  2.3353 -		spin_unlock_irq(&tp->lock);
  2.3354 -
  2.3355 -		return 0;
  2.3356 -	}
  2.3357 -	case ETHTOOL_GMSGLVL: {
  2.3358 -		struct ethtool_value edata = { ETHTOOL_GMSGLVL };
  2.3359 -		edata.data = tp->msg_enable;
  2.3360 -		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.3361 -			return -EFAULT;
  2.3362 -		return 0;
  2.3363 -	}
  2.3364 -	case ETHTOOL_SMSGLVL: {
  2.3365 -		struct ethtool_value edata;
  2.3366 -		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.3367 -			return -EFAULT;
  2.3368 -		tp->msg_enable = edata.data;
  2.3369 -		return 0;
  2.3370 -	}
  2.3371 -	case ETHTOOL_NWAY_RST: {
  2.3372 -		u32 bmcr;
  2.3373 -		int r;
  2.3374 -
  2.3375 -		spin_lock_irq(&tp->lock);
  2.3376 -		tg3_readphy(tp, MII_BMCR, &bmcr);
  2.3377 -		tg3_readphy(tp, MII_BMCR, &bmcr);
  2.3378 -		r = -EINVAL;
  2.3379 -		if (bmcr & BMCR_ANENABLE) {
  2.3380 -			tg3_writephy(tp, MII_BMCR,
  2.3381 -				     bmcr | BMCR_ANRESTART);
  2.3382 -			r = 0;
  2.3383 -		}
  2.3384 -		spin_unlock_irq(&tp->lock);
  2.3385 -
  2.3386 -		return r;
  2.3387 -	}
  2.3388 -	case ETHTOOL_GLINK: {
  2.3389 -		struct ethtool_value edata = { ETHTOOL_GLINK };
  2.3390 -		edata.data = netif_carrier_ok(tp->dev) ? 1 : 0;
  2.3391 -		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.3392 -			return -EFAULT;
  2.3393 -		return 0;
  2.3394 -	}
  2.3395 -	case ETHTOOL_GRINGPARAM: {
  2.3396 -		struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
  2.3397 -
  2.3398 -		ering.rx_max_pending = TG3_RX_RING_SIZE - 1;
  2.3399 -		ering.rx_mini_max_pending = 0;
  2.3400 -		ering.rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  2.3401 -
  2.3402 -		ering.rx_pending = tp->rx_pending;
  2.3403 -		ering.rx_mini_pending = 0;
  2.3404 -		ering.rx_jumbo_pending = tp->rx_jumbo_pending;
  2.3405 -		ering.tx_pending = tp->tx_pending;
  2.3406 -
  2.3407 -		if (copy_to_user(useraddr, &ering, sizeof(ering)))
  2.3408 -			return -EFAULT;
  2.3409 -		return 0;
  2.3410 -	}
  2.3411 -	case ETHTOOL_SRINGPARAM: {
  2.3412 -		struct ethtool_ringparam ering;
  2.3413 -
  2.3414 -		if (copy_from_user(&ering, useraddr, sizeof(ering)))
  2.3415 -			return -EFAULT;
  2.3416 -
  2.3417 -		if ((ering.rx_pending > TG3_RX_RING_SIZE - 1) ||
  2.3418 -		    (ering.rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  2.3419 -		    (ering.tx_pending > TG3_TX_RING_SIZE - 1))
  2.3420 +  		return 0;
  2.3421 +  	}
  2.3422 +  
  2.3423 +	spin_lock_irq(&tp->lock);
  2.3424 +	if (data)
  2.3425 +		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  2.3426 +	else
  2.3427 +		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  2.3428 +	spin_unlock_irq(&tp->lock);
  2.3429 +  
  2.3430 +	return 0;
  2.3431 +}
  2.3432 +  
  2.3433 +static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  2.3434 +{
  2.3435 +	struct tg3 *tp = dev->priv;
  2.3436 +  
  2.3437 +	if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.3438 +		if (data != 0)
  2.3439  			return -EINVAL;
  2.3440 -
  2.3441 -		tg3_netif_stop(tp);
  2.3442 -		spin_lock_irq(&tp->lock);
  2.3443 -		spin_lock(&tp->tx_lock);
  2.3444 -
  2.3445 -		tp->rx_pending = ering.rx_pending;
  2.3446 -		tp->rx_jumbo_pending = ering.rx_jumbo_pending;
  2.3447 -		tp->tx_pending = ering.tx_pending;
  2.3448 -
  2.3449 -		tg3_halt(tp);
  2.3450 -		tg3_init_rings(tp);
  2.3451 -		tg3_init_hw(tp);
  2.3452 -		netif_wake_queue(tp->dev);
  2.3453 -		spin_unlock(&tp->tx_lock);
  2.3454 -		spin_unlock_irq(&tp->lock);
  2.3455 -		tg3_netif_start(tp);
  2.3456 -
  2.3457 -		return 0;
  2.3458 -	}
  2.3459 -	case ETHTOOL_GPAUSEPARAM: {
  2.3460 -		struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
  2.3461 -
  2.3462 -		epause.autoneg =
  2.3463 -			(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  2.3464 -		epause.rx_pause =
  2.3465 -			(tp->tg3_flags & TG3_FLAG_PAUSE_RX) != 0;
  2.3466 -		epause.tx_pause =
  2.3467 -			(tp->tg3_flags & TG3_FLAG_PAUSE_TX) != 0;
  2.3468 -		if (copy_to_user(useraddr, &epause, sizeof(epause)))
  2.3469 -			return -EFAULT;
  2.3470 -		return 0;
  2.3471 -	}
  2.3472 -	case ETHTOOL_SPAUSEPARAM: {
  2.3473 -		struct ethtool_pauseparam epause;
  2.3474 -
  2.3475 -		if (copy_from_user(&epause, useraddr, sizeof(epause)))
  2.3476 -			return -EFAULT;
  2.3477 -
  2.3478 -		tg3_netif_stop(tp);
  2.3479 -		spin_lock_irq(&tp->lock);
  2.3480 -		spin_lock(&tp->tx_lock);
  2.3481 -		if (epause.autoneg)
  2.3482 -			tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  2.3483 -		else
  2.3484 -			tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  2.3485 -		if (epause.rx_pause)
  2.3486 -			tp->tg3_flags |= TG3_FLAG_PAUSE_RX;
  2.3487 -		else
  2.3488 -			tp->tg3_flags &= ~TG3_FLAG_PAUSE_RX;
  2.3489 -		if (epause.tx_pause)
  2.3490 -			tp->tg3_flags |= TG3_FLAG_PAUSE_TX;
  2.3491 -		else
  2.3492 -			tp->tg3_flags &= ~TG3_FLAG_PAUSE_TX;
  2.3493 -		tg3_halt(tp);
  2.3494 -		tg3_init_rings(tp);
  2.3495 -		tg3_init_hw(tp);
  2.3496 -		spin_unlock(&tp->tx_lock);
  2.3497 -		spin_unlock_irq(&tp->lock);
  2.3498 -		tg3_netif_start(tp);
  2.3499 -
  2.3500 -		return 0;
  2.3501 -	}
  2.3502 -	case ETHTOOL_GRXCSUM: {
  2.3503 -		struct ethtool_value edata = { ETHTOOL_GRXCSUM };
  2.3504 -
  2.3505 -		edata.data =
  2.3506 -			(tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  2.3507 -		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.3508 -			return -EFAULT;
  2.3509 -		return 0;
  2.3510 -	}
  2.3511 -	case ETHTOOL_SRXCSUM: {
  2.3512 -		struct ethtool_value edata;
  2.3513 -
  2.3514 -		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.3515 -			return -EFAULT;
  2.3516 -
  2.3517 -		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.3518 -			if (edata.data != 0)
  2.3519 -				return -EINVAL;
  2.3520 -			return 0;
  2.3521 -		}
  2.3522 -
  2.3523 -		spin_lock_irq(&tp->lock);
  2.3524 -		if (edata.data)
  2.3525 -			tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  2.3526 -		else
  2.3527 -			tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  2.3528 -		spin_unlock_irq(&tp->lock);
  2.3529 -
  2.3530 -		return 0;
  2.3531 -	}
  2.3532 -	case ETHTOOL_GTXCSUM: {
  2.3533 -		struct ethtool_value edata = { ETHTOOL_GTXCSUM };
  2.3534 -
  2.3535 -		edata.data =
  2.3536 -			(tp->dev->features & NETIF_F_IP_CSUM) != 0;
  2.3537 -		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.3538 -			return -EFAULT;
  2.3539 -		return 0;
  2.3540 -	}
  2.3541 -	case ETHTOOL_STXCSUM: {
  2.3542 -		struct ethtool_value edata;
  2.3543 -
  2.3544 -		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.3545 -			return -EFAULT;
  2.3546 -
  2.3547 -		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  2.3548 -			if (edata.data != 0)
  2.3549 -				return -EINVAL;
  2.3550 -			return 0;
  2.3551 -		}
  2.3552 -
  2.3553 -		if (edata.data)
  2.3554 -			tp->dev->features |= NETIF_F_IP_CSUM;
  2.3555 -		else
  2.3556 -			tp->dev->features &= ~NETIF_F_IP_CSUM;
  2.3557 -
  2.3558 -		return 0;
  2.3559 -	}
  2.3560 -	case ETHTOOL_GSG: {
  2.3561 -		struct ethtool_value edata = { ETHTOOL_GSG };
  2.3562 -
  2.3563 -		edata.data =
  2.3564 -			(tp->dev->features & NETIF_F_SG) != 0;
  2.3565 -		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.3566 -			return -EFAULT;
  2.3567 -		return 0;
  2.3568 -	}
  2.3569 -	case ETHTOOL_SSG: {
  2.3570 -		struct ethtool_value edata;
  2.3571 -
  2.3572 -		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.3573 -			return -EFAULT;
  2.3574 -
  2.3575 -		if (edata.data)
  2.3576 -			tp->dev->features |= NETIF_F_SG;
  2.3577 -		else
  2.3578 -			tp->dev->features &= ~NETIF_F_SG;
  2.3579 -
  2.3580 -		return 0;
  2.3581 -	}
  2.3582 -	};
  2.3583 -
  2.3584 -	return -EOPNOTSUPP;
  2.3585 +  		return 0;
  2.3586 +  	}
  2.3587 +  
  2.3588 +	if (data)
  2.3589 +		dev->features |= NETIF_F_IP_CSUM;
  2.3590 +	else
  2.3591 +		dev->features &= ~NETIF_F_IP_CSUM;
  2.3592 +
  2.3593 +	return 0;
  2.3594  }
  2.3595 -
  2.3596 +  
  2.3597  static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2.3598  {
  2.3599  	struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
  2.3600 @@ -5568,8 +6221,6 @@ static int tg3_ioctl(struct net_device *
  2.3601  	int err;
  2.3602  
  2.3603  	switch(cmd) {
  2.3604 -	case SIOCETHTOOL:
  2.3605 -		return tg3_ethtool_ioctl(dev, (void *) ifr->ifr_data);
  2.3606  	case SIOCGMIIPHY:
  2.3607  		data->phy_id = PHY_ADDR;
  2.3608  
  2.3609 @@ -5633,11 +6284,44 @@ static void tg3_vlan_rx_kill_vid(struct 
  2.3610  }
  2.3611  #endif
  2.3612  
  2.3613 +#ifdef ETHTOOL
  2.3614 +static struct ethtool_ops tg3_ethtool_ops = {
  2.3615 +	.get_settings		= tg3_get_settings,
  2.3616 +	.set_settings		= tg3_set_settings,
  2.3617 +	.get_drvinfo		= tg3_get_drvinfo,
  2.3618 +	.get_regs_len		= tg3_get_regs_len,
  2.3619 +	.get_regs		= tg3_get_regs,
  2.3620 +	.get_wol		= tg3_get_wol,
  2.3621 +	.set_wol		= tg3_set_wol,
  2.3622 +	.get_msglevel		= tg3_get_msglevel,
  2.3623 +	.set_msglevel		= tg3_set_msglevel,
  2.3624 +	.nway_reset		= tg3_nway_reset,
  2.3625 +	.get_link		= ethtool_op_get_link,
  2.3626 +	.get_ringparam		= tg3_get_ringparam,
  2.3627 +	.set_ringparam		= tg3_set_ringparam,
  2.3628 +	.get_pauseparam		= tg3_get_pauseparam,
  2.3629 +	.set_pauseparam		= tg3_set_pauseparam,
  2.3630 +	.get_rx_csum		= tg3_get_rx_csum,
  2.3631 +	.set_rx_csum		= tg3_set_rx_csum,
  2.3632 +	.get_tx_csum		= ethtool_op_get_tx_csum,
  2.3633 +	.set_tx_csum		= tg3_set_tx_csum,
  2.3634 +	.get_sg			= ethtool_op_get_sg,
  2.3635 +	.set_sg			= ethtool_op_set_sg,
  2.3636 +#if TG3_TSO_SUPPORT != 0
  2.3637 +	.get_tso		= ethtool_op_get_tso,
  2.3638 +	.set_tso		= tg3_set_tso,
  2.3639 +#endif
  2.3640 +};
  2.3641 +#endif
  2.3642 +
  2.3643  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  2.3644  static void __devinit tg3_nvram_init(struct tg3 *tp)
  2.3645  {
  2.3646  	int j;
  2.3647  
  2.3648 +	if (tp->tg3_flags2 & TG3_FLG2_SUN_5704)
  2.3649 +		return;
  2.3650 +
  2.3651  	tw32(GRC_EEPROM_ADDR,
  2.3652  	     (EEPROM_ADDR_FSM_RESET |
  2.3653  	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
  2.3654 @@ -5710,6 +6394,11 @@ static int __devinit tg3_nvram_read(stru
  2.3655  {
  2.3656  	int i, saw_done_clear;
  2.3657  
  2.3658 +	if (tp->tg3_flags2 & TG3_FLG2_SUN_5704) {
  2.3659 +		printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 5704\n");
  2.3660 +		return -EINVAL;
  2.3661 +	}
  2.3662 +
  2.3663  	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  2.3664  		return tg3_nvram_read_using_eeprom(tp, offset, val);
  2.3665  
  2.3666 @@ -5825,6 +6514,7 @@ static int __devinit tg3_phy_probe(struc
  2.3667  		u32 nic_cfg;
  2.3668  
  2.3669  		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  2.3670 +		tp->nic_sram_data_cfg = nic_cfg;
  2.3671  
  2.3672  		eeprom_signature_found = 1;
  2.3673  
  2.3674 @@ -5858,8 +6548,10 @@ static int __devinit tg3_phy_probe(struc
  2.3675  			eeprom_led_mode = led_mode_auto;
  2.3676  			break;
  2.3677  		};
  2.3678 -		if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1 ||
  2.3679 -		     tp->pci_chip_rev_id == CHIPREV_ID_5703_A2) &&
  2.3680 +
  2.3681 +		if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
  2.3682 +		     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  2.3683 +		     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
  2.3684  		    (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
  2.3685  			tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  2.3686  
  2.3687 @@ -5941,9 +6633,7 @@ static int __devinit tg3_phy_probe(struc
  2.3688  	}
  2.3689  
  2.3690  	/* Enable Ethernet@WireSpeed */
  2.3691 -	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
  2.3692 -	tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  2.3693 -	tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
  2.3694 +	tg3_phy_set_wirespeed(tp);
  2.3695  
  2.3696  	if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  2.3697  		err = tg3_init_5401phy_dsp(tp);
  2.3698 @@ -5978,6 +6668,14 @@ static void __devinit tg3_read_partno(st
  2.3699  	unsigned char vpd_data[256];
  2.3700  	int i;
  2.3701  
  2.3702 +	if (tp->tg3_flags2 & TG3_FLG2_SUN_5704) {
  2.3703 +		/* Sun decided not to put the necessary bits in the
  2.3704 +		 * NVRAM of their onboard tg3 parts :(
  2.3705 +		 */
  2.3706 +		strcpy(tp->board_part_number, "Sun 5704");
  2.3707 +		return;
  2.3708 +	}
  2.3709 +
  2.3710  	for (i = 0; i < 256; i += 4) {
  2.3711  		u32 tmp;
  2.3712  
  2.3713 @@ -6034,6 +6732,34 @@ out_not_found:
  2.3714  	strcpy(tp->board_part_number, "none");
  2.3715  }
  2.3716  
  2.3717 +#ifdef CONFIG_SPARC64
  2.3718 +static int __devinit tg3_is_sun_5704(struct tg3 *tp)
  2.3719 +{
  2.3720 +	struct pci_dev *pdev = tp->pdev;
  2.3721 +	struct pcidev_cookie *pcp = pdev->sysdata;
  2.3722 +
  2.3723 +	if (pcp != NULL) {
  2.3724 +		int node = pcp->prom_node;
  2.3725 +		u32 venid, devid;
  2.3726 +		int err;
  2.3727 +
  2.3728 +		err = prom_getproperty(node, "subsystem-vendor-id",
  2.3729 +				       (char *) &venid, sizeof(venid));
  2.3730 +		if (err == 0 || err == -1)
  2.3731 +			return 0;
  2.3732 +		err = prom_getproperty(node, "subsystem-id",
  2.3733 +				       (char *) &devid, sizeof(devid));
  2.3734 +		if (err == 0 || err == -1)
  2.3735 +			return 0;
  2.3736 +
  2.3737 +		if (venid == PCI_VENDOR_ID_SUN &&
  2.3738 +		    devid == PCI_DEVICE_ID_TIGON3_5704)
  2.3739 +			return 1;
  2.3740 +	}
  2.3741 +	return 0;
  2.3742 +}
  2.3743 +#endif
  2.3744 +
  2.3745  static int __devinit tg3_get_invariants(struct tg3 *tp)
  2.3746  {
  2.3747  	u32 misc_ctrl_reg;
  2.3748 @@ -6042,7 +6768,12 @@ static int __devinit tg3_get_invariants(
  2.3749  	u16 pci_cmd;
  2.3750  	int err;
  2.3751  
  2.3752 -	/* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
  2.3753 +#ifdef CONFIG_SPARC64
  2.3754 +	if (tg3_is_sun_5704(tp))
  2.3755 +		tp->tg3_flags2 |= TG3_FLG2_SUN_5704;
  2.3756 +#endif
  2.3757 +
  2.3758 +	/* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
  2.3759  	 * reordering to the mailbox registers done by the host
  2.3760  	 * controller can cause major troubles.  We read back from
  2.3761  	 * every mailbox register write to force the writes to be
  2.3762 @@ -6052,13 +6783,17 @@ static int __devinit tg3_get_invariants(
  2.3763  			    PCI_DEVICE_ID_INTEL_82801AA_8, NULL) ||
  2.3764  	    pci_find_device(PCI_VENDOR_ID_INTEL,
  2.3765  			    PCI_DEVICE_ID_INTEL_82801AB_8, NULL) ||
  2.3766 +	    pci_find_device(PCI_VENDOR_ID_INTEL,
  2.3767 +			    PCI_DEVICE_ID_INTEL_82801BA_11, NULL) ||
  2.3768 +	    pci_find_device(PCI_VENDOR_ID_INTEL,
  2.3769 +			    PCI_DEVICE_ID_INTEL_82801BA_6, NULL) ||
  2.3770  	    pci_find_device(PCI_VENDOR_ID_AMD,
  2.3771  			    PCI_DEVICE_ID_AMD_FE_GATE_700C, NULL))
  2.3772  		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  2.3773  
  2.3774  	/* Force memory write invalidate off.  If we leave it on,
  2.3775  	 * then on 5700_BX chips we have to enable a workaround.
  2.3776 -	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
  2.3777 +	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  2.3778  	 * to match the cacheline size.  The Broadcom driver have this
  2.3779  	 * workaround but turns MWI off all the times so never uses
  2.3780  	 * it.  This seems to suggest that the workaround is insufficient.
  2.3781 @@ -6200,7 +6935,15 @@ static int __devinit tg3_get_invariants(
  2.3782  		tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  2.3783  	}
  2.3784  
  2.3785 +	/* A few boards don't want Ethernet@WireSpeed phy feature */
  2.3786 +	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  2.3787 +	    ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  2.3788 +	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  2.3789 +	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
  2.3790 +		tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  2.3791 +
  2.3792  	/* Only 5701 and later support tagged irq status mode.
  2.3793 +	 * Also, 5788 chips cannot use tagged irq status.
  2.3794  	 *
  2.3795  	 * However, since we are using NAPI avoid tagged irq status
  2.3796  	 * because the interrupt condition is more difficult to
  2.3797 @@ -6257,7 +7000,8 @@ static int __devinit tg3_get_invariants(
  2.3798  	/* Determine if TX descriptors will reside in
  2.3799  	 * main memory or in the chip SRAM.
  2.3800  	 */
  2.3801 -	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  2.3802 +	if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0 ||
  2.3803 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.3804  		tp->tg3_flags |= TG3_FLAG_HOST_TXDS;
  2.3805  
  2.3806  	grc_misc_cfg = tr32(GRC_MISC_CFG);
  2.3807 @@ -6269,8 +7013,18 @@ static int __devinit tg3_get_invariants(
  2.3808  		tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
  2.3809  	}
  2.3810  
  2.3811 -	/* this one is limited to 10/100 only */
  2.3812 -	if (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5702FE)
  2.3813 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  2.3814 +	    (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  2.3815 +	     grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  2.3816 +		tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  2.3817 +
  2.3818 +	/* these are limited to 10/100 only */
  2.3819 +	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  2.3820 +	     (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  2.3821 +	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  2.3822 +	     tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  2.3823 +	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  2.3824 +	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2)))
  2.3825  		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  2.3826  
  2.3827  	err = tg3_phy_probe(tp);
  2.3828 @@ -6350,11 +7104,44 @@ static int __devinit tg3_get_invariants(
  2.3829  	return err;
  2.3830  }
  2.3831  
  2.3832 +#ifdef CONFIG_SPARC64
  2.3833 +static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  2.3834 +{
  2.3835 +	struct net_device *dev = tp->dev;
  2.3836 +	struct pci_dev *pdev = tp->pdev;
  2.3837 +	struct pcidev_cookie *pcp = pdev->sysdata;
  2.3838 +
  2.3839 +	if (pcp != NULL) {
  2.3840 +		int node = pcp->prom_node;
  2.3841 +
  2.3842 +		if (prom_getproplen(node, "local-mac-address") == 6) {
  2.3843 +			prom_getproperty(node, "local-mac-address",
  2.3844 +					 dev->dev_addr, 6);
  2.3845 +			return 0;
  2.3846 +		}
  2.3847 +	}
  2.3848 +	return -ENODEV;
  2.3849 +}
  2.3850 +
  2.3851 +static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  2.3852 +{
  2.3853 +	struct net_device *dev = tp->dev;
  2.3854 +
  2.3855 +	memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  2.3856 +	return 0;
  2.3857 +}
  2.3858 +#endif
  2.3859 +
  2.3860  static int __devinit tg3_get_device_address(struct tg3 *tp)
  2.3861  {
  2.3862  	struct net_device *dev = tp->dev;
  2.3863  	u32 hi, lo, mac_offset;
  2.3864  
  2.3865 +#ifdef CONFIG_SPARC64
  2.3866 +	if (!tg3_get_macaddr_sparc(tp))
  2.3867 +		return 0;
  2.3868 +#endif
  2.3869 +
  2.3870  	if (PCI_FUNC(tp->pdev->devfn) == 0)
  2.3871  		mac_offset = 0x7c;
  2.3872  	else
  2.3873 @@ -6373,7 +7160,8 @@ static int __devinit tg3_get_device_addr
  2.3874  		dev->dev_addr[5] = (lo >>  0) & 0xff;
  2.3875  	}
  2.3876  	/* Next, try NVRAM. */
  2.3877 -	else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  2.3878 +	else if (!(tp->tg3_flags & TG3_FLG2_SUN_5704) &&
  2.3879 +		 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  2.3880  		 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  2.3881  		dev->dev_addr[0] = ((hi >> 16) & 0xff);
  2.3882  		dev->dev_addr[1] = ((hi >> 24) & 0xff);
  2.3883 @@ -6395,9 +7183,13 @@ static int __devinit tg3_get_device_addr
  2.3884  		dev->dev_addr[0] = (hi >> 8) & 0xff;
  2.3885  	}
  2.3886  
  2.3887 -	if (!is_valid_ether_addr(&dev->dev_addr[0]))
  2.3888 +	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  2.3889 +#ifdef CONFIG_SPARC64
  2.3890 +		if (!tg3_get_default_macaddr_sparc(tp))
  2.3891 +			return 0;
  2.3892 +#endif
  2.3893  		return -EINVAL;
  2.3894 -
  2.3895 +	}
  2.3896  	return 0;
  2.3897  }
  2.3898  
  2.3899 @@ -6492,8 +7284,6 @@ static int __devinit tg3_test_dma(struct
  2.3900  		goto out_nofree;
  2.3901  	}
  2.3902  
  2.3903 -	tw32(TG3PCI_CLOCK_CTRL, 0);
  2.3904 -
  2.3905  	if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
  2.3906  		tp->dma_rwctrl =
  2.3907  			(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  2.3908 @@ -6501,7 +7291,9 @@ static int __devinit tg3_test_dma(struct
  2.3909  			(0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  2.3910  			(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
  2.3911  			(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
  2.3912 -		/* XXX 5705 note: set MIN_DMA to zero here */
  2.3913 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  2.3914 +			tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA
  2.3915 +					    << DMA_RWCTRL_MIN_DMA_SHIFT);
  2.3916  	} else {
  2.3917  		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.3918  			tp->dma_rwctrl =
  2.3919 @@ -6602,13 +7394,20 @@ static int __devinit tg3_test_dma(struct
  2.3920  		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  2.3921  	}
  2.3922  
  2.3923 +	tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  2.3924 +
  2.3925  	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  2.3926  
  2.3927 +#if 0
  2.3928 +	/* Unneeded, already done by tg3_get_invariants.  */
  2.3929 +	tg3_switch_clocks(tp);
  2.3930 +#endif
  2.3931 +
  2.3932 +	ret = 0;
  2.3933  	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  2.3934  	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  2.3935 -		return 0;
  2.3936 -
  2.3937 -	ret = 0;
  2.3938 +		goto out;
  2.3939 +
  2.3940  	while (1) {
  2.3941  		u32 *p, i;
  2.3942  
  2.3943 @@ -6708,12 +7507,35 @@ static char * __devinit tg3_phy_string(s
  2.3944  	case PHY_ID_BCM5701:	return "5701";
  2.3945  	case PHY_ID_BCM5703:	return "5703";
  2.3946  	case PHY_ID_BCM5704:	return "5704";
  2.3947 +	case PHY_ID_BCM5705:	return "5705";
  2.3948  	case PHY_ID_BCM8002:	return "8002";
  2.3949  	case PHY_ID_SERDES:	return "serdes";
  2.3950  	default:		return "unknown";
  2.3951  	};
  2.3952  }
  2.3953  
  2.3954 +static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
  2.3955 +{
  2.3956 +	struct pci_dev *peer = NULL;
  2.3957 +	unsigned int func;
  2.3958 +
  2.3959 +	for (func = 0; func < 7; func++) {
  2.3960 +		unsigned int devfn = tp->pdev->devfn;
  2.3961 +
  2.3962 +		devfn &= ~7;
  2.3963 +		devfn |= func;
  2.3964 +
  2.3965 +		if (devfn == tp->pdev->devfn)
  2.3966 +			continue;
  2.3967 +		peer = pci_find_slot(tp->pdev->bus->number, devfn);
  2.3968 +		if (peer)
  2.3969 +			break;
  2.3970 +	}
  2.3971 +	if (!peer || peer == tp->pdev)
  2.3972 +		BUG();
  2.3973 +	return peer;
  2.3974 +}
  2.3975 +
  2.3976  static int __devinit tg3_init_one(struct pci_dev *pdev,
  2.3977  				  const struct pci_device_id *ent)
  2.3978  {
  2.3979 @@ -6758,10 +7580,10 @@ static int __devinit tg3_init_one(struct
  2.3980  	}
  2.3981  
  2.3982  	/* Configure DMA attributes. */
  2.3983 -	if (!pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff)) {
  2.3984 +	if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
  2.3985  		pci_using_dac = 1;
  2.3986  	} else {
  2.3987 -		err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
  2.3988 +		err = pci_set_dma_mask(pdev, 0xffffffffULL);
  2.3989  		if (err) {
  2.3990  			printk(KERN_ERR PFX "No usable DMA configuration, "
  2.3991  			       "aborting.\n");
  2.3992 @@ -6789,9 +7611,6 @@ static int __devinit tg3_init_one(struct
  2.3993  	dev->vlan_rx_register = tg3_vlan_rx_register;
  2.3994  	dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
  2.3995  #endif
  2.3996 -#if TG3_DO_TSO != 0
  2.3997 -	dev->features |= NETIF_F_TSO;
  2.3998 -#endif
  2.3999  
  2.4000  	tp = dev->priv;
  2.4001  	tp->pdev = pdev;
  2.4002 @@ -6830,7 +7649,7 @@ static int __devinit tg3_init_one(struct
  2.4003  	spin_lock_init(&tp->lock);
  2.4004  	spin_lock_init(&tp->tx_lock);
  2.4005  	spin_lock_init(&tp->indirect_lock);
  2.4006 -	PREPARE_TQUEUE(&tp->reset_task, tg3_reset_task, tp);
  2.4007 +	INIT_TQUEUE(&tp->reset_task, tg3_reset_task, tp);
  2.4008  
  2.4009  	tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
  2.4010  	if (tp->regs == 0UL) {
  2.4011 @@ -6857,6 +7676,11 @@ static int __devinit tg3_init_one(struct
  2.4012  	dev->tx_timeout = tg3_tx_timeout;
  2.4013  #ifdef NAPI
  2.4014  	dev->poll = tg3_poll;
  2.4015 +#endif
  2.4016 +#ifdef ETHTOOL
  2.4017 +	dev->ethtool_ops = &tg3_ethtool_ops;
  2.4018 +#endif
  2.4019 +#ifdef NAPI
  2.4020  	dev->weight = 64;
  2.4021  #endif
  2.4022  	dev->watchdog_timeo = TG3_TX_TIMEOUT;
  2.4023 @@ -6870,6 +7694,44 @@ static int __devinit tg3_init_one(struct
  2.4024  		goto err_out_iounmap;
  2.4025  	}
  2.4026  
  2.4027 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2.4028 +		tp->bufmgr_config.mbuf_read_dma_low_water =
  2.4029 +			DEFAULT_MB_RDMA_LOW_WATER_5705;
  2.4030 +		tp->bufmgr_config.mbuf_mac_rx_low_water =
  2.4031 +			DEFAULT_MB_MACRX_LOW_WATER_5705;
  2.4032 +		tp->bufmgr_config.mbuf_high_water =
  2.4033 +			DEFAULT_MB_HIGH_WATER_5705;
  2.4034 +	}
  2.4035 +
  2.4036 +#if TG3_TSO_SUPPORT != 0
  2.4037 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2.4038 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  2.4039 +	    tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  2.4040 +	    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  2.4041 +	    (tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  2.4042 +		tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  2.4043 +	} else {
  2.4044 +		tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  2.4045 +	}
  2.4046 +
  2.4047 +	/* TSO is off by default, user can enable using ethtool.  */
  2.4048 +#if 0
  2.4049 +	if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
  2.4050 +		dev->features |= NETIF_F_TSO;
  2.4051 +#endif
  2.4052 +
  2.4053 +#endif
  2.4054 +
  2.4055 +	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  2.4056 +	    !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  2.4057 +	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  2.4058 +		tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  2.4059 +		tp->rx_pending = 63;
  2.4060 +	}
  2.4061 +
  2.4062 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  2.4063 +		tp->pdev_peer = tg3_find_5704_peer(tp);
  2.4064 +
  2.4065  	err = tg3_get_device_address(tp);
  2.4066  	if (err) {
  2.4067  		printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  2.4068 @@ -6892,6 +7754,9 @@ static int __devinit tg3_init_one(struct
  2.4069  	} else
  2.4070  		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  2.4071  
  2.4072 +	if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  2.4073 +		dev->features &= ~NETIF_F_HIGHDMA;
  2.4074 +
  2.4075  	err = register_netdev(dev);
  2.4076  	if (err) {
  2.4077  		printk(KERN_ERR PFX "Cannot register net device, "
  2.4078 @@ -6965,6 +7830,8 @@ static int tg3_suspend(struct pci_dev *p
  2.4079  
  2.4080  	tg3_netif_stop(tp);
  2.4081  
  2.4082 +	del_timer_sync(&tp->timer);
  2.4083 +
  2.4084  	spin_lock_irq(&tp->lock);
  2.4085  	spin_lock(&tp->tx_lock);
  2.4086  	tg3_disable_ints(tp);
  2.4087 @@ -6984,9 +7851,11 @@ static int tg3_suspend(struct pci_dev *p
  2.4088  		spin_lock_irq(&tp->lock);
  2.4089  		spin_lock(&tp->tx_lock);
  2.4090  
  2.4091 -		tg3_init_rings(tp);
  2.4092  		tg3_init_hw(tp);
  2.4093  
  2.4094 +		tp->timer.expires = jiffies + tp->timer_offset;
  2.4095 +		add_timer(&tp->timer);
  2.4096 +
  2.4097  		spin_unlock(&tp->tx_lock);
  2.4098  		spin_unlock_irq(&tp->lock);
  2.4099  
  2.4100 @@ -7015,8 +7884,11 @@ static int tg3_resume(struct pci_dev *pd
  2.4101  	spin_lock_irq(&tp->lock);
  2.4102  	spin_lock(&tp->tx_lock);
  2.4103  
  2.4104 -	tg3_init_rings(tp);
  2.4105  	tg3_init_hw(tp);
  2.4106 +
  2.4107 +	tp->timer.expires = jiffies + tp->timer_offset;
  2.4108 +	add_timer(&tp->timer);
  2.4109 +
  2.4110  	tg3_enable_ints(tp);
  2.4111  
  2.4112  	spin_unlock(&tp->tx_lock);

     3.1 --- a/xen/drivers/net/tg3.h	Wed Dec 24 16:46:32 2003 +0000
     3.2 +++ b/xen/drivers/net/tg3.h	Wed Dec 31 17:44:09 2003 +0000
     3.3 @@ -21,10 +21,10 @@
     3.4  #define TG3_BDINFO_NIC_ADDR		0xcUL /* 32-bit */
     3.5  #define TG3_BDINFO_SIZE			0x10UL
     3.6  
     3.7 -/* XXX Xen: No copy break. */
     3.8 -#define RX_COPY_THRESHOLD  		0 /*256*/
     3.9 +#define RX_COPY_THRESHOLD  		0  /* No CopyBreak for Xen */
    3.10  
    3.11  #define RX_STD_MAX_SIZE			1536
    3.12 +#define RX_STD_MAX_SIZE_5705		512
    3.13  #define RX_JUMBO_MAX_SIZE		0xdeadbeef /* XXX */
    3.14  
    3.15  /* First 256 bytes are a mirror of PCI config space. */
    3.16 @@ -60,7 +60,7 @@
    3.17  #define  PCIX_CAPS_SPLIT_SHIFT		 20
    3.18  #define  PCIX_CAPS_BURST_MASK		 0x000c0000
    3.19  #define  PCIX_CAPS_BURST_SHIFT		 18
    3.20 -#define  PCIX_CAPS_MAX_BURST_5704	 2
    3.21 +#define  PCIX_CAPS_MAX_BURST_CPIOB	 2
    3.22  #define TG3PCI_PM_CAP_PTR		0x00000041
    3.23  #define TG3PCI_X_COMMAND		0x00000042
    3.24  #define TG3PCI_X_STATUS			0x00000044
    3.25 @@ -116,11 +116,14 @@
    3.26  #define  CHIPREV_ID_5704_A0		 0x2000
    3.27  #define  CHIPREV_ID_5704_A1		 0x2001
    3.28  #define  CHIPREV_ID_5704_A2		 0x2002
    3.29 +#define  CHIPREV_ID_5705_A0		 0x3000
    3.30 +#define  CHIPREV_ID_5705_A1		 0x3001
    3.31  #define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
    3.32  #define   ASIC_REV_5700			 0x07
    3.33  #define   ASIC_REV_5701			 0x00
    3.34  #define   ASIC_REV_5703			 0x01
    3.35  #define   ASIC_REV_5704			 0x02
    3.36 +#define   ASIC_REV_5705			 0x03
    3.37  #define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
    3.38  #define   CHIPREV_5700_AX		 0x70
    3.39  #define   CHIPREV_5700_BX		 0x71
    3.40 @@ -181,6 +184,9 @@
    3.41  #define  CLOCK_CTRL_ALTCLK		 0x00001000
    3.42  #define  CLOCK_CTRL_PWRDOWN_PLL133	 0x00008000
    3.43  #define  CLOCK_CTRL_44MHZ_CORE		 0x00040000
    3.44 +#define  CLOCK_CTRL_625_CORE		 0x00100000
    3.45 +#define  CLOCK_CTRL_FORCE_CLKRUN	 0x00200000
    3.46 +#define  CLOCK_CTRL_CLKRUN_OENABLE	 0x00400000
    3.47  #define  CLOCK_CTRL_DELAY_PCI_GRANT	 0x80000000
    3.48  #define TG3PCI_REG_BASE_ADDR		0x00000078
    3.49  #define TG3PCI_MEM_WIN_BASE_ADDR	0x0000007c
    3.50 @@ -458,17 +464,89 @@
    3.51  #define MAC_RCV_RULE_CFG		0x00000500
    3.52  #define  RCV_RULE_CFG_DEFAULT_CLASS	0x00000008
    3.53  #define MAC_LOW_WMARK_MAX_RX_FRAME	0x00000504
    3.54 -/* 0x504 --> 0x590 unused */
    3.55 +/* 0x508 --> 0x520 unused */
    3.56 +#define MAC_HASHREGU_0			0x00000520
    3.57 +#define MAC_HASHREGU_1			0x00000524
    3.58 +#define MAC_HASHREGU_2			0x00000528
    3.59 +#define MAC_HASHREGU_3			0x0000052c
    3.60 +#define MAC_EXTADDR_0_HIGH		0x00000530
    3.61 +#define MAC_EXTADDR_0_LOW		0x00000534
    3.62 +#define MAC_EXTADDR_1_HIGH		0x00000538
    3.63 +#define MAC_EXTADDR_1_LOW		0x0000053c
    3.64 +#define MAC_EXTADDR_2_HIGH		0x00000540
    3.65 +#define MAC_EXTADDR_2_LOW		0x00000544
    3.66 +#define MAC_EXTADDR_3_HIGH		0x00000548
    3.67 +#define MAC_EXTADDR_3_LOW		0x0000054c
    3.68 +#define MAC_EXTADDR_4_HIGH		0x00000550
    3.69 +#define MAC_EXTADDR_4_LOW		0x00000554
    3.70 +#define MAC_EXTADDR_5_HIGH		0x00000558
    3.71 +#define MAC_EXTADDR_5_LOW		0x0000055c
    3.72 +#define MAC_EXTADDR_6_HIGH		0x00000560
    3.73 +#define MAC_EXTADDR_6_LOW		0x00000564
    3.74 +#define MAC_EXTADDR_7_HIGH		0x00000568
    3.75 +#define MAC_EXTADDR_7_LOW		0x0000056c
    3.76 +#define MAC_EXTADDR_8_HIGH		0x00000570
    3.77 +#define MAC_EXTADDR_8_LOW		0x00000574
    3.78 +#define MAC_EXTADDR_9_HIGH		0x00000578
    3.79 +#define MAC_EXTADDR_9_LOW		0x0000057c
    3.80 +#define MAC_EXTADDR_10_HIGH		0x00000580
    3.81 +#define MAC_EXTADDR_10_LOW		0x00000584
    3.82 +#define MAC_EXTADDR_11_HIGH		0x00000588
    3.83 +#define MAC_EXTADDR_11_LOW		0x0000058c
    3.84  #define MAC_SERDES_CFG			0x00000590
    3.85  #define MAC_SERDES_STAT			0x00000594
    3.86  /* 0x598 --> 0x600 unused */
    3.87  #define MAC_TX_MAC_STATE_BASE		0x00000600 /* 16 bytes */
    3.88  #define MAC_RX_MAC_STATE_BASE		0x00000610 /* 20 bytes */
    3.89  /* 0x624 --> 0x800 unused */
    3.90 -#define MAC_RX_STATS_BASE		0x00000800 /* 26 32-bit words */
    3.91 -/* 0x868 --> 0x880 unused */
    3.92 -#define MAC_TX_STATS_BASE		0x00000880 /* 28 32-bit words */
    3.93 -/* 0x8f0 --> 0xc00 unused */
    3.94 +#define MAC_TX_STATS_OCTETS		0x00000800
    3.95 +#define MAC_TX_STATS_RESV1		0x00000804
    3.96 +#define MAC_TX_STATS_COLLISIONS		0x00000808
    3.97 +#define MAC_TX_STATS_XON_SENT		0x0000080c
    3.98 +#define MAC_TX_STATS_XOFF_SENT		0x00000810
    3.99 +#define MAC_TX_STATS_RESV2		0x00000814
   3.100 +#define MAC_TX_STATS_MAC_ERRORS		0x00000818
   3.101 +#define MAC_TX_STATS_SINGLE_COLLISIONS	0x0000081c
   3.102 +#define MAC_TX_STATS_MULT_COLLISIONS	0x00000820
   3.103 +#define MAC_TX_STATS_DEFERRED		0x00000824
   3.104 +#define MAC_TX_STATS_RESV3		0x00000828
   3.105 +#define MAC_TX_STATS_EXCESSIVE_COL	0x0000082c
   3.106 +#define MAC_TX_STATS_LATE_COL		0x00000830
   3.107 +#define MAC_TX_STATS_RESV4_1		0x00000834
   3.108 +#define MAC_TX_STATS_RESV4_2		0x00000838
   3.109 +#define MAC_TX_STATS_RESV4_3		0x0000083c
   3.110 +#define MAC_TX_STATS_RESV4_4		0x00000840
   3.111 +#define MAC_TX_STATS_RESV4_5		0x00000844
   3.112 +#define MAC_TX_STATS_RESV4_6		0x00000848
   3.113 +#define MAC_TX_STATS_RESV4_7		0x0000084c
   3.114 +#define MAC_TX_STATS_RESV4_8		0x00000850
   3.115 +#define MAC_TX_STATS_RESV4_9		0x00000854
   3.116 +#define MAC_TX_STATS_RESV4_10		0x00000858
   3.117 +#define MAC_TX_STATS_RESV4_11		0x0000085c
   3.118 +#define MAC_TX_STATS_RESV4_12		0x00000860
   3.119 +#define MAC_TX_STATS_RESV4_13		0x00000864
   3.120 +#define MAC_TX_STATS_RESV4_14		0x00000868
   3.121 +#define MAC_TX_STATS_UCAST		0x0000086c
   3.122 +#define MAC_TX_STATS_MCAST		0x00000870
   3.123 +#define MAC_TX_STATS_BCAST		0x00000874
   3.124 +#define MAC_TX_STATS_RESV5_1		0x00000878
   3.125 +#define MAC_TX_STATS_RESV5_2		0x0000087c
   3.126 +#define MAC_RX_STATS_OCTETS		0x00000880
   3.127 +#define MAC_RX_STATS_RESV1		0x00000884
   3.128 +#define MAC_RX_STATS_FRAGMENTS		0x00000888
   3.129 +#define MAC_RX_STATS_UCAST		0x0000088c
   3.130 +#define MAC_RX_STATS_MCAST		0x00000890
   3.131 +#define MAC_RX_STATS_BCAST		0x00000894
   3.132 +#define MAC_RX_STATS_FCS_ERRORS		0x00000898
   3.133 +#define MAC_RX_STATS_ALIGN_ERRORS	0x0000089c
   3.134 +#define MAC_RX_STATS_XON_PAUSE_RECVD	0x000008a0
   3.135 +#define MAC_RX_STATS_XOFF_PAUSE_RECVD	0x000008a4
   3.136 +#define MAC_RX_STATS_MAC_CTRL_RECVD	0x000008a8
   3.137 +#define MAC_RX_STATS_XOFF_ENTERED	0x000008ac
   3.138 +#define MAC_RX_STATS_FRAME_TOO_LONG	0x000008b0
   3.139 +#define MAC_RX_STATS_JABBERS		0x000008b4
   3.140 +#define MAC_RX_STATS_UNDERSIZE		0x000008b8
   3.141 +/* 0x8bc --> 0xc00 unused */
   3.142  
   3.143  /* Send data initiator control registers */
   3.144  #define SNDDATAI_MODE			0x00000c00
   3.145 @@ -600,6 +678,7 @@
   3.146  #define  RCVLPC_STATSCTRL_ENABLE	 0x00000001
   3.147  #define  RCVLPC_STATSCTRL_FASTUPD	 0x00000002
   3.148  #define RCVLPC_STATS_ENABLE		0x00002018
   3.149 +#define  RCVLPC_STATSENAB_LNGBRST_RFIX	 0x00400000
   3.150  #define RCVLPC_STATS_INCMASK		0x0000201c
   3.151  /* 0x2020 --> 0x2100 unused */
   3.152  #define RCVLPC_SELLST_BASE		0x00002100 /* 16 16-byte entries */
   3.153 @@ -813,13 +892,16 @@
   3.154  #define BUFMGR_MB_POOL_ADDR		0x00004408
   3.155  #define BUFMGR_MB_POOL_SIZE		0x0000440c
   3.156  #define BUFMGR_MB_RDMA_LOW_WATER	0x00004410
   3.157 -#define  DEFAULT_MB_RDMA_LOW_WATER	 0x00000040
   3.158 +#define  DEFAULT_MB_RDMA_LOW_WATER	 0x00000050
   3.159 +#define  DEFAULT_MB_RDMA_LOW_WATER_5705	 0x00000000
   3.160  #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
   3.161  #define BUFMGR_MB_MACRX_LOW_WATER	0x00004414
   3.162  #define  DEFAULT_MB_MACRX_LOW_WATER	  0x00000020
   3.163 +#define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
   3.164  #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
   3.165  #define BUFMGR_MB_HIGH_WATER		0x00004418
   3.166  #define  DEFAULT_MB_HIGH_WATER		 0x00000060
   3.167 +#define  DEFAULT_MB_HIGH_WATER_5705	 0x00000060
   3.168  #define  DEFAULT_MB_HIGH_WATER_JUMBO	 0x0000017c
   3.169  #define BUFMGR_RX_MB_ALLOC_REQ		0x0000441c
   3.170  #define  BUFMGR_MB_ALLOC_BIT		 0x10000000
   3.171 @@ -855,6 +937,8 @@
   3.172  #define  RDMAC_MODE_LNGREAD_ENAB	 0x00000200
   3.173  #define  RDMAC_MODE_SPLIT_ENABLE	 0x00000800
   3.174  #define  RDMAC_MODE_SPLIT_RESET		 0x00001000
   3.175 +#define  RDMAC_MODE_FIFO_SIZE_128	 0x00020000
   3.176 +#define  RDMAC_MODE_FIFO_LONG_BURST	 0x00030000
   3.177  #define RDMAC_STATUS			0x00004804
   3.178  #define  RDMAC_STATUS_TGTABORT		 0x00000004
   3.179  #define  RDMAC_STATUS_MSTABORT		 0x00000008
   3.180 @@ -878,6 +962,7 @@
   3.181  #define  WDMAC_MODE_FIFOURUN_ENAB	 0x00000080
   3.182  #define  WDMAC_MODE_FIFOOREAD_ENAB	 0x00000100
   3.183  #define  WDMAC_MODE_LNGREAD_ENAB	 0x00000200
   3.184 +#define  WDMAC_MODE_RX_ACCEL	 	 0x00000400
   3.185  #define WDMAC_STATUS			0x00004c04
   3.186  #define  WDMAC_STATUS_TGTABORT		 0x00000004
   3.187  #define  WDMAC_STATUS_MSTABORT		 0x00000008
   3.188 @@ -1141,7 +1226,10 @@
   3.189  #define  GRC_MISC_CFG_BOARD_ID_5704	0x00000000
   3.190  #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
   3.191  #define  GRC_MISC_CFG_BOARD_ID_5704_A2	0x00008000
   3.192 +#define  GRC_MISC_CFG_BOARD_ID_5788	0x00010000
   3.193 +#define  GRC_MISC_CFG_BOARD_ID_5788M	0x00018000
   3.194  #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
   3.195 +#define  GRC_MISC_CFG_KEEP_GPHY_POWER	0x04000000
   3.196  #define GRC_LOCAL_CTRL			0x00006808
   3.197  #define  GRC_LCLCTRL_INT_ACTIVE		0x00000001
   3.198  #define  GRC_LCLCTRL_CLEARINT		0x00000002
   3.199 @@ -1276,6 +1364,7 @@
   3.200  #define  NIC_SRAM_DATA_CFG_WOL_ENABLE		 0x00000040
   3.201  #define  NIC_SRAM_DATA_CFG_ASF_ENABLE		 0x00000080
   3.202  #define  NIC_SRAM_DATA_CFG_EEPROM_WP		 0x00000100
   3.203 +#define  NIC_SRAM_DATA_CFG_MINI_PCI		 0x00001000
   3.204  #define  NIC_SRAM_DATA_CFG_FIBER_WOL		 0x00004000
   3.205  
   3.206  #define NIC_SRAM_DATA_PHY_ID		0x00000b74
   3.207 @@ -1313,6 +1402,8 @@
   3.208  #define NIC_SRAM_MBUF_POOL_BASE		0x00008000
   3.209  #define  NIC_SRAM_MBUF_POOL_SIZE96	 0x00018000
   3.210  #define  NIC_SRAM_MBUF_POOL_SIZE64	 0x00010000
   3.211 +#define  NIC_SRAM_MBUF_POOL_BASE5705	0x00010000
   3.212 +#define  NIC_SRAM_MBUF_POOL_SIZE5705	0x0000e000
   3.213  
   3.214  /* Currently this is fixed. */
   3.215  #define PHY_ADDR		0x01
   3.216 @@ -1824,6 +1915,11 @@ struct tg3 {
   3.217  #define TG3_FLAG_INIT_COMPLETE		0x80000000
   3.218  	u32				tg3_flags2;
   3.219  #define TG3_FLG2_RESTART_TIMER		0x00000001
   3.220 +#define TG3_FLG2_SUN_5704		0x00000002
   3.221 +#define TG3_FLG2_NO_ETH_WIRE_SPEED	0x00000004
   3.222 +#define TG3_FLG2_IS_5788		0x00000008
   3.223 +#define TG3_FLG2_MAX_RXPEND_64		0x00000010
   3.224 +#define TG3_FLG2_TSO_CAPABLE		0x00000020
   3.225  
   3.226  	u32				split_mode_max_reqs;
   3.227  #define SPLIT_MODE_5704_MAX_REQ		3
   3.228 @@ -1868,6 +1964,7 @@ struct tg3 {
   3.229  #define PHY_ID_BCM5701			0x60008110
   3.230  #define PHY_ID_BCM5703			0x60008160
   3.231  #define PHY_ID_BCM5704			0x60008190
   3.232 +#define PHY_ID_BCM5705			0x600081a0
   3.233  #define PHY_ID_BCM8002			0x60010140
   3.234  #define PHY_ID_SERDES			0xfeedbee0
   3.235  #define PHY_ID_INVALID			0xffffffff
   3.236 @@ -1880,6 +1977,9 @@ struct tg3 {
   3.237  	enum phy_led_mode		led_mode;
   3.238  
   3.239  	char				board_part_number[24];
   3.240 +	u32				nic_sram_data_cfg;
   3.241 +	u32				pci_clock_ctrl;
   3.242 +	struct pci_dev			*pdev_peer;
   3.243  
   3.244  	/* This macro assumes the passed PHY ID is already masked
   3.245  	 * with PHY_ID_MASK.
   3.246 @@ -1888,6 +1988,7 @@ struct tg3 {
   3.247  	((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
   3.248  	 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
   3.249  	 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
   3.250 +	 (X) == PHY_ID_BCM5705 || \
   3.251  	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
   3.252  
   3.253  	struct tg3_hw_stats		*hw_stats;

     4.1 --- a/xen/include/xeno/interrupt.h	Wed Dec 24 16:46:32 2003 +0000
     4.2 +++ b/xen/include/xeno/interrupt.h	Wed Dec 31 17:44:09 2003 +0000
     4.3 @@ -11,6 +11,12 @@
     4.4  #include <asm/atomic.h>
     4.5  #include <asm/ptrace.h>
     4.6  
     4.7 +/* For 2.6.x compatibility */
     4.8 +typedef void irqreturn_t;
     4.9 +#define IRQ_NONE
    4.10 +#define IRQ_HANDLED
    4.11 +#define IRQ_RETVAL(x)
    4.12 +                                                                                
    4.13  struct irqaction {
    4.14  	void (*handler)(int, void *, struct pt_regs *);
    4.15  	unsigned long flags;

     5.1 --- a/xen/include/xeno/pci_ids.h	Wed Dec 24 16:46:32 2003 +0000
     5.2 +++ b/xen/include/xeno/pci_ids.h	Wed Dec 31 17:44:09 2003 +0000
     5.3 @@ -258,17 +258,61 @@
     5.4  #define PCI_DEVICE_ID_ATI_RAGE128_U1	0x5446
     5.5  #define PCI_DEVICE_ID_ATI_RAGE128_U2	0x544C
     5.6  #define PCI_DEVICE_ID_ATI_RAGE128_U3	0x5452
     5.7 -/* Radeon M4 */
     5.8 +/* Rage M4 */
     5.9  #define PCI_DEVICE_ID_ATI_RADEON_LE	0x4d45
    5.10  #define PCI_DEVICE_ID_ATI_RADEON_LF	0x4d46
    5.11 -/* Radeon NV-100 */
    5.12 -#define PCI_DEVICE_ID_ATI_RADEON_N1	0x5159
    5.13 -#define PCI_DEVICE_ID_ATI_RADEON_N2	0x515a
    5.14 -/* Radeon */
    5.15 -#define PCI_DEVICE_ID_ATI_RADEON_RA	0x5144
    5.16 -#define PCI_DEVICE_ID_ATI_RADEON_RB	0x5145
    5.17 -#define PCI_DEVICE_ID_ATI_RADEON_RC	0x5146
    5.18 -#define PCI_DEVICE_ID_ATI_RADEON_RD	0x5147
    5.19 +/* Radeon R100 */
    5.20 +#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
    5.21 +#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
    5.22 +#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
    5.23 +#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
    5.24 +/* Radeon RV100 (VE) */
    5.25 +#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
    5.26 +#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
    5.27 +/* Radeon R200 (8500) */
    5.28 +#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
    5.29 +#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
    5.30 +#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
    5.31 +#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
    5.32 +#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
    5.33 +/* Radeon R200 (9100) */
    5.34 +#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
    5.35 +/* Radeon RV200 (7500) */
    5.36 +#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
    5.37 +#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
    5.38 +/* Radeon RV250 (9000) */
    5.39 +#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
    5.40 +#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
    5.41 +#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
    5.42 +#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
    5.43 +/* Radeon RV280 (9200) */
    5.44 +#define PCI_DEVICE_ID_ATI_RADEON_Y_	0x5960
    5.45 +/* Radeon R300 (9700) */
    5.46 +#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
    5.47 +#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
    5.48 +#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
    5.49 +#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
    5.50 +#define PCI_DEVICE_ID_ATI_RADEON_AE	0x4145
    5.51 +#define PCI_DEVICE_ID_ATI_RADEON_AF	0x4146
    5.52 +/* Radeon R300 (9500) */
    5.53 +#define PCI_DEVICE_ID_ATI_RADEON_AD	0x4144
    5.54 +/* Radeon R350 (9800) */
    5.55 +#define PCI_DEVICE_ID_ATI_RADEON_NH	0x4e48
    5.56 +#define PCI_DEVICE_ID_ATI_RADEON_NI	0x4e49
    5.57 +/* Radeon RV350 (9600) */
    5.58 +#define PCI_DEVICE_ID_ATI_RADEON_AP	0x4150
    5.59 +#define PCI_DEVICE_ID_ATI_RADEON_AR	0x4152
    5.60 +/* Radeon M6 */
    5.61 +#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
    5.62 +#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
    5.63 +/* Radeon M7 */
    5.64 +#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
    5.65 +#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
    5.66 +/* Radeon M9 */
    5.67 +#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
    5.68 +#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
    5.69 +#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
    5.70 +#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
    5.71  /* RadeonIGP */
    5.72  #define PCI_DEVICE_ID_ATI_RADEON_IGP	0xCAB0
    5.73  
    5.74 @@ -493,6 +537,7 @@
    5.75  #define PCI_DEVICE_ID_SI_601		0x0601
    5.76  #define PCI_DEVICE_ID_SI_620		0x0620
    5.77  #define PCI_DEVICE_ID_SI_630		0x0630
    5.78 +#define PCI_DEVICE_ID_SI_633		0x0633
    5.79  #define PCI_DEVICE_ID_SI_635		0x0635
    5.80  #define PCI_DEVICE_ID_SI_640		0x0640
    5.81  #define PCI_DEVICE_ID_SI_645		0x0645
    5.82 @@ -501,7 +546,9 @@
    5.83  #define PCI_DEVICE_ID_SI_650		0x0650
    5.84  #define PCI_DEVICE_ID_SI_651		0x0651
    5.85  #define PCI_DEVICE_ID_SI_652		0x0652
    5.86 +#define PCI_DEVICE_ID_SI_655		0x0655
    5.87  #define PCI_DEVICE_ID_SI_730		0x0730
    5.88 +#define PCI_DEVICE_ID_SI_733		0x0733
    5.89  #define PCI_DEVICE_ID_SI_630_VGA	0x6300
    5.90  #define PCI_DEVICE_ID_SI_730_VGA	0x7300
    5.91  #define PCI_DEVICE_ID_SI_735		0x0735
    5.92 @@ -512,6 +559,7 @@
    5.93  #define PCI_DEVICE_ID_SI_750		0x0750
    5.94  #define PCI_DEVICE_ID_SI_751		0x0751
    5.95  #define PCI_DEVICE_ID_SI_752		0x0752
    5.96 +#define PCI_DEVICE_ID_SI_755            0x0755
    5.97  #define PCI_DEVICE_ID_SI_900		0x0900
    5.98  #define PCI_DEVICE_ID_SI_5107		0x5107
    5.99  #define PCI_DEVICE_ID_SI_5300		0x5300
   5.100 @@ -519,7 +567,10 @@
   5.101  #define PCI_DEVICE_ID_SI_5513		0x5513
   5.102  #define PCI_DEVICE_ID_SI_5518		0x5518
   5.103  #define PCI_DEVICE_ID_SI_5571		0x5571
   5.104 +#define PCI_DEVICE_ID_SI_5581		0x5581
   5.105 +#define PCI_DEVICE_ID_SI_5582		0x5582
   5.106  #define PCI_DEVICE_ID_SI_5591		0x5591
   5.107 +#define PCI_DEVICE_ID_SI_5596		0x5596
   5.108  #define PCI_DEVICE_ID_SI_5597		0x5597
   5.109  #define PCI_DEVICE_ID_SI_5598		0x5598
   5.110  #define PCI_DEVICE_ID_SI_5600		0x5600
   5.111 @@ -539,11 +590,13 @@
   5.112  #define PCI_DEVICE_ID_HP_DIVA1		0x1049
   5.113  #define PCI_DEVICE_ID_HP_DIVA2		0x104A
   5.114  #define PCI_DEVICE_ID_HP_SP2_0		0x104B
   5.115 +#define PCI_DEVICE_ID_HP_PCI_LBA	0x1054
   5.116  #define PCI_DEVICE_ID_HP_REO_SBA	0x10f0
   5.117  #define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
   5.118  #define PCI_DEVICE_ID_HP_ZX1_SBA	0x1229
   5.119  #define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
   5.120 -#define PCI_DEVICE_ID_HP_ZX1_LBA	0x122e
   5.121 +#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
   5.122 +#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
   5.123  
   5.124  #define PCI_VENDOR_ID_PCTECH		0x1042
   5.125  #define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
   5.126 @@ -758,8 +811,11 @@
   5.127  #define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
   5.128  #define PCI_DEVICE_ID_SUN_SABRE		0xa000
   5.129  #define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
   5.130 +#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
   5.131  
   5.132  #define PCI_VENDOR_ID_CMD		0x1095
   5.133 +#define PCI_DEVICE_ID_SII_1210SA	0x0240
   5.134 +
   5.135  #define PCI_DEVICE_ID_CMD_640		0x0640
   5.136  #define PCI_DEVICE_ID_CMD_643		0x0643
   5.137  #define PCI_DEVICE_ID_CMD_646		0x0646
   5.138 @@ -767,7 +823,6 @@
   5.139  #define PCI_DEVICE_ID_CMD_648		0x0648
   5.140  #define PCI_DEVICE_ID_CMD_649		0x0649
   5.141  #define PCI_DEVICE_ID_CMD_670		0x0670
   5.142 -#define PCI_DEVICE_ID_CMD_680		0x0680
   5.143  
   5.144  #define PCI_DEVICE_ID_SII_680		0x0680
   5.145  #define PCI_DEVICE_ID_SII_3112		0x3112
   5.146 @@ -788,6 +843,7 @@
   5.147  
   5.148  #define PCI_VENDOR_ID_SGI		0x10a9
   5.149  #define PCI_DEVICE_ID_SGI_IOC3		0x0003
   5.150 +#define PCI_DEVICE_ID_SGI_IOC4		0x100a
   5.151  
   5.152  #define PCI_VENDOR_ID_ACC		0x10aa
   5.153  #define PCI_DEVICE_ID_ACC_2056		0x0000
   5.154 @@ -912,6 +968,8 @@
   5.155  #define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
   5.156  #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
   5.157  #define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
   5.158 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
   5.159 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
   5.160  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
   5.161  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
   5.162  #define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
   5.163 @@ -924,7 +982,9 @@
   5.164  #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
   5.165  #define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
   5.166  #define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
   5.167 +#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
   5.168  #define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
   5.169 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
   5.170  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
   5.171  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
   5.172  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
   5.173 @@ -984,6 +1044,7 @@
   5.174  #define PCI_DEVICE_ID_TTI_HPT302	0x0006
   5.175  #define PCI_DEVICE_ID_TTI_HPT371	0x0007
   5.176  #define PCI_DEVICE_ID_TTI_HPT374	0x0008
   5.177 +#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	// appoarently a 372N variant?
   5.178  
   5.179  #define PCI_VENDOR_ID_VIA		0x1106
   5.180  #define PCI_DEVICE_ID_VIA_8363_0	0x0305
   5.181 @@ -1025,11 +1086,16 @@
   5.182  #define PCI_DEVICE_ID_VIA_8622		0x3102
   5.183  #define PCI_DEVICE_ID_VIA_8233C_0	0x3109
   5.184  #define PCI_DEVICE_ID_VIA_8361		0x3112
   5.185 +#define PCI_DEVICE_ID_VIA_8375		0x3116
   5.186 +#define PCI_DEVICE_ID_VIA_CLE266	0x3123
   5.187  #define PCI_DEVICE_ID_VIA_8233A		0x3147
   5.188 -#define PCI_DEVICE_ID_VIA_P4X333   0x3168
   5.189 -#define PCI_DEVICE_ID_VIA_8235        0x3177
   5.190 -#define PCI_DEVICE_ID_VIA_8377_0  0x3189
   5.191 +#define PCI_DEVICE_ID_VIA_P4M266	0x3148
   5.192 +#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
   5.193 +#define PCI_DEVICE_ID_VIA_P4X333	0x3168
   5.194 +#define PCI_DEVICE_ID_VIA_8235		0x3177
   5.195  #define PCI_DEVICE_ID_VIA_8377_0	0x3189
   5.196 +#define PCI_DEVICE_ID_VIA_K8T400M_0	0x3188
   5.197 +#define PCI_DEVICE_ID_VIA_8237		0x3227
   5.198  #define PCI_DEVICE_ID_VIA_86C100A	0x6100
   5.199  #define PCI_DEVICE_ID_VIA_8231		0x8231
   5.200  #define PCI_DEVICE_ID_VIA_8231_4	0x8235
   5.201 @@ -1128,6 +1194,8 @@
   5.202  #define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
   5.203  #define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
   5.204  #define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
   5.205 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
   5.206 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
   5.207  
   5.208  #define PCI_VENDOR_ID_VMIC		0x114a
   5.209  #define PCI_DEVICE_ID_VMIC_VME		0x7587
   5.210 @@ -1183,6 +1251,7 @@
   5.211  #define PCI_DEVICE_ID_SBE_WANXL400	0x0104
   5.212  
   5.213  #define PCI_VENDOR_ID_TOSHIBA		0x1179
   5.214 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO	0x0102
   5.215  #define PCI_DEVICE_ID_TOSHIBA_601	0x0601
   5.216  #define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
   5.217  #define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
   5.218 @@ -1588,11 +1657,20 @@
   5.219  #define PCI_DEVICE_ID_TIGON3_5703	0x1647
   5.220  #define PCI_DEVICE_ID_TIGON3_5704	0x1648
   5.221  #define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
   5.222 +#define PCI_DEVICE_ID_TIGON3_5705	0x1653
   5.223 +#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
   5.224 +#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
   5.225 +#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
   5.226 +#define PCI_DEVICE_ID_TIGON3_5782	0x1696
   5.227 +#define PCI_DEVICE_ID_TIGON3_5788	0x169c
   5.228  #define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
   5.229  #define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
   5.230  #define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
   5.231  #define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
   5.232  #define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
   5.233 +#define PCI_DEVICE_ID_TIGON3_5901	0x170d
   5.234 +#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
   5.235 +#define PCI_DEVICE_ID_BCM4401		0x4401
   5.236  
   5.237  #define PCI_VENDOR_ID_SYBA		0x1592
   5.238  #define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
   5.239 @@ -1605,11 +1683,13 @@
   5.240  #define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
   5.241  
   5.242  #define PCI_VENDOR_ID_PDC		0x15e9
   5.243 -#define PCI_DEVICE_ID_PDC_1841		0x1841
   5.244 +#define PCI_DEVICE_ID_PDC_ADMA100	0x1841
   5.245  
   5.246  #define PCI_VENDOR_ID_ALTIMA		0x173b
   5.247  #define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
   5.248 +#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
   5.249  #define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
   5.250 +#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
   5.251  
   5.252  #define PCI_VENDOR_ID_SYMPHONY		0x1c1c
   5.253  #define PCI_DEVICE_ID_SYMPHONY_101	0x0001
   5.254 @@ -1638,6 +1718,9 @@
   5.255  #define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
   5.256  #define PCI_DEVICE_ID_AKS_CPC		0x0200
   5.257  
   5.258 +#define PCI_VENDOR_ID_REDCREEK		0x4916
   5.259 +#define PCI_DEVICE_ID_RC45		0x1960
   5.260 +
   5.261  #define PCI_VENDOR_ID_NETVIN		0x4a14
   5.262  #define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
   5.263  
   5.264 @@ -1690,6 +1773,7 @@
   5.265  #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
   5.266  #define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
   5.267  #define PCI_DEVICE_ID_INTEL_7116	0x1223
   5.268 +#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
   5.269  #define PCI_DEVICE_ID_INTEL_82596	0x1226
   5.270  #define PCI_DEVICE_ID_INTEL_82865	0x1227
   5.271  #define PCI_DEVICE_ID_INTEL_82557	0x1229
   5.272 @@ -1702,6 +1786,7 @@
   5.273  #define PCI_DEVICE_ID_INTEL_82380FB	0x124b
   5.274  #define PCI_DEVICE_ID_INTEL_82439	0x1250
   5.275  #define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
   5.276 +#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
   5.277  #define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
   5.278  #define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
   5.279  #define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
   5.280 @@ -1761,8 +1846,37 @@
   5.281  #define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
   5.282  #define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
   5.283  #define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
   5.284 +#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
   5.285  #define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
   5.286 +#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
   5.287  #define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
   5.288 +#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
   5.289 +#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
   5.290 +#define PCI_DEVICE_ID_INTEL_82801EB_2	0x24d2
   5.291 +#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
   5.292 +#define PCI_DEVICE_ID_INTEL_82801EB_4	0x24d4
   5.293 +#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
   5.294 +#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
   5.295 +#define PCI_DEVICE_ID_INTEL_82801EB_7	0x24d7
   5.296 +#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
   5.297 +#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
   5.298 +#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
   5.299 +#define PCI_DEVICE_ID_INTEL_ESB_0	0x25a0
   5.300 +#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
   5.301 +#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
   5.302 +#define PCI_DEVICE_ID_INTEL_ESB_3	0x25a3
   5.303 +#define PCI_DEVICE_ID_INTEL_ESB_31	0x25b0
   5.304 +#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
   5.305 +#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
   5.306 +#define PCI_DEVICE_ID_INTEL_ESB_6	0x25a7
   5.307 +#define PCI_DEVICE_ID_INTEL_ESB_7	0x25a9
   5.308 +#define PCI_DEVICE_ID_INTEL_ESB_8	0x25aa
   5.309 +#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
   5.310 +#define PCI_DEVICE_ID_INTEL_ESB_11	0x25ac
   5.311 +#define PCI_DEVICE_ID_INTEL_ESB_12	0x25ad
   5.312 +#define PCI_DEVICE_ID_INTEL_ESB_13	0x25ae
   5.313 +#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
   5.314 +#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
   5.315  #define PCI_DEVICE_ID_INTEL_80310	0x530d
   5.316  #define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
   5.317  #define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
   5.318 @@ -1777,6 +1891,9 @@
   5.319  #define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
   5.320  #define PCI_DEVICE_ID_INTEL_82443MX_2	0x719a
   5.321  #define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
   5.322 +#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
   5.323 +#define PCI_DEVICE_ID_INTEL_82443GX_1	0x71a1
   5.324 +#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
   5.325  #define PCI_DEVICE_ID_INTEL_82372FB_0	0x7600
   5.326  #define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
   5.327  #define PCI_DEVICE_ID_INTEL_82372FB_2	0x7602