ia64/xen-unstable

changeset 7658:d51b071bfcfc

Enable ar.unat handling for fast paths (by Anthony Xu)
author djm@kirby.fc.hp.com
date Mon Nov 07 16:53:25 2005 -0600 (2005-11-07)
parents b547291cb6d4
children 66dd96e90be4
files xen/arch/ia64/xen/hyperprivop.S
line diff
     1.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Mon Nov 07 11:25:59 2005 -0600
     1.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Mon Nov 07 16:53:25 2005 -0600
     1.3 @@ -59,7 +59,7 @@
     1.4  #endif
     1.5  
     1.6  // FIXME: turn off for now... but NaTs may crash Xen so re-enable soon!
     1.7 -//#define HANDLE_AR_UNAT
     1.8 +#define HANDLE_AR_UNAT
     1.9  
    1.10  // FIXME: This is defined in include/asm-ia64/hw_irq.h but this
    1.11  // doesn't appear to be include'able from assembly?
    1.12 @@ -497,19 +497,29 @@ GLOBAL_ENTRY(fast_tick_reflect)
    1.13  	.mem.offset 0,0; st8.spill [r2]=r30,16;
    1.14  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    1.15  #ifdef HANDLE_AR_UNAT
    1.16 -	// bank0 regs have no NaT bit, so ensure they are NaT clean
    1.17 -	mov r16=r0; mov r17=r0; mov r18=r0; mov r19=r0;
    1.18 -	mov r20=r0; mov r21=r0; mov r22=r0; mov r23=r0;
    1.19 -	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    1.20 -	mov r28=r0; mov r29=r0; mov r30=r0; movl r31=XSI_IPSR;;
    1.21 + 	// r16~r23 are preserved regsin bank0 regs, we need to restore them,
    1.22 +    // r24~r31 are scratch regs, we don't need to handle NaT bit,
    1.23 +    // because OS handler must assign it before access it
    1.24 +    ld8 r16=[r2],16;
    1.25 +    ld8 r17=[r3],16;;
    1.26 +    ld8 r18=[r2],16;
    1.27 +    ld8 r19=[r3],16;;
    1.28 +    ld8 r20=[r2],16;
    1.29 +    ld8 r21=[r3],16;;
    1.30 +    ld8 r22=[r2],16;
    1.31 +    ld8 r23=[r3],16;;
    1.32  #endif
    1.33 -	bsw.0 ;;
    1.34 -	mov r2=r30; mov r3=r29;;
    1.35 +    movl r31=XSI_IPSR;;
    1.36 +    bsw.0 ;;
    1.37 +    mov r24=ar.unat;
    1.38 +    mov r2=r30; mov r3=r29;;
    1.39  #ifdef HANDLE_AR_UNAT
    1.40 -	mov ar.unat=r28;
    1.41 +    mov ar.unat=r28;
    1.42  #endif
    1.43 -	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.44 -	st4 [r20]=r0 ;;
    1.45 +    adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
    1.46 +    adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.47 +    st8 [r25]=r24;
    1.48 +    st4 [r20]=r0 ;;
    1.49  fast_tick_reflect_done:
    1.50  	mov pr=r31,-1 ;;
    1.51  	rfi
    1.52 @@ -651,19 +661,28 @@ ENTRY(fast_reflect)
    1.53  	.mem.offset 0,0; st8.spill [r2]=r30,16;
    1.54  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    1.55  #ifdef HANDLE_AR_UNAT
    1.56 -	// bank0 regs have no NaT bit, so ensure they are NaT clean
    1.57 -	mov r16=r0; mov r17=r0; mov r18=r0; mov r19=r0;
    1.58 -	mov r20=r0; mov r21=r0; mov r22=r0; mov r23=r0;
    1.59 -	mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
    1.60 -	mov r28=r0; mov r29=r0; mov r30=r0; movl r31=XSI_IPSR;;
    1.61 +	// r16~r23 are preserved regsin bank0 regs, we need to restore them,
    1.62 +    // r24~r31 are scratch regs, we don't need to handle NaT bit,
    1.63 +    // because OS handler must assign it before access it
    1.64 +	ld8 r16=[r2],16;
    1.65 +    ld8 r17=[r3],16;;
    1.66 +    ld8 r18=[r2],16;
    1.67 +    ld8 r19=[r3],16;;
    1.68 +	ld8 r20=[r2],16;
    1.69 +    ld8 r21=[r3],16;;
    1.70 +    ld8 r22=[r2],16;
    1.71 +    ld8 r23=[r3],16;;
    1.72  #endif
    1.73  	movl r31=XSI_IPSR;;
    1.74  	bsw.0 ;;
    1.75 +    mov r24=ar.unat;
    1.76  	mov r2=r30; mov r3=r29;;
    1.77  #ifdef HANDLE_AR_UNAT
    1.78  	mov ar.unat=r28;
    1.79  #endif
    1.80 +    adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
    1.81  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.82 +    st8 [r25]=r24;
    1.83  	st4 [r20]=r0 ;;
    1.84  	mov pr=r31,-1 ;;
    1.85  	rfi