ia64/xen-unstable

changeset 19247:d0df93e627bc

xend: Fix some mistakes in tools/python/xend/util/pci.py

1) PCI_PM_CTRL_NO_SOFT_RESET: this is bit3 of PMCSR(Power Management
Control/Status). It should be 8. This bit means a device's capability
of not doing an internal reset across D3hot/D0.
If the bit is 1, there shall be no reset across D3hot/D0, so we should
not use it as a method to reset device.
2) When performing reset using standard FLR methods, we should sleep
at least 100ms; in current code, it's incorrect somewhere we sleep
0.2s and somewhere 0.01s.
3) In detect_dev_info(), fix a typo: PCI_EXP_TYPE_PCI_BRIDG ->
PCI_EXP_FLAGS_TYPE.
4) fix a small typo in the comment of transform_list().

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Mar 02 10:23:50 2009 +0000 (2009-03-02)
parents f8916c9bc149
children 9bc5799566be
files tools/python/xen/util/pci.py
line diff
     1.1 --- a/tools/python/xen/util/pci.py	Mon Mar 02 10:22:23 2009 +0000
     1.2 +++ b/tools/python/xen/util/pci.py	Mon Mar 02 10:23:50 2009 +0000
     1.3 @@ -66,9 +66,10 @@ PCI_EXP_DEVCTL_FLR = (0x1 << 15)
     1.4  
     1.5  PCI_CAP_ID_PM = 0x01
     1.6  PCI_PM_CTRL = 4
     1.7 -PCI_PM_CTRL_NO_SOFT_RESET = 0x0004
     1.8 +PCI_PM_CTRL_NO_SOFT_RESET = 0x0008
     1.9  PCI_PM_CTRL_STATE_MASK = 0x0003
    1.10  PCI_D3hot = 3
    1.11 +PCI_D0hot = 0
    1.12  
    1.13  VENDOR_INTEL  = 0x8086
    1.14  PCI_CAP_ID_VENDOR_SPECIFIC_CAP = 0x09
    1.15 @@ -234,7 +235,7 @@ def find_all_devices_owned_by_pciback():
    1.16      return dev_list
    1.17  
    1.18  def transform_list(target, src):
    1.19 -    ''' src: its element is pci string (Format: xxxx:xx:xx:x).
    1.20 +    ''' src: its element is pci string (Format: xxxx:xx:xx.x).
    1.21          target: its element is pci string, or a list of pci string.
    1.22  
    1.23          If all the elements in src are in target, we remove them from target
    1.24 @@ -467,12 +468,12 @@ class PciDevice:
    1.25          os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
    1.26          br_cntl |= PCI_BRIDGE_CTL_BUS_RESET
    1.27          os.write(fd, struct.pack('H', br_cntl))
    1.28 -        time.sleep(0.200)
    1.29 +        time.sleep(0.100)
    1.30          # De-assert Secondary Bus Reset
    1.31          os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
    1.32          br_cntl &= ~PCI_BRIDGE_CTL_BUS_RESET
    1.33          os.write(fd, struct.pack('H', br_cntl))
    1.34 -        time.sleep(0.200)
    1.35 +        time.sleep(0.100)
    1.36          os.close(fd)
    1.37  
    1.38          # Restore the config spaces
    1.39 @@ -483,18 +484,25 @@ class PciDevice:
    1.40          if pos == 0:
    1.41              return False
    1.42          
    1.43 +        # No_Soft_Reset - When set 1, this bit indicates that
    1.44 +        # devices transitioning from D3hot to D0 because of
    1.45 +        # PowerState commands do not perform an internal reset.
    1.46 +        pm_ctl = self.pci_conf_read32(pos + PCI_PM_CTRL)
    1.47 +        if (pm_ctl & PCI_PM_CTRL_NO_SOFT_RESET) == 1:
    1.48 +            return False
    1.49 +
    1.50          (pci_list, cfg_list) = save_pci_conf_space([self.name])
    1.51          
    1.52 -        # Enter D3hot without soft reset
    1.53 -        pm_ctl = self.pci_conf_read32(pos + PCI_PM_CTRL)
    1.54 -        pm_ctl |= PCI_PM_CTRL_NO_SOFT_RESET
    1.55 +        # Enter D3hot
    1.56          pm_ctl &= ~PCI_PM_CTRL_STATE_MASK
    1.57          pm_ctl |= PCI_D3hot
    1.58          self.pci_conf_write32(pos + PCI_PM_CTRL, pm_ctl)
    1.59          time.sleep(0.010)
    1.60  
    1.61          # From D3hot to D0
    1.62 -        self.pci_conf_write32(pos + PCI_PM_CTRL, 0)
    1.63 +        pm_ctl &= ~PCI_PM_CTRL_STATE_MASK
    1.64 +        pm_ctl |= PCI_D0hot
    1.65 +        self.pci_conf_write32(pos + PCI_PM_CTRL, pm_ctl)
    1.66          time.sleep(0.010)
    1.67  
    1.68          restore_pci_conf_space((pci_list, cfg_list))
    1.69 @@ -516,7 +524,7 @@ class PciDevice:
    1.70          (pci_list, cfg_list) = save_pci_conf_space([self.name])
    1.71  
    1.72          self.pci_conf_write8(pos + PCI_USB_FLRCTRL, 1)
    1.73 -        time.sleep(0.010)
    1.74 +        time.sleep(0.100)
    1.75  
    1.76          restore_pci_conf_space((pci_list, cfg_list))
    1.77  
    1.78 @@ -636,7 +644,7 @@ class PciDevice:
    1.79                  self.dev_type = DEV_TYPE_PCI_BRIDGE
    1.80              else:
    1.81                  creg = self.pci_conf_read16(pos + PCI_EXP_FLAGS)
    1.82 -                if ((creg & PCI_EXP_TYPE_PCI_BRIDGE) >> 4) == \
    1.83 +                if ((creg & PCI_EXP_FLAGS_TYPE) >> 4) == \
    1.84                      PCI_EXP_TYPE_PCI_BRIDGE:
    1.85                      self.dev_type = DEV_TYPE_PCI_BRIDGE
    1.86                  else:
    1.87 @@ -701,7 +709,7 @@ class PciDevice:
    1.88                  pos = self.find_cap_offset(PCI_CAP_ID_EXP)
    1.89                  self.pci_conf_write32(pos + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_FLR)
    1.90                  # We must sleep at least 100ms for the completion of FLR
    1.91 -                time.sleep(0.200)
    1.92 +                time.sleep(0.100)
    1.93                  restore_pci_conf_space((pci_list, cfg_list))
    1.94              else:
    1.95                  if self.bus == 0:
    1.96 @@ -722,7 +730,7 @@ class PciDevice:
    1.97                  # We use Advanced Capability to do FLR.
    1.98                  pos = self.find_cap_offset(PCI_CAP_ID_AF)
    1.99                  self.pci_conf_write8(pos + PCI_AF_CTL, PCI_AF_CTL_FLR)
   1.100 -                time.sleep(0.200)
   1.101 +                time.sleep(0.100)
   1.102                  restore_pci_conf_space((pci_list, cfg_list))
   1.103              else:
   1.104                  if self.bus == 0: